1 // SPDX-License-Identifier: GPL-2.0+
3 * spi driver for rockchip
5 * (C) 2019 Theobroma Systems Design und Consulting GmbH
7 * (C) Copyright 2015 Google, Inc
9 * (C) Copyright 2008-2013 Rockchip Electronics
10 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
16 #include <dt-structs.h>
21 #include <linux/errno.h>
23 #include <asm/arch-rockchip/clock.h>
24 #include <asm/arch-rockchip/periph.h>
25 #include <dm/pinctrl.h>
28 /* Change to 1 to output registers at the start of each transaction */
29 #define DEBUG_RK_SPI 0
32 * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
33 * the controller seems to hang when given 0x10000, so stick with this for now.
35 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
37 struct rockchip_spi_params {
38 /* RXFIFO overruns and TXFIFO underruns stop the master clock */
39 bool master_manages_fifo;
42 struct rockchip_spi_platdata {
43 #if CONFIG_IS_ENABLED(OF_PLATDATA)
44 struct dtd_rockchip_rk3288_spi of_plat;
46 s32 frequency; /* Default clock frequency, -1 for none */
48 uint deactivate_delay_us; /* Delay to wait after deactivate */
49 uint activate_delay_us; /* Delay to wait after activate */
52 struct rockchip_spi_priv {
53 struct rockchip_spi *regs;
55 unsigned int max_freq;
57 ulong last_transaction_us; /* Time of last transaction end */
58 unsigned int speed_hz;
59 unsigned int last_speed_hz;
63 #define SPI_FIFO_DEPTH 32
65 static void rkspi_dump_regs(struct rockchip_spi *regs)
67 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
68 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
69 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
70 debug("ser: \t\t0x%08x\n", readl(®s->ser));
71 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
72 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
73 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
74 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
75 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
76 debug("sr: \t\t0x%08x\n", readl(®s->sr));
77 debug("imr: \t\t0x%08x\n", readl(®s->imr));
78 debug("isr: \t\t0x%08x\n", readl(®s->isr));
79 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
80 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
81 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
84 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
86 writel(enable ? 1 : 0, ®s->enr);
89 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
92 * We should try not to exceed the speed requested by the caller:
93 * when selecting a divider, we need to make sure we round up.
95 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
97 /* The baudrate register (BAUDR) is defined as a 32bit register where
98 * the upper 16bit are reserved and having 'Fsclk_out' in the lower
99 * 16bits with 'Fsclk_out' defined as follows:
101 * Fsclk_out = Fspi_clk/ SCKDV
102 * Where SCKDV is any even value between 2 and 65534.
104 if (clk_div > 0xfffe) {
106 debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
107 __func__, speed, priv->input_rate / clk_div);
110 /* Round up to the next even 16bit number */
111 clk_div = (clk_div + 1) & 0xfffe;
113 debug("spi speed %u, div %u\n", speed, clk_div);
115 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
116 priv->last_speed_hz = speed;
119 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
123 start = get_timer(0);
124 while (readl(®s->sr) & SR_BUSY) {
125 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
126 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
134 static void spi_cs_activate(struct udevice *dev, uint cs)
136 struct udevice *bus = dev->parent;
137 struct rockchip_spi_platdata *plat = bus->platdata;
138 struct rockchip_spi_priv *priv = dev_get_priv(bus);
139 struct rockchip_spi *regs = priv->regs;
141 /* If it's too soon to do another transaction, wait */
142 if (plat->deactivate_delay_us && priv->last_transaction_us) {
143 ulong delay_us; /* The delay completed so far */
144 delay_us = timer_get_us() - priv->last_transaction_us;
145 if (delay_us < plat->deactivate_delay_us) {
146 ulong additional_delay_us =
147 plat->deactivate_delay_us - delay_us;
148 debug("%s: delaying by %ld us\n",
149 __func__, additional_delay_us);
150 udelay(additional_delay_us);
154 debug("activate cs%u\n", cs);
155 writel(1 << cs, ®s->ser);
156 if (plat->activate_delay_us)
157 udelay(plat->activate_delay_us);
160 static void spi_cs_deactivate(struct udevice *dev, uint cs)
162 struct udevice *bus = dev->parent;
163 struct rockchip_spi_platdata *plat = bus->platdata;
164 struct rockchip_spi_priv *priv = dev_get_priv(bus);
165 struct rockchip_spi *regs = priv->regs;
167 debug("deactivate cs%u\n", cs);
168 writel(0, ®s->ser);
170 /* Remember time of this transaction so we can honour the bus delay */
171 if (plat->deactivate_delay_us)
172 priv->last_transaction_us = timer_get_us();
175 #if CONFIG_IS_ENABLED(OF_PLATDATA)
176 static int conv_of_platdata(struct udevice *dev)
178 struct rockchip_spi_platdata *plat = dev->platdata;
179 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
180 struct rockchip_spi_priv *priv = dev_get_priv(dev);
183 plat->base = dtplat->reg[0];
184 plat->frequency = 20000000;
185 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
194 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
196 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
197 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
198 struct rockchip_spi_priv *priv = dev_get_priv(bus);
201 plat->base = dev_read_addr(bus);
203 ret = clk_get_by_index(bus, 0, &priv->clk);
205 debug("%s: Could not get clock for %s: %d\n", __func__,
211 dev_read_u32_default(bus, "spi-max-frequency", 50000000);
212 plat->deactivate_delay_us =
213 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
214 plat->activate_delay_us =
215 dev_read_u32_default(bus, "spi-activate-delay", 0);
217 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
218 __func__, (uint)plat->base, plat->frequency,
219 plat->deactivate_delay_us);
225 static int rockchip_spi_calc_modclk(ulong max_freq)
228 * While this is not strictly correct for the RK3368, as the
229 * GPLL will be 576MHz, things will still work, as the
230 * clk_set_rate(...) implementation in our clock-driver will
231 * chose the next closest rate not exceeding what we request
232 * based on the output of this function.
236 const unsigned long gpll_hz = 594000000UL;
239 * We need to find an input clock that provides at least twice
240 * the maximum frequency and can be generated from the assumed
241 * speed of GPLL (594MHz) using an integer divider.
243 * To give us more achievable bitrates at higher speeds (these
244 * are generated by dividing by an even 16-bit integer from
245 * this frequency), we try to have an input frequency of at
246 * least 4x our max_freq.
249 div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
250 return gpll_hz / div;
253 static int rockchip_spi_probe(struct udevice *bus)
255 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
256 struct rockchip_spi_priv *priv = dev_get_priv(bus);
259 debug("%s: probe\n", __func__);
260 #if CONFIG_IS_ENABLED(OF_PLATDATA)
261 ret = conv_of_platdata(bus);
265 priv->regs = (struct rockchip_spi *)plat->base;
267 priv->last_transaction_us = timer_get_us();
268 priv->max_freq = plat->frequency;
270 /* Clamp the value from the DTS against any hardware limits */
271 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
272 priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
274 /* Find a module-input clock that fits with the max_freq setting */
275 ret = clk_set_rate(&priv->clk,
276 rockchip_spi_calc_modclk(priv->max_freq));
278 debug("%s: Failed to set clock: %d\n", __func__, ret);
281 priv->input_rate = ret;
282 debug("%s: rate = %u\n", __func__, priv->input_rate);
287 static int rockchip_spi_claim_bus(struct udevice *dev)
289 struct udevice *bus = dev->parent;
290 struct rockchip_spi_priv *priv = dev_get_priv(bus);
291 struct rockchip_spi *regs = priv->regs;
294 /* Disable the SPI hardware */
295 rkspi_enable_chip(regs, false);
297 if (priv->speed_hz != priv->last_speed_hz)
298 rkspi_set_clk(priv, priv->speed_hz);
301 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
303 /* Data Frame Size */
304 ctrlr0 |= DFS_8BIT << DFS_SHIFT;
306 /* set SPI mode 0..3 */
307 if (priv->mode & SPI_CPOL)
308 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
309 if (priv->mode & SPI_CPHA)
310 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
312 /* Chip Select Mode */
313 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
315 /* SSN to Sclk_out delay */
316 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
318 /* Serial Endian Mode */
319 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
322 ctrlr0 |= FBM_MSB << FBM_SHIFT;
324 /* Byte and Halfword Transform */
325 ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
327 /* Rxd Sample Delay */
328 ctrlr0 |= 0 << RXDSD_SHIFT;
331 ctrlr0 |= FRF_SPI << FRF_SHIFT;
334 ctrlr0 |= TMOD_TR << TMOD_SHIFT;
336 writel(ctrlr0, ®s->ctrlr0);
341 static int rockchip_spi_release_bus(struct udevice *dev)
343 struct udevice *bus = dev->parent;
344 struct rockchip_spi_priv *priv = dev_get_priv(bus);
346 rkspi_enable_chip(priv->regs, false);
351 static inline int rockchip_spi_16bit_reader(struct udevice *dev,
354 struct udevice *bus = dev->parent;
355 const struct rockchip_spi_params * const data =
356 (void *)dev_get_driver_data(bus);
357 struct rockchip_spi_priv *priv = dev_get_priv(bus);
358 struct rockchip_spi *regs = priv->regs;
359 const u32 saved_ctrlr0 = readl(®s->ctrlr0);
361 u32 statistics_rxlevels[33] = { };
363 u32 frames = *len / 2;
364 u8 *in = (u8 *)(*din);
365 u32 max_chunk_size = SPI_FIFO_DEPTH;
371 * If we know that the hardware will manage RXFIFO overruns
372 * (i.e. stop the SPI clock until there's space in the FIFO),
373 * we the allow largest possible chunk size that can be
374 * represented in CTRLR1.
376 if (data && data->master_manages_fifo)
377 max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;
379 // rockchip_spi_configure(dev, mode, size)
380 rkspi_enable_chip(regs, false);
381 clrsetbits_le32(®s->ctrlr0,
382 TMOD_MASK << TMOD_SHIFT,
383 TMOD_RO << TMOD_SHIFT);
384 /* 16bit data frame size */
385 clrsetbits_le32(®s->ctrlr0, DFS_MASK, DFS_16BIT);
387 /* Update caller's context */
388 const u32 bytes_to_process = 2 * frames;
389 *din += bytes_to_process;
390 *len -= bytes_to_process;
392 /* Process our frames */
394 u32 chunk_size = min(frames, max_chunk_size);
396 frames -= chunk_size;
398 writew(chunk_size - 1, ®s->ctrlr1);
399 rkspi_enable_chip(regs, true);
402 u32 rx_level = readw(®s->rxflr);
404 statistics_rxlevels[rx_level]++;
406 chunk_size -= rx_level;
408 u16 val = readw(regs->rxdr);
412 } while (chunk_size);
414 rkspi_enable_chip(regs, false);
418 debug("%s: observed rx_level during processing:\n", __func__);
419 for (int i = 0; i <= 32; ++i)
420 if (statistics_rxlevels[i])
421 debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
423 /* Restore the original transfer setup and return error-free. */
424 writel(saved_ctrlr0, ®s->ctrlr0);
428 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
429 const void *dout, void *din, unsigned long flags)
431 struct udevice *bus = dev->parent;
432 struct rockchip_spi_priv *priv = dev_get_priv(bus);
433 struct rockchip_spi *regs = priv->regs;
434 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
435 int len = bitlen >> 3;
436 const u8 *out = dout;
441 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
444 rkspi_dump_regs(regs);
446 /* Assert CS before transfer */
447 if (flags & SPI_XFER_BEGIN)
448 spi_cs_activate(dev, slave_plat->cs);
451 * To ensure fast loading of firmware images (e.g. full U-Boot
452 * stage, ATF, Linux kernel) from SPI flash, we optimise the
453 * case of read-only transfers by using the full 16bits of each
457 ret = rockchip_spi_16bit_reader(dev, &in, &len);
459 /* This is the original 8bit reader/writer code */
461 int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);
463 rkspi_enable_chip(regs, false);
464 writel(todo - 1, ®s->ctrlr1);
465 rkspi_enable_chip(regs, true);
469 while (toread || towrite) {
470 u32 status = readl(®s->sr);
472 if (towrite && !(status & SR_TF_FULL)) {
473 writel(out ? *out++ : 0, regs->txdr);
476 if (toread && !(status & SR_RF_EMPT)) {
477 u32 byte = readl(regs->rxdr);
486 * In case that there's a transmit-component, we need to wait
487 * until the control goes idle before we can disable the SPI
488 * control logic (as this will implictly flush the FIFOs).
491 ret = rkspi_wait_till_not_busy(regs);
499 /* Deassert CS after transfer */
500 if (flags & SPI_XFER_END)
501 spi_cs_deactivate(dev, slave_plat->cs);
503 rkspi_enable_chip(regs, false);
508 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
510 struct rockchip_spi_priv *priv = dev_get_priv(bus);
512 /* Clamp to the maximum frequency specified in the DTS */
513 if (speed > priv->max_freq)
514 speed = priv->max_freq;
516 priv->speed_hz = speed;
521 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
523 struct rockchip_spi_priv *priv = dev_get_priv(bus);
530 static const struct dm_spi_ops rockchip_spi_ops = {
531 .claim_bus = rockchip_spi_claim_bus,
532 .release_bus = rockchip_spi_release_bus,
533 .xfer = rockchip_spi_xfer,
534 .set_speed = rockchip_spi_set_speed,
535 .set_mode = rockchip_spi_set_mode,
537 * cs_info is not needed, since we require all chip selects to be
538 * in the device tree explicitly
542 const struct rockchip_spi_params rk3399_spi_params = {
543 .master_manages_fifo = true,
546 static const struct udevice_id rockchip_spi_ids[] = {
547 { .compatible = "rockchip,rk3288-spi" },
548 { .compatible = "rockchip,rk3368-spi",
549 .data = (ulong)&rk3399_spi_params },
550 { .compatible = "rockchip,rk3399-spi",
551 .data = (ulong)&rk3399_spi_params },
555 U_BOOT_DRIVER(rockchip_spi) = {
556 #if CONFIG_IS_ENABLED(OF_PLATDATA)
557 .name = "rockchip_rk3288_spi",
559 .name = "rockchip_spi",
562 .of_match = rockchip_spi_ids,
563 .ops = &rockchip_spi_ops,
564 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
565 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
566 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
567 .probe = rockchip_spi_probe,