1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
11 #include <dm/device_compat.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/mach-imx/spi.h>
20 DECLARE_GLOBAL_DATA_PTR;
23 /* i.MX27 has a completely wrong register layout and register definitions in the
24 * datasheet, the correct one is in the Freescale's Linux driver */
26 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
27 "See linux mxc_spi driver from Freescale for details."
30 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
35 #define OUT MXC_GPIO_DIRECTION_OUT
37 #define reg_read readl
38 #define reg_write(a, v) writel(v, a)
40 #if !defined(CONFIG_SYS_SPI_MXC_WAIT)
41 #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
44 #define MAX_CS_COUNT 4
46 struct mxc_spi_slave {
47 struct spi_slave slave;
50 #if defined(MXC_ECSPI)
58 struct gpio_desc cs_gpios[MAX_CS_COUNT];
62 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
64 return container_of(slave, struct mxc_spi_slave, slave);
67 static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
69 #if defined(CONFIG_DM_SPI)
70 struct udevice *dev = mxcs->dev;
71 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
73 u32 cs = slave_plat->cs;
75 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
78 dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
81 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
85 static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
87 #if defined(CONFIG_DM_SPI)
88 struct udevice *dev = mxcs->dev;
89 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
91 u32 cs = slave_plat->cs;
93 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
96 dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
99 gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
103 u32 get_cspi_div(u32 div)
107 for (i = 0; i < 8; i++) {
115 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
117 unsigned int ctrl_reg;
120 unsigned int max_hz = mxcs->max_hz;
121 unsigned int mode = mxcs->mode;
123 clk_src = mxc_get_clock(MXC_CSPI_CLK);
125 div = DIV_ROUND_UP(clk_src, max_hz);
126 div = get_cspi_div(div);
128 debug("clk %d Hz, div %d, real clk %d Hz\n",
129 max_hz, div, clk_src / (4 << div));
131 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
132 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
133 MXC_CSPICTRL_DATARATE(div) |
141 ctrl_reg |= MXC_CSPICTRL_PHA;
143 ctrl_reg |= MXC_CSPICTRL_POL;
144 if (mode & SPI_CS_HIGH)
145 ctrl_reg |= MXC_CSPICTRL_SSPOL;
146 mxcs->ctrl_reg = ctrl_reg;
153 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
155 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
156 s32 reg_ctrl, reg_config;
157 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
158 u32 pre_div = 0, post_div = 0;
159 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
160 unsigned int max_hz = mxcs->max_hz;
161 unsigned int mode = mxcs->mode;
164 * Reset SPI and set all CSs to master mode, if toggling
165 * between slave and master mode we might see a glitch
168 reg_ctrl = MXC_CSPICTRL_MODE_MASK;
169 reg_write(®s->ctrl, reg_ctrl);
170 reg_ctrl |= MXC_CSPICTRL_EN;
171 reg_write(®s->ctrl, reg_ctrl);
173 if (clk_src > max_hz) {
174 pre_div = (clk_src - 1) / max_hz;
175 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
176 post_div = fls(pre_div);
179 if (post_div >= 16) {
180 printf("Error: no divider for the freq: %d\n",
184 pre_div >>= post_div;
190 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
191 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
192 MXC_CSPICTRL_SELCHAN(cs);
193 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
194 MXC_CSPICTRL_PREDIV(pre_div);
195 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
196 MXC_CSPICTRL_POSTDIV(post_div);
198 if (mode & SPI_CS_HIGH)
201 if (mode & SPI_CPOL) {
209 reg_config = reg_read(®s->cfg);
212 * Configuration register setup
213 * The MX51 supports different setup for each SS
215 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
216 (ss_pol << (cs + MXC_CSPICON_SSPOL));
217 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
218 (sclkpol << (cs + MXC_CSPICON_POL));
219 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
220 (sclkctl << (cs + MXC_CSPICON_CTL));
221 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
222 (sclkpha << (cs + MXC_CSPICON_PHA));
224 debug("reg_ctrl = 0x%x\n", reg_ctrl);
225 reg_write(®s->ctrl, reg_ctrl);
226 debug("reg_config = 0x%x\n", reg_config);
227 reg_write(®s->cfg, reg_config);
229 /* save config register and control register */
230 mxcs->ctrl_reg = reg_ctrl;
231 mxcs->cfg_reg = reg_config;
233 /* clear interrupt reg */
234 reg_write(®s->intr, 0);
235 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
241 int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
242 const u8 *dout, u8 *din, unsigned long flags)
244 int nbytes = DIV_ROUND_UP(bitlen, 8);
246 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
250 debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
251 __func__, bitlen, (ulong)dout, (ulong)din);
253 mxcs->ctrl_reg = (mxcs->ctrl_reg &
254 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
255 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
257 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
259 reg_write(®s->cfg, mxcs->cfg_reg);
262 /* Clear interrupt register */
263 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
266 * The SPI controller works only with words,
267 * check if less than a word is sent.
268 * Access to the FIFO is only 32 bit
272 cnt = (bitlen % 32) / 8;
274 for (i = 0; i < cnt; i++) {
275 data = (data << 8) | (*dout++ & 0xFF);
278 debug("Sending SPI 0x%x\n", data);
280 reg_write(®s->txdata, data);
289 /* Buffer is not 32-bit aligned */
290 if ((unsigned long)dout & 0x03) {
292 for (i = 0; i < 4; i++)
293 data = (data << 8) | (*dout++ & 0xFF);
296 data = cpu_to_be32(data);
300 debug("Sending SPI 0x%x\n", data);
301 reg_write(®s->txdata, data);
305 /* FIFO is written, now starts the transfer setting the XCH bit */
306 reg_write(®s->ctrl, mxcs->ctrl_reg |
307 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
310 status = reg_read(®s->stat);
311 /* Wait until the TC (Transfer completed) bit is set */
312 while ((status & MXC_CSPICTRL_TC) == 0) {
313 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
314 printf("spi_xchg_single: Timeout!\n");
317 status = reg_read(®s->stat);
320 /* Transfer completed, clear any pending request */
321 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
323 nbytes = DIV_ROUND_UP(bitlen, 8);
328 data = reg_read(®s->rxdata);
329 cnt = (bitlen % 32) / 8;
330 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
331 debug("SPI Rx unaligned: 0x%x\n", data);
333 memcpy(din, &data, cnt);
341 tmp = reg_read(®s->rxdata);
342 data = cpu_to_be32(tmp);
343 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
344 cnt = min_t(u32, nbytes, sizeof(data));
346 memcpy(din, &data, cnt);
356 static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
357 unsigned int bitlen, const void *dout,
358 void *din, unsigned long flags)
360 int n_bytes = DIV_ROUND_UP(bitlen, 8);
364 u8 *p_outbuf = (u8 *)dout;
365 u8 *p_inbuf = (u8 *)din;
370 if (flags & SPI_XFER_BEGIN)
371 mxc_spi_cs_activate(mxcs);
373 while (n_bytes > 0) {
374 if (n_bytes < MAX_SPI_BYTES)
377 blk_size = MAX_SPI_BYTES;
379 n_bits = blk_size * 8;
381 ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
386 p_outbuf += blk_size;
392 if (flags & SPI_XFER_END) {
393 mxc_spi_cs_deactivate(mxcs);
399 static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
401 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
404 reg_write(®s->rxdata, 1);
406 ret = spi_cfg_mxc(mxcs, cs);
408 printf("mxc_spi: cannot setup SPI controller\n");
411 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
412 reg_write(®s->intr, 0);
417 #ifndef CONFIG_DM_SPI
418 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
419 void *din, unsigned long flags)
421 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
423 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
427 * Some SPI devices require active chip-select over multiple
428 * transactions, we achieve this using a GPIO. Still, the SPI
429 * controller has to be configured to use one of its own chipselects.
430 * To use this feature you have to implement board_spi_cs_gpio() to assign
431 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
432 * You must use some unused on this SPI controller cs between 0 and 3.
434 static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
435 unsigned int bus, unsigned int cs)
439 mxcs->gpio = board_spi_cs_gpio(bus, cs);
440 if (mxcs->gpio == -1)
443 gpio_request(mxcs->gpio, "spi-cs");
444 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
446 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
453 static unsigned long spi_bases[] = {
454 MXC_SPI_BASE_ADDRESSES
457 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
458 unsigned int max_hz, unsigned int mode)
460 struct mxc_spi_slave *mxcs;
463 if (bus >= ARRAY_SIZE(spi_bases))
467 printf("Error: desired clock is 0\n");
471 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
473 puts("mxc_spi: SPI Slave not allocated !\n");
477 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
479 ret = setup_cs_gpio(mxcs, bus, cs);
485 mxcs->base = spi_bases[bus];
486 mxcs->max_hz = max_hz;
492 void spi_free_slave(struct spi_slave *slave)
494 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
499 int spi_claim_bus(struct spi_slave *slave)
501 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
503 return mxc_spi_claim_bus_internal(mxcs, slave->cs);
506 void spi_release_bus(struct spi_slave *slave)
508 /* TODO: Shut the controller down */
512 static int mxc_spi_probe(struct udevice *bus)
514 struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
515 int node = dev_of_offset(bus);
516 const void *blob = gd->fdt_blob;
520 ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
521 ARRAY_SIZE(mxcs->cs_gpios), 0);
523 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
527 for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
528 if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
531 ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
532 GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
534 dev_err(bus, "Setting cs %d error\n", i);
539 mxcs->base = devfdt_get_addr(bus);
540 if (mxcs->base == FDT_ADDR_T_NONE)
543 mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
549 static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
550 const void *dout, void *din, unsigned long flags)
552 struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
555 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
558 static int mxc_spi_claim_bus(struct udevice *dev)
560 struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
561 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
565 return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
568 static int mxc_spi_release_bus(struct udevice *dev)
573 static int mxc_spi_set_speed(struct udevice *bus, uint speed)
579 static int mxc_spi_set_mode(struct udevice *bus, uint mode)
581 struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
584 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
589 static const struct dm_spi_ops mxc_spi_ops = {
590 .claim_bus = mxc_spi_claim_bus,
591 .release_bus = mxc_spi_release_bus,
592 .xfer = mxc_spi_xfer,
593 .set_speed = mxc_spi_set_speed,
594 .set_mode = mxc_spi_set_mode,
597 static const struct udevice_id mxc_spi_ids[] = {
598 { .compatible = "fsl,imx51-ecspi" },
602 U_BOOT_DRIVER(mxc_spi) = {
605 .of_match = mxc_spi_ids,
607 .platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
608 .probe = mxc_spi_probe,