1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012 SAMSUNG Electronics
4 * Padmavathi Venna <padma.v@samsung.com>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/pinmux.h>
20 #include <asm/arch/spi.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 struct exynos_spi_platdata {
26 enum periph_id periph_id;
27 s32 frequency; /* Default clock frequency, -1 for none */
28 struct exynos_spi *regs;
29 uint deactivate_delay_us; /* Delay to wait after deactivate */
32 struct exynos_spi_priv {
33 struct exynos_spi *regs;
34 unsigned int freq; /* Default frequency */
36 enum periph_id periph_id; /* Peripheral ID for this device */
37 unsigned int fifo_size;
39 ulong last_transaction_us; /* Time of last transaction end */
43 * Flush spi tx, rx fifos and reset the SPI controller
45 * @param regs Pointer to SPI registers
47 static void spi_flush_fifo(struct exynos_spi *regs)
49 clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
50 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
51 setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
54 static void spi_get_fifo_levels(struct exynos_spi *regs,
55 int *rx_lvl, int *tx_lvl)
57 uint32_t spi_sts = readl(®s->spi_sts);
59 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
60 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
64 * If there's something to transfer, do a software reset and set a
67 * @param regs SPI peripheral registers
68 * @param count Number of bytes to transfer
69 * @param step Number of bytes to transfer in each packet (1 or 4)
71 static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
73 debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
75 /* For word address we need to swap bytes */
77 setbits_le32(®s->mode_cfg,
78 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
80 setbits_le32(®s->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN |
81 SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP |
82 SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
84 /* Select byte access and clear the swap configuration */
85 clrbits_le32(®s->mode_cfg,
86 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
87 writel(0, ®s->swap_cfg);
90 assert(count && count < (1 << 16));
91 setbits_le32(®s->ch_cfg, SPI_CH_RST);
92 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
94 writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
97 static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
98 void **dinp, void const **doutp, unsigned long flags)
100 struct exynos_spi *regs = priv->regs;
102 const uchar *txp = *doutp;
104 uint out_bytes, in_bytes;
106 unsigned start = get_timer(0);
110 out_bytes = in_bytes = todo;
112 stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
113 !(priv->mode & SPI_SLAVE);
116 * Try to transfer words if we can. This helps read performance at
117 * SPI clock speeds above about 20MHz.
120 if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
121 !priv->skip_preamble)
125 * If there's something to send, do a software reset and set a
128 spi_request_bytes(regs, todo, step);
131 * Bytes are transmitted/received in pairs. Wait to receive all the
132 * data because then transmission will be done as well.
139 /* Keep the fifos full/empty. */
140 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
143 * Don't completely fill the txfifo, since we don't want our
144 * rxfifo to overflow, and it may already contain data.
146 while (tx_lvl < priv->fifo_size/2 && out_bytes) {
150 temp = *(uint32_t *)txp;
153 writel(temp, ®s->tx_data);
159 if (rx_lvl >= step) {
160 while (rx_lvl >= step) {
161 temp = readl(®s->rx_data);
162 if (priv->skip_preamble) {
163 if (temp == SPI_PREAMBLE_END_BYTE) {
164 priv->skip_preamble = 0;
168 if (rxp || stopping) {
170 *(uint32_t *)rxp = temp;
180 } else if (!toread) {
182 * We have run out of input data, but haven't read
183 * enough bytes after the preamble yet. Read some more,
184 * and make sure that we transmit dummy bytes too, to
188 out_bytes = in_bytes;
191 spi_request_bytes(regs, toread, step);
193 if (priv->skip_preamble && get_timer(start) > 100) {
194 debug("SPI timeout: in_bytes=%d, out_bytes=%d, ",
195 in_bytes, out_bytes);
207 * Activate the CS by driving it LOW
209 * @param slave Pointer to spi_slave to which controller has to
212 static void spi_cs_activate(struct udevice *dev)
214 struct udevice *bus = dev->parent;
215 struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
216 struct exynos_spi_priv *priv = dev_get_priv(bus);
218 /* If it's too soon to do another transaction, wait */
219 if (pdata->deactivate_delay_us &&
220 priv->last_transaction_us) {
221 ulong delay_us; /* The delay completed so far */
222 delay_us = timer_get_us() - priv->last_transaction_us;
223 if (delay_us < pdata->deactivate_delay_us)
224 udelay(pdata->deactivate_delay_us - delay_us);
227 clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
228 debug("Activate CS, bus '%s'\n", bus->name);
229 priv->skip_preamble = priv->mode & SPI_PREAMBLE;
233 * Deactivate the CS by driving it HIGH
235 * @param slave Pointer to spi_slave to which controller has to
238 static void spi_cs_deactivate(struct udevice *dev)
240 struct udevice *bus = dev->parent;
241 struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
242 struct exynos_spi_priv *priv = dev_get_priv(bus);
244 setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
246 /* Remember time of this transaction so we can honour the bus delay */
247 if (pdata->deactivate_delay_us)
248 priv->last_transaction_us = timer_get_us();
250 debug("Deactivate CS, bus '%s'\n", bus->name);
253 static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
255 struct exynos_spi_platdata *plat = bus->platdata;
256 const void *blob = gd->fdt_blob;
257 int node = dev_of_offset(bus);
259 plat->regs = (struct exynos_spi *)devfdt_get_addr(bus);
260 plat->periph_id = pinmux_decode_periph_id(blob, node);
262 if (plat->periph_id == PERIPH_ID_NONE) {
263 debug("%s: Invalid peripheral ID %d\n", __func__,
265 return -FDT_ERR_NOTFOUND;
268 /* Use 500KHz as a suitable default */
269 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
271 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
272 "spi-deactivate-delay", 0);
273 debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
274 __func__, plat->regs, plat->periph_id, plat->frequency,
275 plat->deactivate_delay_us);
280 static int exynos_spi_probe(struct udevice *bus)
282 struct exynos_spi_platdata *plat = dev_get_platdata(bus);
283 struct exynos_spi_priv *priv = dev_get_priv(bus);
285 priv->regs = plat->regs;
286 if (plat->periph_id == PERIPH_ID_SPI1 ||
287 plat->periph_id == PERIPH_ID_SPI2)
288 priv->fifo_size = 64;
290 priv->fifo_size = 256;
292 priv->skip_preamble = 0;
293 priv->last_transaction_us = timer_get_us();
294 priv->freq = plat->frequency;
295 priv->periph_id = plat->periph_id;
300 static int exynos_spi_claim_bus(struct udevice *dev)
302 struct udevice *bus = dev->parent;
303 struct exynos_spi_priv *priv = dev_get_priv(bus);
305 exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
306 spi_flush_fifo(priv->regs);
308 writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
313 static int exynos_spi_release_bus(struct udevice *dev)
315 struct udevice *bus = dev->parent;
316 struct exynos_spi_priv *priv = dev_get_priv(bus);
318 spi_flush_fifo(priv->regs);
323 static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
324 const void *dout, void *din, unsigned long flags)
326 struct udevice *bus = dev->parent;
327 struct exynos_spi_priv *priv = dev_get_priv(bus);
332 /* spi core configured to do 8 bit transfers */
334 debug("Non byte aligned SPI transfer.\n");
338 /* Start the transaction, if necessary. */
339 if ((flags & SPI_XFER_BEGIN))
340 spi_cs_activate(dev);
343 * Exynos SPI limits each transfer to 65535 transfers. To keep
344 * things simple, allow a maximum of 65532 bytes. We could allow
345 * more in word mode, but the performance difference is small.
347 bytelen = bitlen / 8;
348 for (upto = 0; !ret && upto < bytelen; upto += todo) {
349 todo = min(bytelen - upto, (1 << 16) - 4);
350 ret = spi_rx_tx(priv, todo, &din, &dout, flags);
355 /* Stop the transaction, if necessary. */
356 if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
357 spi_cs_deactivate(dev);
358 if (priv->skip_preamble) {
359 assert(!priv->skip_preamble);
360 debug("Failed to complete premable transaction\n");
368 static int exynos_spi_set_speed(struct udevice *bus, uint speed)
370 struct exynos_spi_platdata *plat = bus->platdata;
371 struct exynos_spi_priv *priv = dev_get_priv(bus);
374 if (speed > plat->frequency)
375 speed = plat->frequency;
376 ret = set_spi_clk(priv->periph_id, speed);
380 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
385 static int exynos_spi_set_mode(struct udevice *bus, uint mode)
387 struct exynos_spi_priv *priv = dev_get_priv(bus);
390 reg = readl(&priv->regs->ch_cfg);
391 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
394 reg |= SPI_CH_CPHA_B;
397 reg |= SPI_CH_CPOL_L;
399 writel(reg, &priv->regs->ch_cfg);
401 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
406 static const struct dm_spi_ops exynos_spi_ops = {
407 .claim_bus = exynos_spi_claim_bus,
408 .release_bus = exynos_spi_release_bus,
409 .xfer = exynos_spi_xfer,
410 .set_speed = exynos_spi_set_speed,
411 .set_mode = exynos_spi_set_mode,
413 * cs_info is not needed, since we require all chip selects to be
414 * in the device tree explicitly
418 static const struct udevice_id exynos_spi_ids[] = {
419 { .compatible = "samsung,exynos-spi" },
423 U_BOOT_DRIVER(exynos_spi) = {
424 .name = "exynos_spi",
426 .of_match = exynos_spi_ids,
427 .ops = &exynos_spi_ops,
428 .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
429 .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
430 .priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
431 .probe = exynos_spi_probe,