1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 * Driver for SPI controller on DaVinci. Based on atmel_spi.c
8 * Copyright (C) 2007 Atmel Corporation
16 #include <asm/arch/hardware.h>
18 #include <dm/platform_data/spi_davinci.h>
19 #include <linux/delay.h>
22 #define SPIGCR0_SPIENA_MASK 0x1
23 #define SPIGCR0_SPIRST_MASK 0x0
26 #define SPIGCR1_CLKMOD_MASK BIT(1)
27 #define SPIGCR1_MASTER_MASK BIT(0)
28 #define SPIGCR1_SPIENA_MASK BIT(24)
31 #define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
32 #define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
33 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
34 #define SPIPC0_EN0FUN_MASK BIT(0)
37 #define SPIFMT_SHIFTDIR_SHIFT 20
38 #define SPIFMT_POLARITY_SHIFT 17
39 #define SPIFMT_PHASE_SHIFT 16
40 #define SPIFMT_PRESCALE_SHIFT 8
43 #define SPIDAT1_CSHOLD_SHIFT 28
44 #define SPIDAT1_CSNR_SHIFT 16
47 #define SPI_C2TDELAY_SHIFT 24
48 #define SPI_T2CDELAY_SHIFT 16
51 #define SPIBUF_RXEMPTY_MASK BIT(31)
52 #define SPIBUF_TXFULL_MASK BIT(29)
55 #define SPIDEF_CSDEF0_MASK BIT(0)
59 #define SPI0_BASE CONFIG_SYS_SPI_BASE
61 * Define default SPI0_NUM_CS as 1 for existing platforms that uses this
62 * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
63 * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
65 #ifndef CONFIG_SYS_SPI0
68 #define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS
72 * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
73 * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
75 #ifdef CONFIG_SYS_SPI1
77 #define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS
78 #define SPI1_BASE CONFIG_SYS_SPI1_BASE
82 * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
83 * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
85 #ifdef CONFIG_SYS_SPI2
87 #define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
88 #define SPI2_BASE CONFIG_SYS_SPI2_BASE
92 DECLARE_GLOBAL_DATA_PTR;
94 /* davinci spi register set */
95 struct davinci_spi_regs {
96 dv_reg gcr0; /* 0x00 */
97 dv_reg gcr1; /* 0x04 */
98 dv_reg int0; /* 0x08 */
99 dv_reg lvl; /* 0x0c */
100 dv_reg flg; /* 0x10 */
101 dv_reg pc0; /* 0x14 */
102 dv_reg pc1; /* 0x18 */
103 dv_reg pc2; /* 0x1c */
104 dv_reg pc3; /* 0x20 */
105 dv_reg pc4; /* 0x24 */
106 dv_reg pc5; /* 0x28 */
108 dv_reg dat0; /* 0x38 */
109 dv_reg dat1; /* 0x3c */
110 dv_reg buf; /* 0x40 */
111 dv_reg emu; /* 0x44 */
112 dv_reg delay; /* 0x48 */
113 dv_reg def; /* 0x4c */
114 dv_reg fmt0; /* 0x50 */
115 dv_reg fmt1; /* 0x54 */
116 dv_reg fmt2; /* 0x58 */
117 dv_reg fmt3; /* 0x5c */
118 dv_reg intvec0; /* 0x60 */
119 dv_reg intvec1; /* 0x64 */
122 /* davinci spi slave */
123 struct davinci_spi_slave {
124 #ifndef CONFIG_DM_SPI
125 struct spi_slave slave;
127 struct davinci_spi_regs *regs;
128 unsigned int freq; /* current SPI bus frequency */
129 unsigned int mode; /* current SPI mode used */
130 u8 num_cs; /* total no. of CS available */
131 u8 cur_cs; /* CS of current slave */
132 bool half_duplex; /* true, if master is half-duplex only */
136 * This functions needs to act like a macro to avoid pipeline reloads in the
137 * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
138 * appears to be zero bytes (da830).
140 __attribute__((always_inline))
141 static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
146 writel(data, &ds->regs->dat1);
148 /* wait for the data to clock in/out */
149 while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
155 static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len,
156 u8 *rxp, unsigned long flags)
158 unsigned int data1_reg_val;
160 /* enable CS hold, CS[n] and clear the data bits */
161 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
162 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
164 /* wait till TXFULL is deasserted */
165 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
168 /* preload the TX buffer to avoid clock starvation */
169 writel(data1_reg_val, &ds->regs->dat1);
171 /* keep reading 1 byte until only 1 byte left */
173 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
175 /* clear CS hold when we reach the end */
176 if (flags & SPI_XFER_END)
177 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
179 /* read the last byte */
180 *rxp = davinci_spi_xfer_data(ds, data1_reg_val);
185 static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len,
186 const u8 *txp, unsigned long flags)
188 unsigned int data1_reg_val;
190 /* enable CS hold and clear the data bits */
191 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
192 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
194 /* wait till TXFULL is deasserted */
195 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
198 /* preload the TX buffer to avoid clock starvation */
200 writel(data1_reg_val | *txp++, &ds->regs->dat1);
204 /* keep writing 1 byte until only 1 byte left */
206 davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
208 /* clear CS hold when we reach the end */
209 if (flags & SPI_XFER_END)
210 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
212 /* write the last byte */
213 davinci_spi_xfer_data(ds, data1_reg_val | *txp);
218 static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned
219 int len, u8 *rxp, const u8 *txp,
222 unsigned int data1_reg_val;
224 /* enable CS hold and clear the data bits */
225 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
226 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
228 /* wait till TXFULL is deasserted */
229 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
232 /* keep reading and writing 1 byte until only 1 byte left */
234 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
236 /* clear CS hold when we reach the end */
237 if (flags & SPI_XFER_END)
238 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
240 /* read and write the last byte */
241 *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
247 static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
249 unsigned int mode = 0, scalar;
251 /* Enable the SPI hardware */
252 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
254 writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
256 /* Set master mode, powered up and not activated */
257 writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
259 /* CS, CLK, SIMO and SOMI are functional pins */
260 writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
261 SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
264 scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
267 * Use following format:
268 * character length = 8,
269 * MSB shifted out first
271 if (ds->mode & SPI_CPOL)
273 if (!(ds->mode & SPI_CPHA))
275 writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
276 (mode << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
279 * Including a minor delay. No science here. Should be good even with
282 writel((50 << SPI_C2TDELAY_SHIFT) |
283 (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
285 /* default chip select register */
286 writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
289 writel(0, &ds->regs->int0);
290 writel(0, &ds->regs->lvl);
293 writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
298 static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
300 /* Disable the SPI hardware */
301 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
306 static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
307 unsigned int bitlen, const void *dout, void *din,
313 /* Finish any previously submitted transfers */
317 * It's not clear how non-8-bit-aligned transfers are supposed to be
318 * represented as a stream of bytes...this is a limitation of
319 * the current SPI interface - here we terminate on receiving such a
323 /* Errors always terminate an ongoing transfer */
324 flags |= SPI_XFER_END;
331 return davinci_spi_read(ds, len, din, flags);
333 return davinci_spi_write(ds, len, dout, flags);
334 if (!ds->half_duplex)
335 return davinci_spi_read_write(ds, len, din, dout, flags);
337 printf("SPI full duplex not supported\n");
338 flags |= SPI_XFER_END;
341 if (flags & SPI_XFER_END) {
343 davinci_spi_write(ds, 1, &dummy, flags);
348 #ifndef CONFIG_DM_SPI
350 static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
352 return container_of(slave, struct davinci_spi_slave, slave);
355 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
361 if (cs < SPI0_NUM_CS)
364 #ifdef CONFIG_SYS_SPI1
366 if (cs < SPI1_NUM_CS)
370 #ifdef CONFIG_SYS_SPI2
372 if (cs < SPI2_NUM_CS)
377 /* Invalid bus number. Do nothing */
383 void spi_cs_activate(struct spi_slave *slave)
388 void spi_cs_deactivate(struct spi_slave *slave)
393 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
394 unsigned int max_hz, unsigned int mode)
396 struct davinci_spi_slave *ds;
398 if (!spi_cs_is_valid(bus, cs))
401 ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
407 ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
409 #ifdef CONFIG_SYS_SPI1
411 ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
414 #ifdef CONFIG_SYS_SPI2
416 ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
419 default: /* Invalid bus number */
429 void spi_free_slave(struct spi_slave *slave)
431 struct davinci_spi_slave *ds = to_davinci_spi(slave);
436 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
437 const void *dout, void *din, unsigned long flags)
439 struct davinci_spi_slave *ds = to_davinci_spi(slave);
441 ds->cur_cs = slave->cs;
443 return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
446 int spi_claim_bus(struct spi_slave *slave)
448 struct davinci_spi_slave *ds = to_davinci_spi(slave);
450 #ifdef CONFIG_SPI_HALF_DUPLEX
451 ds->half_duplex = true;
453 ds->half_duplex = false;
455 return __davinci_spi_claim_bus(ds, ds->slave.cs);
458 void spi_release_bus(struct spi_slave *slave)
460 struct davinci_spi_slave *ds = to_davinci_spi(slave);
462 __davinci_spi_release_bus(ds);
466 static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
468 struct davinci_spi_slave *ds = dev_get_priv(bus);
470 debug("%s speed %u\n", __func__, max_hz);
471 if (max_hz > CONFIG_SYS_SPI_CLK / 2)
479 static int davinci_spi_set_mode(struct udevice *bus, uint mode)
481 struct davinci_spi_slave *ds = dev_get_priv(bus);
483 debug("%s mode %u\n", __func__, mode);
489 static int davinci_spi_claim_bus(struct udevice *dev)
491 struct dm_spi_slave_platdata *slave_plat =
492 dev_get_parent_platdata(dev);
493 struct udevice *bus = dev->parent;
494 struct davinci_spi_slave *ds = dev_get_priv(bus);
496 if (slave_plat->cs >= ds->num_cs) {
497 printf("Invalid SPI chipselect\n");
500 ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
502 return __davinci_spi_claim_bus(ds, slave_plat->cs);
505 static int davinci_spi_release_bus(struct udevice *dev)
507 struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
509 return __davinci_spi_release_bus(ds);
512 static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
513 const void *dout, void *din,
516 struct dm_spi_slave_platdata *slave =
517 dev_get_parent_platdata(dev);
518 struct udevice *bus = dev->parent;
519 struct davinci_spi_slave *ds = dev_get_priv(bus);
521 if (slave->cs >= ds->num_cs) {
522 printf("Invalid SPI chipselect\n");
525 ds->cur_cs = slave->cs;
527 return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
530 static const struct dm_spi_ops davinci_spi_ops = {
531 .claim_bus = davinci_spi_claim_bus,
532 .release_bus = davinci_spi_release_bus,
533 .xfer = davinci_spi_xfer,
534 .set_speed = davinci_spi_set_speed,
535 .set_mode = davinci_spi_set_mode,
538 static int davinci_spi_probe(struct udevice *bus)
540 struct davinci_spi_slave *ds = dev_get_priv(bus);
541 struct davinci_spi_platdata *plat = bus->platdata;
542 ds->regs = plat->regs;
543 ds->num_cs = plat->num_cs;
548 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
549 static int davinci_ofdata_to_platadata(struct udevice *bus)
551 struct davinci_spi_platdata *plat = bus->platdata;
554 addr = devfdt_get_addr(bus);
555 if (addr == FDT_ADDR_T_NONE)
558 plat->regs = (struct davinci_spi_regs *)addr;
559 plat->num_cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "num-cs", 4);
564 static const struct udevice_id davinci_spi_ids[] = {
565 { .compatible = "ti,keystone-spi" },
566 { .compatible = "ti,dm6441-spi" },
567 { .compatible = "ti,da830-spi" },
572 U_BOOT_DRIVER(davinci_spi) = {
573 .name = "davinci_spi",
575 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
576 .of_match = davinci_spi_ids,
577 .ofdata_to_platdata = davinci_ofdata_to_platadata,
578 .platdata_auto_alloc_size = sizeof(struct davinci_spi_platdata),
580 .probe = davinci_spi_probe,
581 .ops = &davinci_spi_ops,
582 .priv_auto_alloc_size = sizeof(struct davinci_spi_slave),