1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 * Driver for SPI controller on DaVinci. Based on atmel_spi.c
8 * Copyright (C) 2007 Atmel Corporation
16 #include <asm/arch/hardware.h>
18 #include <dm/platform_data/spi_davinci.h>
21 #define SPIGCR0_SPIENA_MASK 0x1
22 #define SPIGCR0_SPIRST_MASK 0x0
25 #define SPIGCR1_CLKMOD_MASK BIT(1)
26 #define SPIGCR1_MASTER_MASK BIT(0)
27 #define SPIGCR1_SPIENA_MASK BIT(24)
30 #define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
31 #define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
32 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
33 #define SPIPC0_EN0FUN_MASK BIT(0)
36 #define SPIFMT_SHIFTDIR_SHIFT 20
37 #define SPIFMT_POLARITY_SHIFT 17
38 #define SPIFMT_PHASE_SHIFT 16
39 #define SPIFMT_PRESCALE_SHIFT 8
42 #define SPIDAT1_CSHOLD_SHIFT 28
43 #define SPIDAT1_CSNR_SHIFT 16
46 #define SPI_C2TDELAY_SHIFT 24
47 #define SPI_T2CDELAY_SHIFT 16
50 #define SPIBUF_RXEMPTY_MASK BIT(31)
51 #define SPIBUF_TXFULL_MASK BIT(29)
54 #define SPIDEF_CSDEF0_MASK BIT(0)
58 #define SPI0_BASE CONFIG_SYS_SPI_BASE
60 * Define default SPI0_NUM_CS as 1 for existing platforms that uses this
61 * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
62 * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
64 #ifndef CONFIG_SYS_SPI0
67 #define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS
71 * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
72 * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
74 #ifdef CONFIG_SYS_SPI1
76 #define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS
77 #define SPI1_BASE CONFIG_SYS_SPI1_BASE
81 * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
82 * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
84 #ifdef CONFIG_SYS_SPI2
86 #define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
87 #define SPI2_BASE CONFIG_SYS_SPI2_BASE
91 DECLARE_GLOBAL_DATA_PTR;
93 /* davinci spi register set */
94 struct davinci_spi_regs {
95 dv_reg gcr0; /* 0x00 */
96 dv_reg gcr1; /* 0x04 */
97 dv_reg int0; /* 0x08 */
98 dv_reg lvl; /* 0x0c */
99 dv_reg flg; /* 0x10 */
100 dv_reg pc0; /* 0x14 */
101 dv_reg pc1; /* 0x18 */
102 dv_reg pc2; /* 0x1c */
103 dv_reg pc3; /* 0x20 */
104 dv_reg pc4; /* 0x24 */
105 dv_reg pc5; /* 0x28 */
107 dv_reg dat0; /* 0x38 */
108 dv_reg dat1; /* 0x3c */
109 dv_reg buf; /* 0x40 */
110 dv_reg emu; /* 0x44 */
111 dv_reg delay; /* 0x48 */
112 dv_reg def; /* 0x4c */
113 dv_reg fmt0; /* 0x50 */
114 dv_reg fmt1; /* 0x54 */
115 dv_reg fmt2; /* 0x58 */
116 dv_reg fmt3; /* 0x5c */
117 dv_reg intvec0; /* 0x60 */
118 dv_reg intvec1; /* 0x64 */
121 /* davinci spi slave */
122 struct davinci_spi_slave {
123 #ifndef CONFIG_DM_SPI
124 struct spi_slave slave;
126 struct davinci_spi_regs *regs;
127 unsigned int freq; /* current SPI bus frequency */
128 unsigned int mode; /* current SPI mode used */
129 u8 num_cs; /* total no. of CS available */
130 u8 cur_cs; /* CS of current slave */
131 bool half_duplex; /* true, if master is half-duplex only */
135 * This functions needs to act like a macro to avoid pipeline reloads in the
136 * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
137 * appears to be zero bytes (da830).
139 __attribute__((always_inline))
140 static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
145 writel(data, &ds->regs->dat1);
147 /* wait for the data to clock in/out */
148 while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
154 static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len,
155 u8 *rxp, unsigned long flags)
157 unsigned int data1_reg_val;
159 /* enable CS hold, CS[n] and clear the data bits */
160 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
161 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
163 /* wait till TXFULL is deasserted */
164 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
167 /* preload the TX buffer to avoid clock starvation */
168 writel(data1_reg_val, &ds->regs->dat1);
170 /* keep reading 1 byte until only 1 byte left */
172 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
174 /* clear CS hold when we reach the end */
175 if (flags & SPI_XFER_END)
176 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
178 /* read the last byte */
179 *rxp = davinci_spi_xfer_data(ds, data1_reg_val);
184 static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len,
185 const u8 *txp, unsigned long flags)
187 unsigned int data1_reg_val;
189 /* enable CS hold and clear the data bits */
190 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
191 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
193 /* wait till TXFULL is deasserted */
194 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
197 /* preload the TX buffer to avoid clock starvation */
199 writel(data1_reg_val | *txp++, &ds->regs->dat1);
203 /* keep writing 1 byte until only 1 byte left */
205 davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
207 /* clear CS hold when we reach the end */
208 if (flags & SPI_XFER_END)
209 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
211 /* write the last byte */
212 davinci_spi_xfer_data(ds, data1_reg_val | *txp);
217 static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned
218 int len, u8 *rxp, const u8 *txp,
221 unsigned int data1_reg_val;
223 /* enable CS hold and clear the data bits */
224 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
225 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
227 /* wait till TXFULL is deasserted */
228 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
231 /* keep reading and writing 1 byte until only 1 byte left */
233 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
235 /* clear CS hold when we reach the end */
236 if (flags & SPI_XFER_END)
237 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
239 /* read and write the last byte */
240 *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
246 static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
248 unsigned int mode = 0, scalar;
250 /* Enable the SPI hardware */
251 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
253 writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
255 /* Set master mode, powered up and not activated */
256 writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
258 /* CS, CLK, SIMO and SOMI are functional pins */
259 writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
260 SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
263 scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
266 * Use following format:
267 * character length = 8,
268 * MSB shifted out first
270 if (ds->mode & SPI_CPOL)
272 if (!(ds->mode & SPI_CPHA))
274 writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
275 (mode << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
278 * Including a minor delay. No science here. Should be good even with
281 writel((50 << SPI_C2TDELAY_SHIFT) |
282 (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
284 /* default chip select register */
285 writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
288 writel(0, &ds->regs->int0);
289 writel(0, &ds->regs->lvl);
292 writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
297 static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
299 /* Disable the SPI hardware */
300 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
305 static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
306 unsigned int bitlen, const void *dout, void *din,
312 /* Finish any previously submitted transfers */
316 * It's not clear how non-8-bit-aligned transfers are supposed to be
317 * represented as a stream of bytes...this is a limitation of
318 * the current SPI interface - here we terminate on receiving such a
322 /* Errors always terminate an ongoing transfer */
323 flags |= SPI_XFER_END;
330 return davinci_spi_read(ds, len, din, flags);
332 return davinci_spi_write(ds, len, dout, flags);
333 if (!ds->half_duplex)
334 return davinci_spi_read_write(ds, len, din, dout, flags);
336 printf("SPI full duplex not supported\n");
337 flags |= SPI_XFER_END;
340 if (flags & SPI_XFER_END) {
342 davinci_spi_write(ds, 1, &dummy, flags);
347 #ifndef CONFIG_DM_SPI
349 static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
351 return container_of(slave, struct davinci_spi_slave, slave);
354 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
360 if (cs < SPI0_NUM_CS)
363 #ifdef CONFIG_SYS_SPI1
365 if (cs < SPI1_NUM_CS)
369 #ifdef CONFIG_SYS_SPI2
371 if (cs < SPI2_NUM_CS)
376 /* Invalid bus number. Do nothing */
382 void spi_cs_activate(struct spi_slave *slave)
387 void spi_cs_deactivate(struct spi_slave *slave)
392 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
393 unsigned int max_hz, unsigned int mode)
395 struct davinci_spi_slave *ds;
397 if (!spi_cs_is_valid(bus, cs))
400 ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
406 ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
408 #ifdef CONFIG_SYS_SPI1
410 ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
413 #ifdef CONFIG_SYS_SPI2
415 ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
418 default: /* Invalid bus number */
428 void spi_free_slave(struct spi_slave *slave)
430 struct davinci_spi_slave *ds = to_davinci_spi(slave);
435 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
436 const void *dout, void *din, unsigned long flags)
438 struct davinci_spi_slave *ds = to_davinci_spi(slave);
440 ds->cur_cs = slave->cs;
442 return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
445 int spi_claim_bus(struct spi_slave *slave)
447 struct davinci_spi_slave *ds = to_davinci_spi(slave);
449 #ifdef CONFIG_SPI_HALF_DUPLEX
450 ds->half_duplex = true;
452 ds->half_duplex = false;
454 return __davinci_spi_claim_bus(ds, ds->slave.cs);
457 void spi_release_bus(struct spi_slave *slave)
459 struct davinci_spi_slave *ds = to_davinci_spi(slave);
461 __davinci_spi_release_bus(ds);
465 static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
467 struct davinci_spi_slave *ds = dev_get_priv(bus);
469 debug("%s speed %u\n", __func__, max_hz);
470 if (max_hz > CONFIG_SYS_SPI_CLK / 2)
478 static int davinci_spi_set_mode(struct udevice *bus, uint mode)
480 struct davinci_spi_slave *ds = dev_get_priv(bus);
482 debug("%s mode %u\n", __func__, mode);
488 static int davinci_spi_claim_bus(struct udevice *dev)
490 struct dm_spi_slave_platdata *slave_plat =
491 dev_get_parent_platdata(dev);
492 struct udevice *bus = dev->parent;
493 struct davinci_spi_slave *ds = dev_get_priv(bus);
495 if (slave_plat->cs >= ds->num_cs) {
496 printf("Invalid SPI chipselect\n");
499 ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
501 return __davinci_spi_claim_bus(ds, slave_plat->cs);
504 static int davinci_spi_release_bus(struct udevice *dev)
506 struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
508 return __davinci_spi_release_bus(ds);
511 static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
512 const void *dout, void *din,
515 struct dm_spi_slave_platdata *slave =
516 dev_get_parent_platdata(dev);
517 struct udevice *bus = dev->parent;
518 struct davinci_spi_slave *ds = dev_get_priv(bus);
520 if (slave->cs >= ds->num_cs) {
521 printf("Invalid SPI chipselect\n");
524 ds->cur_cs = slave->cs;
526 return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
529 static const struct dm_spi_ops davinci_spi_ops = {
530 .claim_bus = davinci_spi_claim_bus,
531 .release_bus = davinci_spi_release_bus,
532 .xfer = davinci_spi_xfer,
533 .set_speed = davinci_spi_set_speed,
534 .set_mode = davinci_spi_set_mode,
537 static int davinci_spi_probe(struct udevice *bus)
539 struct davinci_spi_slave *ds = dev_get_priv(bus);
540 struct davinci_spi_platdata *plat = bus->platdata;
541 ds->regs = plat->regs;
542 ds->num_cs = plat->num_cs;
547 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
548 static int davinci_ofdata_to_platadata(struct udevice *bus)
550 struct davinci_spi_platdata *plat = bus->platdata;
553 addr = devfdt_get_addr(bus);
554 if (addr == FDT_ADDR_T_NONE)
557 plat->regs = (struct davinci_spi_regs *)addr;
558 plat->num_cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "num-cs", 4);
563 static const struct udevice_id davinci_spi_ids[] = {
564 { .compatible = "ti,keystone-spi" },
565 { .compatible = "ti,dm6441-spi" },
566 { .compatible = "ti,da830-spi" },
571 U_BOOT_DRIVER(davinci_spi) = {
572 .name = "davinci_spi",
574 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
575 .of_match = davinci_spi_ids,
576 .ofdata_to_platdata = davinci_ofdata_to_platadata,
577 .platdata_auto_alloc_size = sizeof(struct davinci_spi_platdata),
579 .probe = davinci_spi_probe,
580 .ops = &davinci_spi_ops,
581 .priv_auto_alloc_size = sizeof(struct davinci_spi_slave),