drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <log.h>
  30 #include <asm/io.h>
  31 #include <dma.h>
  32 #include <linux/errno.h>
  33 #include <wait_bit.h>
  34 #include <spi.h>
  35 #include <spi-mem.h>
  36 #include <malloc.h>
  37 #include "cadence_qspi.h"
  38
  39 #define CQSPI_REG_POLL_US                       1 /* 1us */
  40 #define CQSPI_REG_RETRY                         10000
  41 #define CQSPI_POLL_IDLE_RETRY                   3
  42
  43 /* Transfer mode */
  44 #define CQSPI_INST_TYPE_SINGLE                  0
  45 #define CQSPI_INST_TYPE_DUAL                    1
  46 #define CQSPI_INST_TYPE_QUAD                    2
  47 #define CQSPI_INST_TYPE_OCTAL                   3
  48
  49 #define CQSPI_STIG_DATA_LEN_MAX                 8
  50
  51 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
  52 #define CQSPI_DUMMY_BYTES_MAX                   4
  53
  54 /****************************************************************************
  55  * Controller's configuration and status register (offset from QSPI_BASE)
  56  ****************************************************************************/
  57 #define CQSPI_REG_CONFIG                        0x00
  58 #define CQSPI_REG_CONFIG_ENABLE                 BIT(0)
  59 #define CQSPI_REG_CONFIG_CLK_POL                BIT(1)
  60 #define CQSPI_REG_CONFIG_CLK_PHA                BIT(2)
  61 #define CQSPI_REG_CONFIG_DIRECT                 BIT(7)
  62 #define CQSPI_REG_CONFIG_DECODE                 BIT(9)
  63 #define CQSPI_REG_CONFIG_XIP_IMM                BIT(18)
  64 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  65 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  66 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  67 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  68 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  69
  70 #define CQSPI_REG_RD_INSTR                      0x04
  71 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  72 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  73 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  74 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  75 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  76 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  77 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  78 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  79 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  80 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  81
  82 #define CQSPI_REG_WR_INSTR                      0x08
  83 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  84 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
  85
  86 #define CQSPI_REG_DELAY                         0x0C
  87 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  88 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  89 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  90 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  91 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  92 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  93 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
  94 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
  95
  96 #define CQSPI_REG_RD_DATA_CAPTURE               0x10
  97 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS        BIT(0)
  98 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB     1
  99 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK    0xF
 100
 101 #define CQSPI_REG_SIZE                          0x14
 102 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 103 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 104 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 105 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 106 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 107 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 108
 109 #define CQSPI_REG_SRAMPARTITION                 0x18
 110 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 111
 112 #define CQSPI_REG_REMAP                         0x24
 113 #define CQSPI_REG_MODE_BIT                      0x28
 114
 115 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 116 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 117 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 118 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 119 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 120
 121 #define CQSPI_REG_IRQSTATUS                     0x40
 122 #define CQSPI_REG_IRQMASK                       0x44
 123
 124 #define CQSPI_REG_INDIRECTRD                    0x60
 125 #define CQSPI_REG_INDIRECTRD_START              BIT(0)
 126 #define CQSPI_REG_INDIRECTRD_CANCEL             BIT(1)
 127 #define CQSPI_REG_INDIRECTRD_INPROGRESS         BIT(2)
 128 #define CQSPI_REG_INDIRECTRD_DONE               BIT(5)
 129
 130 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 131 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 132 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 133
 134 #define CQSPI_REG_CMDCTRL                       0x90
 135 #define CQSPI_REG_CMDCTRL_EXECUTE               BIT(0)
 136 #define CQSPI_REG_CMDCTRL_INPROGRESS            BIT(1)
 137 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 138 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 139 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 140 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 141 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 142 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 143 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 144 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 145 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 146 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 147 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 148 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 149 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 150
 151 #define CQSPI_REG_INDIRECTWR                    0x70
 152 #define CQSPI_REG_INDIRECTWR_START              BIT(0)
 153 #define CQSPI_REG_INDIRECTWR_CANCEL             BIT(1)
 154 #define CQSPI_REG_INDIRECTWR_INPROGRESS         BIT(2)
 155 #define CQSPI_REG_INDIRECTWR_DONE               BIT(5)
 156
 157 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 158 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 159 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 160
 161 #define CQSPI_REG_CMDADDRESS                    0x94
 162 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 163 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 164 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 165 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 166
 167 #define CQSPI_REG_IS_IDLE(base)                                 \
 168         ((readl(base + CQSPI_REG_CONFIG) >>             \
 169                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 170
 171 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 172         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 173         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 174
 175 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 176         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 177         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 178
 179 void cadence_qspi_apb_controller_enable(void *reg_base)
 180 {
 181         unsigned int reg;
 182         reg = readl(reg_base + CQSPI_REG_CONFIG);
 183         reg |= CQSPI_REG_CONFIG_ENABLE;
 184         writel(reg, reg_base + CQSPI_REG_CONFIG);
 185 }
 186
 187 void cadence_qspi_apb_controller_disable(void *reg_base)
 188 {
 189         unsigned int reg;
 190         reg = readl(reg_base + CQSPI_REG_CONFIG);
 191         reg &= ~CQSPI_REG_CONFIG_ENABLE;
 192         writel(reg, reg_base + CQSPI_REG_CONFIG);
 193 }
 194
 195 void cadence_qspi_apb_dac_mode_enable(void *reg_base)
 196 {
 197         unsigned int reg;
 198
 199         reg = readl(reg_base + CQSPI_REG_CONFIG);
 200         reg |= CQSPI_REG_CONFIG_DIRECT;
 201         writel(reg, reg_base + CQSPI_REG_CONFIG);
 202 }
 203
 204 /* Return 1 if idle, otherwise return 0 (busy). */
 205 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 206 {
 207         unsigned int start, count = 0;
 208         /* timeout in unit of ms */
 209         unsigned int timeout = 5000;
 210
 211         start = get_timer(0);
 212         for ( ; get_timer(start) < timeout ; ) {
 213                 if (CQSPI_REG_IS_IDLE(reg_base))
 214                         count++;
 215                 else
 216                         count = 0;
 217                 /*
 218                  * Ensure the QSPI controller is in true idle state after
 219                  * reading back the same idle status consecutively
 220                  */
 221                 if (count >= CQSPI_POLL_IDLE_RETRY)
 222                         return 1;
 223         }
 224
 225         /* Timeout, still in busy mode. */
 226         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 227                CQSPI_REG_RETRY);
 228         return 0;
 229 }
 230
 231 void cadence_qspi_apb_readdata_capture(void *reg_base,
 232                                 unsigned int bypass, unsigned int delay)
 233 {
 234         unsigned int reg;
 235         cadence_qspi_apb_controller_disable(reg_base);
 236
 237         reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 238
 239         if (bypass)
 240                 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 241         else
 242                 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 243
 244         reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
 245                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
 246
 247         reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
 248                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
 249
 250         writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 251
 252         cadence_qspi_apb_controller_enable(reg_base);
 253 }
 254
 255 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 256         unsigned int ref_clk_hz, unsigned int sclk_hz)
 257 {
 258         unsigned int reg;
 259         unsigned int div;
 260
 261         cadence_qspi_apb_controller_disable(reg_base);
 262         reg = readl(reg_base + CQSPI_REG_CONFIG);
 263         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 264
 265         /*
 266          * The baud_div field in the config reg is 4 bits, and the ref clock is
 267          * divided by 2 * (baud_div + 1). Round up the divider to ensure the
 268          * SPI clock rate is less than or equal to the requested clock rate.
 269          */
 270         div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
 271
 272         /* ensure the baud rate doesn't exceed the max value */
 273         if (div > CQSPI_REG_CONFIG_BAUD_MASK)
 274                 div = CQSPI_REG_CONFIG_BAUD_MASK;
 275
 276         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
 277               ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
 278
 279         reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
 280         writel(reg, reg_base + CQSPI_REG_CONFIG);
 281
 282         cadence_qspi_apb_controller_enable(reg_base);
 283 }
 284
 285 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
 286 {
 287         unsigned int reg;
 288
 289         cadence_qspi_apb_controller_disable(reg_base);
 290         reg = readl(reg_base + CQSPI_REG_CONFIG);
 291         reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
 292
 293         if (mode & SPI_CPOL)
 294                 reg |= CQSPI_REG_CONFIG_CLK_POL;
 295         if (mode & SPI_CPHA)
 296                 reg |= CQSPI_REG_CONFIG_CLK_PHA;
 297
 298         writel(reg, reg_base + CQSPI_REG_CONFIG);
 299
 300         cadence_qspi_apb_controller_enable(reg_base);
 301 }
 302
 303 void cadence_qspi_apb_chipselect(void *reg_base,
 304         unsigned int chip_select, unsigned int decoder_enable)
 305 {
 306         unsigned int reg;
 307
 308         cadence_qspi_apb_controller_disable(reg_base);
 309
 310         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 311               decoder_enable);
 312
 313         reg = readl(reg_base + CQSPI_REG_CONFIG);
 314         /* docoder */
 315         if (decoder_enable) {
 316                 reg |= CQSPI_REG_CONFIG_DECODE;
 317         } else {
 318                 reg &= ~CQSPI_REG_CONFIG_DECODE;
 319                 /* Convert CS if without decoder.
 320                  * CS0 to 4b'1110
 321                  * CS1 to 4b'1101
 322                  * CS2 to 4b'1011
 323                  * CS3 to 4b'0111
 324                  */
 325                 chip_select = 0xF & ~(1 << chip_select);
 326         }
 327
 328         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 329                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 330         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 331                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 332         writel(reg, reg_base + CQSPI_REG_CONFIG);
 333
 334         cadence_qspi_apb_controller_enable(reg_base);
 335 }
 336
 337 void cadence_qspi_apb_delay(void *reg_base,
 338         unsigned int ref_clk, unsigned int sclk_hz,
 339         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 340         unsigned int tchsh_ns, unsigned int tslch_ns)
 341 {
 342         unsigned int ref_clk_ns;
 343         unsigned int sclk_ns;
 344         unsigned int tshsl, tchsh, tslch, tsd2d;
 345         unsigned int reg;
 346
 347         cadence_qspi_apb_controller_disable(reg_base);
 348
 349         /* Convert to ns. */
 350         ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
 351
 352         /* Convert to ns. */
 353         sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
 354
 355         /* The controller adds additional delay to that programmed in the reg */
 356         if (tshsl_ns >= sclk_ns + ref_clk_ns)
 357                 tshsl_ns -= sclk_ns + ref_clk_ns;
 358         if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
 359                 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
 360         tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
 361         tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
 362         tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
 363         tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
 364
 365         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 366                         << CQSPI_REG_DELAY_TSHSL_LSB);
 367         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 368                         << CQSPI_REG_DELAY_TCHSH_LSB);
 369         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 370                         << CQSPI_REG_DELAY_TSLCH_LSB);
 371         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 372                         << CQSPI_REG_DELAY_TSD2D_LSB);
 373         writel(reg, reg_base + CQSPI_REG_DELAY);
 374
 375         cadence_qspi_apb_controller_enable(reg_base);
 376 }
 377
 378 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 379 {
 380         unsigned reg;
 381
 382         cadence_qspi_apb_controller_disable(plat->regbase);
 383
 384         /* Configure the device size and address bytes */
 385         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 386         /* Clear the previous value */
 387         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 388         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 389         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 390         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 391         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 392
 393         /* Configure the remap address register, no remap */
 394         writel(0, plat->regbase + CQSPI_REG_REMAP);
 395
 396         /* Indirect mode configurations */
 397         writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
 398
 399         /* Disable all interrupts */
 400         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 401
 402         cadence_qspi_apb_controller_enable(plat->regbase);
 403 }
 404
 405 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 406         unsigned int reg)
 407 {
 408         unsigned int retry = CQSPI_REG_RETRY;
 409
 410         /* Write the CMDCTRL without start execution. */
 411         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 412         /* Start execute */
 413         reg |= CQSPI_REG_CMDCTRL_EXECUTE;
 414         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 415
 416         while (retry--) {
 417                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 418                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
 419                         break;
 420                 udelay(1);
 421         }
 422
 423         if (!retry) {
 424                 printf("QSPI: flash command execution timeout\n");
 425                 return -EIO;
 426         }
 427
 428         /* Polling QSPI idle status. */
 429         if (!cadence_qspi_wait_idle(reg_base))
 430                 return -EIO;
 431
 432         return 0;
 433 }
 434
 435 /* For command RDID, RDSR. */
 436 int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op)
 437 {
 438         unsigned int reg;
 439         unsigned int read_len;
 440         int status;
 441         unsigned int rxlen = op->data.nbytes;
 442         void *rxbuf = op->data.buf.in;
 443
 444         if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 445                 printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
 446                 return -EINVAL;
 447         }
 448
 449         reg = op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 450
 451         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 452
 453         /* 0 means 1 byte. */
 454         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 455                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 456         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 457         if (status != 0)
 458                 return status;
 459
 460         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 461
 462         /* Put the read value into rx_buf */
 463         read_len = (rxlen > 4) ? 4 : rxlen;
 464         memcpy(rxbuf, &reg, read_len);
 465         rxbuf += read_len;
 466
 467         if (rxlen > 4) {
 468                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 469
 470                 read_len = rxlen - read_len;
 471                 memcpy(rxbuf, &reg, read_len);
 472         }
 473         return 0;
 474 }
 475
 476 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 477 int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op)
 478 {
 479         unsigned int reg = 0;
 480         unsigned int wr_data;
 481         unsigned int wr_len;
 482         unsigned int txlen = op->data.nbytes;
 483         const void *txbuf = op->data.buf.out;
 484         u32 addr;
 485
 486         /* Reorder address to SPI bus order if only transferring address */
 487         if (!txlen) {
 488                 addr = cpu_to_be32(op->addr.val);
 489                 if (op->addr.nbytes == 3)
 490                         addr >>= 8;
 491                 txbuf = &addr;
 492                 txlen = op->addr.nbytes;
 493         }
 494
 495         if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
 496                 printf("QSPI: Invalid input arguments txlen %u\n", txlen);
 497                 return -EINVAL;
 498         }
 499
 500         reg |= op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 501
 502         if (txlen) {
 503                 /* writing data = yes */
 504                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 505                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 506                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 507
 508                 wr_len = txlen > 4 ? 4 : txlen;
 509                 memcpy(&wr_data, txbuf, wr_len);
 510                 writel(wr_data, reg_base +
 511                         CQSPI_REG_CMDWRITEDATALOWER);
 512
 513                 if (txlen > 4) {
 514                         txbuf += wr_len;
 515                         wr_len = txlen - wr_len;
 516                         memcpy(&wr_data, txbuf, wr_len);
 517                         writel(wr_data, reg_base +
 518                                 CQSPI_REG_CMDWRITEDATAUPPER);
 519                 }
 520         }
 521
 522         /* Execute the command */
 523         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 524 }
 525
 526 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 527 int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
 528                                 const struct spi_mem_op *op)
 529 {
 530         unsigned int reg;
 531         unsigned int rd_reg;
 532         unsigned int dummy_clk;
 533         unsigned int dummy_bytes = op->dummy.nbytes;
 534
 535         /* Setup the indirect trigger address */
 536         writel(plat->trigger_address,
 537                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 538
 539         /* Configure the opcode */
 540         rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 541
 542         if (op->data.buswidth == 8)
 543                 /* Instruction and address at DQ0, data at DQ0-7. */
 544                 rd_reg |= CQSPI_INST_TYPE_OCTAL << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 545         else if (op->data.buswidth == 4)
 546                 /* Instruction and address at DQ0, data at DQ0-3. */
 547                 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 548
 549         writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 550
 551         if (dummy_bytes) {
 552                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 553                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 554
 555                 /* Convert to clock cycles. */
 556                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 557
 558                 if (dummy_clk)
 559                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 560                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 561         }
 562
 563         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 564
 565         /* set device size */
 566         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 567         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 568         reg |= (op->addr.nbytes - 1);
 569         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 570         return 0;
 571 }
 572
 573 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
 574 {
 575         u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
 576         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 577         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 578 }
 579
 580 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
 581 {
 582         unsigned int timeout = 10000;
 583         u32 reg;
 584
 585         while (timeout--) {
 586                 reg = cadence_qspi_get_rd_sram_level(plat);
 587                 if (reg)
 588                         return reg;
 589                 udelay(1);
 590         }
 591
 592         return -ETIMEDOUT;
 593 }
 594
 595 static int
 596 cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 597                                        unsigned int n_rx, u8 *rxbuf)
 598 {
 599         unsigned int remaining = n_rx;
 600         unsigned int bytes_to_read = 0;
 601         int ret;
 602
 603         writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 604
 605         /* Start the indirect read transfer */
 606         writel(CQSPI_REG_INDIRECTRD_START,
 607                plat->regbase + CQSPI_REG_INDIRECTRD);
 608
 609         while (remaining > 0) {
 610                 ret = cadence_qspi_wait_for_data(plat);
 611                 if (ret < 0) {
 612                         printf("Indirect write timed out (%i)\n", ret);
 613                         goto failrd;
 614                 }
 615
 616                 bytes_to_read = ret;
 617
 618                 while (bytes_to_read != 0) {
 619                         bytes_to_read *= plat->fifo_width;
 620                         bytes_to_read = bytes_to_read > remaining ?
 621                                         remaining : bytes_to_read;
 622                         /*
 623                          * Handle non-4-byte aligned access to avoid
 624                          * data abort.
 625                          */
 626                         if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
 627                                 readsb(plat->ahbbase, rxbuf, bytes_to_read);
 628                         else
 629                                 readsl(plat->ahbbase, rxbuf,
 630                                        bytes_to_read >> 2);
 631                         rxbuf += bytes_to_read;
 632                         remaining -= bytes_to_read;
 633                         bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
 634                 }
 635         }
 636
 637         /* Check indirect done status */
 638         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
 639                                 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
 640         if (ret) {
 641                 printf("Indirect read completion error (%i)\n", ret);
 642                 goto failrd;
 643         }
 644
 645         /* Clear indirect completion status */
 646         writel(CQSPI_REG_INDIRECTRD_DONE,
 647                plat->regbase + CQSPI_REG_INDIRECTRD);
 648
 649         return 0;
 650
 651 failrd:
 652         /* Cancel the indirect read */
 653         writel(CQSPI_REG_INDIRECTRD_CANCEL,
 654                plat->regbase + CQSPI_REG_INDIRECTRD);
 655         return ret;
 656 }
 657
 658 int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
 659                                   const struct spi_mem_op *op)
 660 {
 661         u64 from = op->addr.val;
 662         void *buf = op->data.buf.in;
 663         size_t len = op->data.nbytes;
 664
 665         if (plat->use_dac_mode && (from + len < plat->ahbsize)) {
 666                 if (len < 256 ||
 667                     dma_memcpy(buf, plat->ahbbase + from, len) < 0) {
 668                         memcpy_fromio(buf, plat->ahbbase + from, len);
 669                 }
 670                 if (!cadence_qspi_wait_idle(plat->regbase))
 671                         return -EIO;
 672                 return 0;
 673         }
 674
 675         return cadence_qspi_apb_indirect_read_execute(plat, len, buf);
 676 }
 677
 678 /* Opcode + Address (3/4 bytes) */
 679 int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
 680                                  const struct spi_mem_op *op)
 681 {
 682         unsigned int reg;
 683
 684         /* Setup the indirect trigger address */
 685         writel(plat->trigger_address,
 686                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 687
 688         /* Configure the opcode */
 689         reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 690         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 691
 692         writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 693
 694         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 695         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 696         reg |= (op->addr.nbytes - 1);
 697         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 698         return 0;
 699 }
 700
 701 static int
 702 cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 703                                         unsigned int n_tx, const u8 *txbuf)
 704 {
 705         unsigned int page_size = plat->page_size;
 706         unsigned int remaining = n_tx;
 707         const u8 *bb_txbuf = txbuf;
 708         void *bounce_buf = NULL;
 709         unsigned int write_bytes;
 710         int ret;
 711
 712         /*
 713          * Use bounce buffer for non 32 bit aligned txbuf to avoid data
 714          * aborts
 715          */
 716         if ((uintptr_t)txbuf % 4) {
 717                 bounce_buf = malloc(n_tx);
 718                 if (!bounce_buf)
 719                         return -ENOMEM;
 720                 memcpy(bounce_buf, txbuf, n_tx);
 721                 bb_txbuf = bounce_buf;
 722         }
 723
 724         /* Configure the indirect read transfer bytes */
 725         writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 726
 727         /* Start the indirect write transfer */
 728         writel(CQSPI_REG_INDIRECTWR_START,
 729                plat->regbase + CQSPI_REG_INDIRECTWR);
 730
 731         while (remaining > 0) {
 732                 write_bytes = remaining > page_size ? page_size : remaining;
 733                 writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
 734                 if (write_bytes % 4)
 735                         writesb(plat->ahbbase,
 736                                 bb_txbuf + rounddown(write_bytes, 4),
 737                                 write_bytes % 4);
 738
 739                 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
 740                                         CQSPI_REG_SDRAMLEVEL_WR_MASK <<
 741                                         CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
 742                 if (ret) {
 743                         printf("Indirect write timed out (%i)\n", ret);
 744                         goto failwr;
 745                 }
 746
 747                 bb_txbuf += write_bytes;
 748                 remaining -= write_bytes;
 749         }
 750
 751         /* Check indirect done status */
 752         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
 753                                 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
 754         if (ret) {
 755                 printf("Indirect write completion error (%i)\n", ret);
 756                 goto failwr;
 757         }
 758
 759         /* Clear indirect completion status */
 760         writel(CQSPI_REG_INDIRECTWR_DONE,
 761                plat->regbase + CQSPI_REG_INDIRECTWR);
 762         if (bounce_buf)
 763                 free(bounce_buf);
 764         return 0;
 765
 766 failwr:
 767         /* Cancel the indirect write */
 768         writel(CQSPI_REG_INDIRECTWR_CANCEL,
 769                plat->regbase + CQSPI_REG_INDIRECTWR);
 770         if (bounce_buf)
 771                 free(bounce_buf);
 772         return ret;
 773 }
 774
 775 int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
 776                                    const struct spi_mem_op *op)
 777 {
 778         u32 to = op->addr.val;
 779         const void *buf = op->data.buf.out;
 780         size_t len = op->data.nbytes;
 781
 782         if (plat->use_dac_mode && (to + len < plat->ahbsize)) {
 783                 memcpy_toio(plat->ahbbase + to, buf, len);
 784                 if (!cadence_qspi_wait_idle(plat->regbase))
 785                         return -EIO;
 786                 return 0;
 787         }
 788
 789         return cadence_qspi_apb_indirect_write_execute(plat, len, buf);
 790 }
 791
 792 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 793 {
 794         unsigned int reg;
 795
 796         /* enter XiP mode immediately and enable direct mode */
 797         reg = readl(reg_base + CQSPI_REG_CONFIG);
 798         reg |= CQSPI_REG_CONFIG_ENABLE;
 799         reg |= CQSPI_REG_CONFIG_DIRECT;
 800         reg |= CQSPI_REG_CONFIG_XIP_IMM;
 801         writel(reg, reg_base + CQSPI_REG_CONFIG);
 802
 803         /* keep the XiP mode */
 804         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 805
 806         /* Enable mode bit at devrd */
 807         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 808         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 809         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 810 }