drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <log.h>
  30 #include <asm/io.h>
  31 #include <dma.h>
  32 #include <linux/delay.h>
  33 #include <linux/errno.h>
  34 #include <wait_bit.h>
  35 #include <spi.h>
  36 #include <spi-mem.h>
  37 #include <malloc.h>
  38 #include "cadence_qspi.h"
  39
  40 #define CQSPI_REG_POLL_US                       1 /* 1us */
  41 #define CQSPI_REG_RETRY                         10000
  42 #define CQSPI_POLL_IDLE_RETRY                   3
  43
  44 /* Transfer mode */
  45 #define CQSPI_INST_TYPE_SINGLE                  0
  46 #define CQSPI_INST_TYPE_DUAL                    1
  47 #define CQSPI_INST_TYPE_QUAD                    2
  48 #define CQSPI_INST_TYPE_OCTAL                   3
  49
  50 #define CQSPI_STIG_DATA_LEN_MAX                 8
  51
  52 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
  53 #define CQSPI_DUMMY_BYTES_MAX                   4
  54
  55 /****************************************************************************
  56  * Controller's configuration and status register (offset from QSPI_BASE)
  57  ****************************************************************************/
  58 #define CQSPI_REG_CONFIG                        0x00
  59 #define CQSPI_REG_CONFIG_ENABLE                 BIT(0)
  60 #define CQSPI_REG_CONFIG_CLK_POL                BIT(1)
  61 #define CQSPI_REG_CONFIG_CLK_PHA                BIT(2)
  62 #define CQSPI_REG_CONFIG_DIRECT                 BIT(7)
  63 #define CQSPI_REG_CONFIG_DECODE                 BIT(9)
  64 #define CQSPI_REG_CONFIG_XIP_IMM                BIT(18)
  65 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  66 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  67 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  68 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  69 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  70
  71 #define CQSPI_REG_RD_INSTR                      0x04
  72 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  73 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  74 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  75 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  76 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  77 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  78 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  79 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  80 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  81 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  82
  83 #define CQSPI_REG_WR_INSTR                      0x08
  84 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  85 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
  86
  87 #define CQSPI_REG_DELAY                         0x0C
  88 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  89 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  90 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  91 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  92 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  93 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  94 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
  95 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
  96
  97 #define CQSPI_REG_RD_DATA_CAPTURE               0x10
  98 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS        BIT(0)
  99 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB     1
 100 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK    0xF
 101
 102 #define CQSPI_REG_SIZE                          0x14
 103 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 104 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 105 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 106 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 107 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 108 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 109
 110 #define CQSPI_REG_SRAMPARTITION                 0x18
 111 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 112
 113 #define CQSPI_REG_REMAP                         0x24
 114 #define CQSPI_REG_MODE_BIT                      0x28
 115
 116 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 117 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 118 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 119 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 120 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 121
 122 #define CQSPI_REG_IRQSTATUS                     0x40
 123 #define CQSPI_REG_IRQMASK                       0x44
 124
 125 #define CQSPI_REG_INDIRECTRD                    0x60
 126 #define CQSPI_REG_INDIRECTRD_START              BIT(0)
 127 #define CQSPI_REG_INDIRECTRD_CANCEL             BIT(1)
 128 #define CQSPI_REG_INDIRECTRD_INPROGRESS         BIT(2)
 129 #define CQSPI_REG_INDIRECTRD_DONE               BIT(5)
 130
 131 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 132 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 133 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 134
 135 #define CQSPI_REG_CMDCTRL                       0x90
 136 #define CQSPI_REG_CMDCTRL_EXECUTE               BIT(0)
 137 #define CQSPI_REG_CMDCTRL_INPROGRESS            BIT(1)
 138 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 139 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 140 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 141 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 142 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 143 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 144 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 145 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 146 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 147 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 148 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 149 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 150 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 151
 152 #define CQSPI_REG_INDIRECTWR                    0x70
 153 #define CQSPI_REG_INDIRECTWR_START              BIT(0)
 154 #define CQSPI_REG_INDIRECTWR_CANCEL             BIT(1)
 155 #define CQSPI_REG_INDIRECTWR_INPROGRESS         BIT(2)
 156 #define CQSPI_REG_INDIRECTWR_DONE               BIT(5)
 157
 158 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 159 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 160 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 161
 162 #define CQSPI_REG_CMDADDRESS                    0x94
 163 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 164 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 165 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 166 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 167
 168 #define CQSPI_REG_IS_IDLE(base)                                 \
 169         ((readl(base + CQSPI_REG_CONFIG) >>             \
 170                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 171
 172 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 173         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 174         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 175
 176 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 177         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 178         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 179
 180 void cadence_qspi_apb_controller_enable(void *reg_base)
 181 {
 182         unsigned int reg;
 183         reg = readl(reg_base + CQSPI_REG_CONFIG);
 184         reg |= CQSPI_REG_CONFIG_ENABLE;
 185         writel(reg, reg_base + CQSPI_REG_CONFIG);
 186 }
 187
 188 void cadence_qspi_apb_controller_disable(void *reg_base)
 189 {
 190         unsigned int reg;
 191         reg = readl(reg_base + CQSPI_REG_CONFIG);
 192         reg &= ~CQSPI_REG_CONFIG_ENABLE;
 193         writel(reg, reg_base + CQSPI_REG_CONFIG);
 194 }
 195
 196 void cadence_qspi_apb_dac_mode_enable(void *reg_base)
 197 {
 198         unsigned int reg;
 199
 200         reg = readl(reg_base + CQSPI_REG_CONFIG);
 201         reg |= CQSPI_REG_CONFIG_DIRECT;
 202         writel(reg, reg_base + CQSPI_REG_CONFIG);
 203 }
 204
 205 /* Return 1 if idle, otherwise return 0 (busy). */
 206 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 207 {
 208         unsigned int start, count = 0;
 209         /* timeout in unit of ms */
 210         unsigned int timeout = 5000;
 211
 212         start = get_timer(0);
 213         for ( ; get_timer(start) < timeout ; ) {
 214                 if (CQSPI_REG_IS_IDLE(reg_base))
 215                         count++;
 216                 else
 217                         count = 0;
 218                 /*
 219                  * Ensure the QSPI controller is in true idle state after
 220                  * reading back the same idle status consecutively
 221                  */
 222                 if (count >= CQSPI_POLL_IDLE_RETRY)
 223                         return 1;
 224         }
 225
 226         /* Timeout, still in busy mode. */
 227         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 228                CQSPI_REG_RETRY);
 229         return 0;
 230 }
 231
 232 void cadence_qspi_apb_readdata_capture(void *reg_base,
 233                                 unsigned int bypass, unsigned int delay)
 234 {
 235         unsigned int reg;
 236         cadence_qspi_apb_controller_disable(reg_base);
 237
 238         reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 239
 240         if (bypass)
 241                 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 242         else
 243                 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 244
 245         reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
 246                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
 247
 248         reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
 249                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
 250
 251         writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 252
 253         cadence_qspi_apb_controller_enable(reg_base);
 254 }
 255
 256 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 257         unsigned int ref_clk_hz, unsigned int sclk_hz)
 258 {
 259         unsigned int reg;
 260         unsigned int div;
 261
 262         cadence_qspi_apb_controller_disable(reg_base);
 263         reg = readl(reg_base + CQSPI_REG_CONFIG);
 264         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 265
 266         /*
 267          * The baud_div field in the config reg is 4 bits, and the ref clock is
 268          * divided by 2 * (baud_div + 1). Round up the divider to ensure the
 269          * SPI clock rate is less than or equal to the requested clock rate.
 270          */
 271         div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
 272
 273         /* ensure the baud rate doesn't exceed the max value */
 274         if (div > CQSPI_REG_CONFIG_BAUD_MASK)
 275                 div = CQSPI_REG_CONFIG_BAUD_MASK;
 276
 277         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
 278               ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
 279
 280         reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
 281         writel(reg, reg_base + CQSPI_REG_CONFIG);
 282
 283         cadence_qspi_apb_controller_enable(reg_base);
 284 }
 285
 286 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
 287 {
 288         unsigned int reg;
 289
 290         cadence_qspi_apb_controller_disable(reg_base);
 291         reg = readl(reg_base + CQSPI_REG_CONFIG);
 292         reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
 293
 294         if (mode & SPI_CPOL)
 295                 reg |= CQSPI_REG_CONFIG_CLK_POL;
 296         if (mode & SPI_CPHA)
 297                 reg |= CQSPI_REG_CONFIG_CLK_PHA;
 298
 299         writel(reg, reg_base + CQSPI_REG_CONFIG);
 300
 301         cadence_qspi_apb_controller_enable(reg_base);
 302 }
 303
 304 void cadence_qspi_apb_chipselect(void *reg_base,
 305         unsigned int chip_select, unsigned int decoder_enable)
 306 {
 307         unsigned int reg;
 308
 309         cadence_qspi_apb_controller_disable(reg_base);
 310
 311         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 312               decoder_enable);
 313
 314         reg = readl(reg_base + CQSPI_REG_CONFIG);
 315         /* docoder */
 316         if (decoder_enable) {
 317                 reg |= CQSPI_REG_CONFIG_DECODE;
 318         } else {
 319                 reg &= ~CQSPI_REG_CONFIG_DECODE;
 320                 /* Convert CS if without decoder.
 321                  * CS0 to 4b'1110
 322                  * CS1 to 4b'1101
 323                  * CS2 to 4b'1011
 324                  * CS3 to 4b'0111
 325                  */
 326                 chip_select = 0xF & ~(1 << chip_select);
 327         }
 328
 329         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 330                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 331         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 332                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 333         writel(reg, reg_base + CQSPI_REG_CONFIG);
 334
 335         cadence_qspi_apb_controller_enable(reg_base);
 336 }
 337
 338 void cadence_qspi_apb_delay(void *reg_base,
 339         unsigned int ref_clk, unsigned int sclk_hz,
 340         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 341         unsigned int tchsh_ns, unsigned int tslch_ns)
 342 {
 343         unsigned int ref_clk_ns;
 344         unsigned int sclk_ns;
 345         unsigned int tshsl, tchsh, tslch, tsd2d;
 346         unsigned int reg;
 347
 348         cadence_qspi_apb_controller_disable(reg_base);
 349
 350         /* Convert to ns. */
 351         ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
 352
 353         /* Convert to ns. */
 354         sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
 355
 356         /* The controller adds additional delay to that programmed in the reg */
 357         if (tshsl_ns >= sclk_ns + ref_clk_ns)
 358                 tshsl_ns -= sclk_ns + ref_clk_ns;
 359         if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
 360                 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
 361         tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
 362         tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
 363         tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
 364         tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
 365
 366         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 367                         << CQSPI_REG_DELAY_TSHSL_LSB);
 368         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 369                         << CQSPI_REG_DELAY_TCHSH_LSB);
 370         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 371                         << CQSPI_REG_DELAY_TSLCH_LSB);
 372         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 373                         << CQSPI_REG_DELAY_TSD2D_LSB);
 374         writel(reg, reg_base + CQSPI_REG_DELAY);
 375
 376         cadence_qspi_apb_controller_enable(reg_base);
 377 }
 378
 379 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 380 {
 381         unsigned reg;
 382
 383         cadence_qspi_apb_controller_disable(plat->regbase);
 384
 385         /* Configure the device size and address bytes */
 386         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 387         /* Clear the previous value */
 388         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 389         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 390         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 391         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 392         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 393
 394         /* Configure the remap address register, no remap */
 395         writel(0, plat->regbase + CQSPI_REG_REMAP);
 396
 397         /* Indirect mode configurations */
 398         writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
 399
 400         /* Disable all interrupts */
 401         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 402
 403         cadence_qspi_apb_controller_enable(plat->regbase);
 404 }
 405
 406 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 407         unsigned int reg)
 408 {
 409         unsigned int retry = CQSPI_REG_RETRY;
 410
 411         /* Write the CMDCTRL without start execution. */
 412         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 413         /* Start execute */
 414         reg |= CQSPI_REG_CMDCTRL_EXECUTE;
 415         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 416
 417         while (retry--) {
 418                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 419                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
 420                         break;
 421                 udelay(1);
 422         }
 423
 424         if (!retry) {
 425                 printf("QSPI: flash command execution timeout\n");
 426                 return -EIO;
 427         }
 428
 429         /* Polling QSPI idle status. */
 430         if (!cadence_qspi_wait_idle(reg_base))
 431                 return -EIO;
 432
 433         return 0;
 434 }
 435
 436 /* For command RDID, RDSR. */
 437 int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op)
 438 {
 439         unsigned int reg;
 440         unsigned int read_len;
 441         int status;
 442         unsigned int rxlen = op->data.nbytes;
 443         void *rxbuf = op->data.buf.in;
 444
 445         if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 446                 printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
 447                 return -EINVAL;
 448         }
 449
 450         reg = op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 451
 452         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 453
 454         /* 0 means 1 byte. */
 455         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 456                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 457         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 458         if (status != 0)
 459                 return status;
 460
 461         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 462
 463         /* Put the read value into rx_buf */
 464         read_len = (rxlen > 4) ? 4 : rxlen;
 465         memcpy(rxbuf, &reg, read_len);
 466         rxbuf += read_len;
 467
 468         if (rxlen > 4) {
 469                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 470
 471                 read_len = rxlen - read_len;
 472                 memcpy(rxbuf, &reg, read_len);
 473         }
 474         return 0;
 475 }
 476
 477 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 478 int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op)
 479 {
 480         unsigned int reg = 0;
 481         unsigned int wr_data;
 482         unsigned int wr_len;
 483         unsigned int txlen = op->data.nbytes;
 484         const void *txbuf = op->data.buf.out;
 485         u32 addr;
 486
 487         /* Reorder address to SPI bus order if only transferring address */
 488         if (!txlen) {
 489                 addr = cpu_to_be32(op->addr.val);
 490                 if (op->addr.nbytes == 3)
 491                         addr >>= 8;
 492                 txbuf = &addr;
 493                 txlen = op->addr.nbytes;
 494         }
 495
 496         if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
 497                 printf("QSPI: Invalid input arguments txlen %u\n", txlen);
 498                 return -EINVAL;
 499         }
 500
 501         reg |= op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 502
 503         if (txlen) {
 504                 /* writing data = yes */
 505                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 506                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 507                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 508
 509                 wr_len = txlen > 4 ? 4 : txlen;
 510                 memcpy(&wr_data, txbuf, wr_len);
 511                 writel(wr_data, reg_base +
 512                         CQSPI_REG_CMDWRITEDATALOWER);
 513
 514                 if (txlen > 4) {
 515                         txbuf += wr_len;
 516                         wr_len = txlen - wr_len;
 517                         memcpy(&wr_data, txbuf, wr_len);
 518                         writel(wr_data, reg_base +
 519                                 CQSPI_REG_CMDWRITEDATAUPPER);
 520                 }
 521         }
 522
 523         /* Execute the command */
 524         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 525 }
 526
 527 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 528 int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
 529                                 const struct spi_mem_op *op)
 530 {
 531         unsigned int reg;
 532         unsigned int rd_reg;
 533         unsigned int dummy_clk;
 534         unsigned int dummy_bytes = op->dummy.nbytes;
 535
 536         /* Setup the indirect trigger address */
 537         writel(plat->trigger_address,
 538                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 539
 540         /* Configure the opcode */
 541         rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 542
 543         if (op->data.buswidth == 8)
 544                 /* Instruction and address at DQ0, data at DQ0-7. */
 545                 rd_reg |= CQSPI_INST_TYPE_OCTAL << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 546         else if (op->data.buswidth == 4)
 547                 /* Instruction and address at DQ0, data at DQ0-3. */
 548                 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 549
 550         writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 551
 552         if (dummy_bytes) {
 553                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 554                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 555
 556                 /* Convert to clock cycles. */
 557                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 558
 559                 if (dummy_clk)
 560                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 561                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 562         }
 563
 564         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 565
 566         /* set device size */
 567         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 568         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 569         reg |= (op->addr.nbytes - 1);
 570         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 571         return 0;
 572 }
 573
 574 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
 575 {
 576         u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
 577         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 578         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 579 }
 580
 581 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
 582 {
 583         unsigned int timeout = 10000;
 584         u32 reg;
 585
 586         while (timeout--) {
 587                 reg = cadence_qspi_get_rd_sram_level(plat);
 588                 if (reg)
 589                         return reg;
 590                 udelay(1);
 591         }
 592
 593         return -ETIMEDOUT;
 594 }
 595
 596 static int
 597 cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 598                                        unsigned int n_rx, u8 *rxbuf)
 599 {
 600         unsigned int remaining = n_rx;
 601         unsigned int bytes_to_read = 0;
 602         int ret;
 603
 604         writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 605
 606         /* Start the indirect read transfer */
 607         writel(CQSPI_REG_INDIRECTRD_START,
 608                plat->regbase + CQSPI_REG_INDIRECTRD);
 609
 610         while (remaining > 0) {
 611                 ret = cadence_qspi_wait_for_data(plat);
 612                 if (ret < 0) {
 613                         printf("Indirect write timed out (%i)\n", ret);
 614                         goto failrd;
 615                 }
 616
 617                 bytes_to_read = ret;
 618
 619                 while (bytes_to_read != 0) {
 620                         bytes_to_read *= plat->fifo_width;
 621                         bytes_to_read = bytes_to_read > remaining ?
 622                                         remaining : bytes_to_read;
 623                         /*
 624                          * Handle non-4-byte aligned access to avoid
 625                          * data abort.
 626                          */
 627                         if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
 628                                 readsb(plat->ahbbase, rxbuf, bytes_to_read);
 629                         else
 630                                 readsl(plat->ahbbase, rxbuf,
 631                                        bytes_to_read >> 2);
 632                         rxbuf += bytes_to_read;
 633                         remaining -= bytes_to_read;
 634                         bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
 635                 }
 636         }
 637
 638         /* Check indirect done status */
 639         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
 640                                 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
 641         if (ret) {
 642                 printf("Indirect read completion error (%i)\n", ret);
 643                 goto failrd;
 644         }
 645
 646         /* Clear indirect completion status */
 647         writel(CQSPI_REG_INDIRECTRD_DONE,
 648                plat->regbase + CQSPI_REG_INDIRECTRD);
 649
 650         return 0;
 651
 652 failrd:
 653         /* Cancel the indirect read */
 654         writel(CQSPI_REG_INDIRECTRD_CANCEL,
 655                plat->regbase + CQSPI_REG_INDIRECTRD);
 656         return ret;
 657 }
 658
 659 int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
 660                                   const struct spi_mem_op *op)
 661 {
 662         u64 from = op->addr.val;
 663         void *buf = op->data.buf.in;
 664         size_t len = op->data.nbytes;
 665
 666         if (plat->use_dac_mode && (from + len < plat->ahbsize)) {
 667                 if (len < 256 ||
 668                     dma_memcpy(buf, plat->ahbbase + from, len) < 0) {
 669                         memcpy_fromio(buf, plat->ahbbase + from, len);
 670                 }
 671                 if (!cadence_qspi_wait_idle(plat->regbase))
 672                         return -EIO;
 673                 return 0;
 674         }
 675
 676         return cadence_qspi_apb_indirect_read_execute(plat, len, buf);
 677 }
 678
 679 /* Opcode + Address (3/4 bytes) */
 680 int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
 681                                  const struct spi_mem_op *op)
 682 {
 683         unsigned int reg;
 684
 685         /* Setup the indirect trigger address */
 686         writel(plat->trigger_address,
 687                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 688
 689         /* Configure the opcode */
 690         reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 691         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 692
 693         writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 694
 695         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 696         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 697         reg |= (op->addr.nbytes - 1);
 698         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 699         return 0;
 700 }
 701
 702 static int
 703 cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 704                                         unsigned int n_tx, const u8 *txbuf)
 705 {
 706         unsigned int page_size = plat->page_size;
 707         unsigned int remaining = n_tx;
 708         const u8 *bb_txbuf = txbuf;
 709         void *bounce_buf = NULL;
 710         unsigned int write_bytes;
 711         int ret;
 712
 713         /*
 714          * Use bounce buffer for non 32 bit aligned txbuf to avoid data
 715          * aborts
 716          */
 717         if ((uintptr_t)txbuf % 4) {
 718                 bounce_buf = malloc(n_tx);
 719                 if (!bounce_buf)
 720                         return -ENOMEM;
 721                 memcpy(bounce_buf, txbuf, n_tx);
 722                 bb_txbuf = bounce_buf;
 723         }
 724
 725         /* Configure the indirect read transfer bytes */
 726         writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 727
 728         /* Start the indirect write transfer */
 729         writel(CQSPI_REG_INDIRECTWR_START,
 730                plat->regbase + CQSPI_REG_INDIRECTWR);
 731
 732         while (remaining > 0) {
 733                 write_bytes = remaining > page_size ? page_size : remaining;
 734                 writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
 735                 if (write_bytes % 4)
 736                         writesb(plat->ahbbase,
 737                                 bb_txbuf + rounddown(write_bytes, 4),
 738                                 write_bytes % 4);
 739
 740                 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
 741                                         CQSPI_REG_SDRAMLEVEL_WR_MASK <<
 742                                         CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
 743                 if (ret) {
 744                         printf("Indirect write timed out (%i)\n", ret);
 745                         goto failwr;
 746                 }
 747
 748                 bb_txbuf += write_bytes;
 749                 remaining -= write_bytes;
 750         }
 751
 752         /* Check indirect done status */
 753         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
 754                                 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
 755         if (ret) {
 756                 printf("Indirect write completion error (%i)\n", ret);
 757                 goto failwr;
 758         }
 759
 760         /* Clear indirect completion status */
 761         writel(CQSPI_REG_INDIRECTWR_DONE,
 762                plat->regbase + CQSPI_REG_INDIRECTWR);
 763         if (bounce_buf)
 764                 free(bounce_buf);
 765         return 0;
 766
 767 failwr:
 768         /* Cancel the indirect write */
 769         writel(CQSPI_REG_INDIRECTWR_CANCEL,
 770                plat->regbase + CQSPI_REG_INDIRECTWR);
 771         if (bounce_buf)
 772                 free(bounce_buf);
 773         return ret;
 774 }
 775
 776 int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
 777                                    const struct spi_mem_op *op)
 778 {
 779         u32 to = op->addr.val;
 780         const void *buf = op->data.buf.out;
 781         size_t len = op->data.nbytes;
 782
 783         if (plat->use_dac_mode && (to + len < plat->ahbsize)) {
 784                 memcpy_toio(plat->ahbbase + to, buf, len);
 785                 if (!cadence_qspi_wait_idle(plat->regbase))
 786                         return -EIO;
 787                 return 0;
 788         }
 789
 790         return cadence_qspi_apb_indirect_write_execute(plat, len, buf);
 791 }
 792
 793 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 794 {
 795         unsigned int reg;
 796
 797         /* enter XiP mode immediately and enable direct mode */
 798         reg = readl(reg_base + CQSPI_REG_CONFIG);
 799         reg |= CQSPI_REG_CONFIG_ENABLE;
 800         reg |= CQSPI_REG_CONFIG_DIRECT;
 801         reg |= CQSPI_REG_CONFIG_XIP_IMM;
 802         writel(reg, reg_base + CQSPI_REG_CONFIG);
 803
 804         /* keep the XiP mode */
 805         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 806
 807         /* Enable mode bit at devrd */
 808         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 809         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 810         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 811 }