drivers/spi/cadence_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012
   4  * Altera Corporation <www.altera.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <asm-generic/io.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <malloc.h>
  13 #include <reset.h>
  14 #include <spi.h>
  15 #include <spi-mem.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/err.h>
  18 #include <linux/errno.h>
  19 #include <linux/sizes.h>
  20 #include "cadence_qspi.h"
  21
  22 #define CQSPI_STIG_READ                 0
  23 #define CQSPI_STIG_WRITE                1
  24 #define CQSPI_READ                      2
  25 #define CQSPI_WRITE                     3
  26
  27 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
  28 {
  29         struct cadence_spi_platdata *plat = bus->platdata;
  30         struct cadence_spi_priv *priv = dev_get_priv(bus);
  31
  32         cadence_qspi_apb_config_baudrate_div(priv->regbase,
  33                                              plat->ref_clk_hz, hz);
  34
  35         /* Reconfigure delay timing if speed is changed. */
  36         cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
  37                                plat->tshsl_ns, plat->tsd2d_ns,
  38                                plat->tchsh_ns, plat->tslch_ns);
  39
  40         return 0;
  41 }
  42
  43 static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
  44 {
  45         struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
  46                                           SPI_MEM_OP_NO_ADDR,
  47                                           SPI_MEM_OP_NO_DUMMY,
  48                                           SPI_MEM_OP_DATA_IN(len, idcode, 1));
  49
  50         return cadence_qspi_apb_command_read(reg_base, &op);
  51 }
  52
  53 /* Calibration sequence to determine the read data capture delay register */
  54 static int spi_calibration(struct udevice *bus, uint hz)
  55 {
  56         struct cadence_spi_priv *priv = dev_get_priv(bus);
  57         void *base = priv->regbase;
  58         unsigned int idcode = 0, temp = 0;
  59         int err = 0, i, range_lo = -1, range_hi = -1;
  60
  61         /* start with slowest clock (1 MHz) */
  62         cadence_spi_write_speed(bus, 1000000);
  63
  64         /* configure the read data capture delay register to 0 */
  65         cadence_qspi_apb_readdata_capture(base, 1, 0);
  66
  67         /* Enable QSPI */
  68         cadence_qspi_apb_controller_enable(base);
  69
  70         /* read the ID which will be our golden value */
  71         err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
  72         if (err) {
  73                 puts("SF: Calibration failed (read)\n");
  74                 return err;
  75         }
  76
  77         /* use back the intended clock and find low range */
  78         cadence_spi_write_speed(bus, hz);
  79         for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
  80                 /* Disable QSPI */
  81                 cadence_qspi_apb_controller_disable(base);
  82
  83                 /* reconfigure the read data capture delay register */
  84                 cadence_qspi_apb_readdata_capture(base, 1, i);
  85
  86                 /* Enable back QSPI */
  87                 cadence_qspi_apb_controller_enable(base);
  88
  89                 /* issue a RDID to get the ID value */
  90                 err = cadence_spi_read_id(base, 3, (u8 *)&temp);
  91                 if (err) {
  92                         puts("SF: Calibration failed (read)\n");
  93                         return err;
  94                 }
  95
  96                 /* search for range lo */
  97                 if (range_lo == -1 && temp == idcode) {
  98                         range_lo = i;
  99                         continue;
 100                 }
 101
 102                 /* search for range hi */
 103                 if (range_lo != -1 && temp != idcode) {
 104                         range_hi = i - 1;
 105                         break;
 106                 }
 107                 range_hi = i;
 108         }
 109
 110         if (range_lo == -1) {
 111                 puts("SF: Calibration failed (low range)\n");
 112                 return err;
 113         }
 114
 115         /* Disable QSPI for subsequent initialization */
 116         cadence_qspi_apb_controller_disable(base);
 117
 118         /* configure the final value for read data capture delay register */
 119         cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
 120         debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
 121               (range_hi + range_lo) / 2, range_lo, range_hi);
 122
 123         /* just to ensure we do once only when speed or chip select change */
 124         priv->qspi_calibrated_hz = hz;
 125         priv->qspi_calibrated_cs = spi_chip_select(bus);
 126
 127         return 0;
 128 }
 129
 130 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
 131 {
 132         struct cadence_spi_platdata *plat = bus->platdata;
 133         struct cadence_spi_priv *priv = dev_get_priv(bus);
 134         int err;
 135
 136         if (hz > plat->max_hz)
 137                 hz = plat->max_hz;
 138
 139         /* Disable QSPI */
 140         cadence_qspi_apb_controller_disable(priv->regbase);
 141
 142         /*
 143          * Calibration required for different current SCLK speed, requested
 144          * SCLK speed or chip select
 145          */
 146         if (priv->previous_hz != hz ||
 147             priv->qspi_calibrated_hz != hz ||
 148             priv->qspi_calibrated_cs != spi_chip_select(bus)) {
 149                 err = spi_calibration(bus, hz);
 150                 if (err)
 151                         return err;
 152
 153                 /* prevent calibration run when same as previous request */
 154                 priv->previous_hz = hz;
 155         }
 156
 157         /* Enable QSPI */
 158         cadence_qspi_apb_controller_enable(priv->regbase);
 159
 160         debug("%s: speed=%d\n", __func__, hz);
 161
 162         return 0;
 163 }
 164
 165 static int cadence_spi_probe(struct udevice *bus)
 166 {
 167         struct cadence_spi_platdata *plat = bus->platdata;
 168         struct cadence_spi_priv *priv = dev_get_priv(bus);
 169         int ret;
 170
 171         priv->regbase = plat->regbase;
 172         priv->ahbbase = plat->ahbbase;
 173
 174         ret = reset_get_bulk(bus, &priv->resets);
 175         if (ret)
 176                 dev_warn(bus, "Can't get reset: %d\n", ret);
 177         else
 178                 reset_deassert_bulk(&priv->resets);
 179
 180         if (!priv->qspi_is_init) {
 181                 cadence_qspi_apb_controller_init(plat);
 182                 priv->qspi_is_init = 1;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static int cadence_spi_remove(struct udevice *dev)
 189 {
 190         struct cadence_spi_priv *priv = dev_get_priv(dev);
 191
 192         return reset_release_bulk(&priv->resets);
 193 }
 194
 195 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
 196 {
 197         struct cadence_spi_platdata *plat = bus->platdata;
 198         struct cadence_spi_priv *priv = dev_get_priv(bus);
 199
 200         /* Disable QSPI */
 201         cadence_qspi_apb_controller_disable(priv->regbase);
 202
 203         /* Set SPI mode */
 204         cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
 205
 206         /* Enable Direct Access Controller */
 207         if (plat->use_dac_mode)
 208                 cadence_qspi_apb_dac_mode_enable(priv->regbase);
 209
 210         /* Enable QSPI */
 211         cadence_qspi_apb_controller_enable(priv->regbase);
 212
 213         return 0;
 214 }
 215
 216 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
 217                                    const struct spi_mem_op *op)
 218 {
 219         struct udevice *bus = spi->dev->parent;
 220         struct cadence_spi_platdata *plat = bus->platdata;
 221         struct cadence_spi_priv *priv = dev_get_priv(bus);
 222         void *base = priv->regbase;
 223         int err = 0;
 224         u32 mode;
 225
 226         /* Set Chip select */
 227         cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
 228                                     plat->is_decoded_cs);
 229
 230         if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
 231                 if (!op->addr.nbytes)
 232                         mode = CQSPI_STIG_READ;
 233                 else
 234                         mode = CQSPI_READ;
 235         } else {
 236                 if (!op->addr.nbytes || !op->data.buf.out)
 237                         mode = CQSPI_STIG_WRITE;
 238                 else
 239                         mode = CQSPI_WRITE;
 240         }
 241
 242         switch (mode) {
 243         case CQSPI_STIG_READ:
 244                 err = cadence_qspi_apb_command_read(base, op);
 245                 break;
 246         case CQSPI_STIG_WRITE:
 247                 err = cadence_qspi_apb_command_write(base, op);
 248                 break;
 249         case CQSPI_READ:
 250                 err = cadence_qspi_apb_read_setup(plat, op);
 251                 if (!err)
 252                         err = cadence_qspi_apb_read_execute(plat, op);
 253                 break;
 254         case CQSPI_WRITE:
 255                 err = cadence_qspi_apb_write_setup(plat, op);
 256                 if (!err)
 257                         err = cadence_qspi_apb_write_execute(plat, op);
 258                 break;
 259         default:
 260                 err = -1;
 261                 break;
 262         }
 263
 264         return err;
 265 }
 266
 267 static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 268 {
 269         struct cadence_spi_platdata *plat = bus->platdata;
 270         ofnode subnode;
 271         struct clk clk;
 272         int ret;
 273
 274         plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
 275         plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
 276                         &plat->ahbsize);
 277         plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
 278         plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
 279         plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
 280         plat->trigger_address = dev_read_u32_default(bus,
 281                                                      "cdns,trigger-address",
 282                                                      0);
 283         /* Use DAC mode only when MMIO window is at least 8M wide */
 284         if (plat->ahbsize >= SZ_8M)
 285                 plat->use_dac_mode = true;
 286
 287         /* All other paramters are embedded in the child node */
 288         subnode = dev_read_first_subnode(bus);
 289         if (!ofnode_valid(subnode)) {
 290                 printf("Error: subnode with SPI flash config missing!\n");
 291                 return -ENODEV;
 292         }
 293
 294         /* Use 500 KHz as a suitable default */
 295         plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
 296                                                500000);
 297
 298         /* Read other parameters from DT */
 299         plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
 300         plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
 301         plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
 302                                                  200);
 303         plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
 304                                                  255);
 305         plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
 306         plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
 307
 308         ret = clk_get_by_index(bus, 0, &clk);
 309         if (ret) {
 310 #ifdef CONFIG_CQSPI_REF_CLK
 311                 plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
 312 #else
 313                 return ret;
 314 #endif
 315         } else {
 316                 plat->ref_clk_hz = clk_get_rate(&clk);
 317                 clk_free(&clk);
 318                 if (IS_ERR_VALUE(plat->ref_clk_hz))
 319                         return plat->ref_clk_hz;
 320         }
 321
 322         debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
 323               __func__, plat->regbase, plat->ahbbase, plat->max_hz,
 324               plat->page_size);
 325
 326         return 0;
 327 }
 328
 329 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
 330         .exec_op = cadence_spi_mem_exec_op,
 331 };
 332
 333 static const struct dm_spi_ops cadence_spi_ops = {
 334         .set_speed      = cadence_spi_set_speed,
 335         .set_mode       = cadence_spi_set_mode,
 336         .mem_ops        = &cadence_spi_mem_ops,
 337         /*
 338          * cs_info is not needed, since we require all chip selects to be
 339          * in the device tree explicitly
 340          */
 341 };
 342
 343 static const struct udevice_id cadence_spi_ids[] = {
 344         { .compatible = "cdns,qspi-nor" },
 345         { .compatible = "ti,am654-ospi" },
 346         { }
 347 };
 348
 349 U_BOOT_DRIVER(cadence_spi) = {
 350         .name = "cadence_spi",
 351         .id = UCLASS_SPI,
 352         .of_match = cadence_spi_ids,
 353         .ops = &cadence_spi_ops,
 354         .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
 355         .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
 356         .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
 357         .probe = cadence_spi_probe,
 358         .remove = cadence_spi_remove,
 359         .flags = DM_FLAG_OS_PREPARE,
 360 };