drivers/sound/wm8994.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Samsung Electronics
   4  * R. Chandrasekar <rcsekar@samsung.com>
   5  */
   6 #include <common.h>
   7 #include <div64.h>
   8 #include <fdtdec.h>
   9 #include <i2c.h>
  10 #include <i2s.h>
  11 #include <sound.h>
  12 #include <asm/gpio.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/sound.h>
  17 #include "wm8994.h"
  18 #include "wm8994_registers.h"
  19
  20 /* defines for wm8994 system clock selection */
  21 #define SEL_MCLK1       0x00
  22 #define SEL_MCLK2       0x08
  23 #define SEL_FLL1        0x10
  24 #define SEL_FLL2        0x18
  25
  26 /* fll config to configure fll */
  27 struct wm8994_fll_config {
  28         int src;        /* Source */
  29         int in;         /* Input frequency in Hz */
  30         int out;        /* output frequency in Hz */
  31 };
  32
  33 /* codec private data */
  34 struct wm8994_priv {
  35         enum wm8994_type type;          /* codec type of wolfson */
  36         int revision;                   /* Revision */
  37         int sysclk[WM8994_MAX_AIF];     /* System clock frequency in Hz  */
  38         int mclk[WM8994_MAX_AIF];       /* master clock frequency in Hz */
  39         int aifclk[WM8994_MAX_AIF];     /* audio interface clock in Hz   */
  40         struct wm8994_fll_config fll[2]; /* fll config to configure fll */
  41         int i2c_addr;
  42 };
  43
  44 /* wm 8994 supported sampling rate values */
  45 static unsigned int src_rate[] = {
  46                          8000, 11025, 12000, 16000, 22050, 24000,
  47                          32000, 44100, 48000, 88200, 96000
  48 };
  49
  50 /* op clock divisions */
  51 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
  52
  53 /* lr clock frame size ratio */
  54 static int fs_ratios[] = {
  55         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
  56 };
  57
  58 /* bit clock divisors */
  59 static int bclk_divs[] = {
  60         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
  61         640, 880, 960, 1280, 1760, 1920
  62 };
  63
  64 /*
  65  * Writes value to a device register through i2c
  66  *
  67  * @param priv  Private data for driver
  68  * @param reg   reg number to be write
  69  * @param data  data to be writen to the above registor
  70  *
  71  * @return      int value 1 for change, 0 for no change or negative error code.
  72  */
  73 static int wm8994_i2c_write(struct wm8994_priv *priv, unsigned int reg,
  74                             unsigned short data)
  75 {
  76         unsigned char val[2];
  77
  78         val[0] = (unsigned char)((data >> 8) & 0xff);
  79         val[1] = (unsigned char)(data & 0xff);
  80         debug("Write Addr : 0x%04X, Data :  0x%04X\n", reg, data);
  81
  82         return i2c_write(priv->i2c_addr, reg, 2, val, 2);
  83 }
  84
  85 /*
  86  * Read a value from a device register through i2c
  87  *
  88  * @param priv  Private data for driver
  89  * @param reg   reg number to be read
  90  * @param data  address of read data to be stored
  91  *
  92  * @return      int value 0 for success, -1 in case of error.
  93  */
  94 static unsigned int wm8994_i2c_read(struct wm8994_priv *priv, unsigned int reg,
  95                                     unsigned short *data)
  96 {
  97         unsigned char val[2];
  98         int ret;
  99
 100         ret = i2c_read(priv->i2c_addr, reg, 2, val, 2);
 101         if (ret != 0) {
 102                 debug("%s: Error while reading register %#04x\n",
 103                       __func__, reg);
 104                 return -1;
 105         }
 106
 107         *data = val[0];
 108         *data <<= 8;
 109         *data |= val[1];
 110
 111         return 0;
 112 }
 113
 114 /*
 115  * update device register bits through i2c
 116  *
 117  * @param priv  Private data for driver
 118  * @param reg   codec register
 119  * @param mask  register mask
 120  * @param value new value
 121  *
 122  * @return int value 1 if change in the register value,
 123  * 0 for no change or negative error code.
 124  */
 125 static int wm8994_bic_or(struct wm8994_priv *priv, unsigned int reg,
 126                          unsigned short mask, unsigned short value)
 127 {
 128         int change , ret = 0;
 129         unsigned short old, new;
 130
 131         if (wm8994_i2c_read(priv, reg, &old) != 0)
 132                 return -1;
 133         new = (old & ~mask) | (value & mask);
 134         change  = (old != new) ? 1 : 0;
 135         if (change)
 136                 ret = wm8994_i2c_write(priv, reg, new);
 137         if (ret < 0)
 138                 return ret;
 139
 140         return change;
 141 }
 142
 143 /*
 144  * Sets i2s set format
 145  *
 146  * @param priv          wm8994 information
 147  * @param aif_id        Interface ID
 148  * @param fmt           i2S format
 149  *
 150  * @return -1 for error and 0  Success.
 151  */
 152 static int wm8994_set_fmt(struct wm8994_priv *priv, int aif_id, uint fmt)
 153 {
 154         int ms_reg;
 155         int aif_reg;
 156         int ms = 0;
 157         int aif = 0;
 158         int aif_clk = 0;
 159         int error = 0;
 160
 161         switch (aif_id) {
 162         case 1:
 163                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
 164                 aif_reg = WM8994_AIF1_CONTROL_1;
 165                 aif_clk = WM8994_AIF1_CLOCKING_1;
 166                 break;
 167         case 2:
 168                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
 169                 aif_reg = WM8994_AIF2_CONTROL_1;
 170                 aif_clk = WM8994_AIF2_CLOCKING_1;
 171                 break;
 172         default:
 173                 debug("%s: Invalid audio interface selection\n", __func__);
 174                 return -1;
 175         }
 176
 177         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 178         case SND_SOC_DAIFMT_CBS_CFS:
 179                 break;
 180         case SND_SOC_DAIFMT_CBM_CFM:
 181                 ms = WM8994_AIF1_MSTR;
 182                 break;
 183         default:
 184                 debug("%s: Invalid i2s master selection\n", __func__);
 185                 return -1;
 186         }
 187
 188         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 189         case SND_SOC_DAIFMT_DSP_B:
 190                 aif |= WM8994_AIF1_LRCLK_INV;
 191         case SND_SOC_DAIFMT_DSP_A:
 192                 aif |= 0x18;
 193                 break;
 194         case SND_SOC_DAIFMT_I2S:
 195                 aif |= 0x10;
 196                 break;
 197         case SND_SOC_DAIFMT_RIGHT_J:
 198                 break;
 199         case SND_SOC_DAIFMT_LEFT_J:
 200                 aif |= 0x8;
 201                 break;
 202         default:
 203                 debug("%s: Invalid i2s format selection\n", __func__);
 204                 return -1;
 205         }
 206
 207         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 208         case SND_SOC_DAIFMT_DSP_A:
 209         case SND_SOC_DAIFMT_DSP_B:
 210                 /* frame inversion not valid for DSP modes */
 211                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 212                 case SND_SOC_DAIFMT_NB_NF:
 213                         break;
 214                 case SND_SOC_DAIFMT_IB_NF:
 215                         aif |= WM8994_AIF1_BCLK_INV;
 216                         break;
 217                 default:
 218                         debug("%s: Invalid i2s frame inverse selection\n",
 219                               __func__);
 220                         return -1;
 221                 }
 222                 break;
 223
 224         case SND_SOC_DAIFMT_I2S:
 225         case SND_SOC_DAIFMT_RIGHT_J:
 226         case SND_SOC_DAIFMT_LEFT_J:
 227                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 228                 case SND_SOC_DAIFMT_NB_NF:
 229                         break;
 230                 case SND_SOC_DAIFMT_IB_IF:
 231                         aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
 232                         break;
 233                 case SND_SOC_DAIFMT_IB_NF:
 234                         aif |= WM8994_AIF1_BCLK_INV;
 235                         break;
 236                 case SND_SOC_DAIFMT_NB_IF:
 237                         aif |= WM8994_AIF1_LRCLK_INV;
 238                         break;
 239                 default:
 240                         debug("%s: Invalid i2s clock polarity selection\n",
 241                               __func__);
 242                         return -1;
 243                 }
 244                 break;
 245         default:
 246                 debug("%s: Invalid i2s format selection\n", __func__);
 247                 return -1;
 248         }
 249
 250         error = wm8994_bic_or(priv, aif_reg, WM8994_AIF1_BCLK_INV |
 251                               WM8994_AIF1_LRCLK_INV_MASK |
 252                                WM8994_AIF1_FMT_MASK, aif);
 253
 254         error |= wm8994_bic_or(priv, ms_reg, WM8994_AIF1_MSTR_MASK, ms);
 255         error |= wm8994_bic_or(priv, aif_clk, WM8994_AIF1CLK_ENA_MASK,
 256                                WM8994_AIF1CLK_ENA);
 257         if (error < 0) {
 258                 debug("%s: codec register access error\n", __func__);
 259                 return -1;
 260         }
 261
 262         return 0;
 263 }
 264
 265 /*
 266  * Sets hw params FOR WM8994
 267  *
 268  * @param priv                  wm8994 information pointer
 269  * @param aif_id                Audio interface ID
 270  * @param sampling_rate         Sampling rate
 271  * @param bits_per_sample       Bits per sample
 272  * @param Channels              Channels in the given audio input
 273  *
 274  * @return -1 for error  and 0  Success.
 275  */
 276 static int wm8994_hw_params(struct wm8994_priv *priv, int aif_id,
 277                             uint sampling_rate, uint bits_per_sample,
 278                             uint channels)
 279 {
 280         int aif1_reg;
 281         int aif2_reg;
 282         int bclk_reg;
 283         int bclk = 0;
 284         int rate_reg;
 285         int aif1 = 0;
 286         int aif2 = 0;
 287         int rate_val = 0;
 288         int id = aif_id - 1;
 289         int i, cur_val, best_val, bclk_rate, best;
 290         unsigned short reg_data;
 291         int ret = 0;
 292
 293         switch (aif_id) {
 294         case 1:
 295                 aif1_reg = WM8994_AIF1_CONTROL_1;
 296                 aif2_reg = WM8994_AIF1_CONTROL_2;
 297                 bclk_reg = WM8994_AIF1_BCLK;
 298                 rate_reg = WM8994_AIF1_RATE;
 299                 break;
 300         case 2:
 301                 aif1_reg = WM8994_AIF2_CONTROL_1;
 302                 aif2_reg = WM8994_AIF2_CONTROL_2;
 303                 bclk_reg = WM8994_AIF2_BCLK;
 304                 rate_reg = WM8994_AIF2_RATE;
 305                 break;
 306         default:
 307                 return -1;
 308         }
 309
 310         bclk_rate = sampling_rate * 32;
 311         switch (bits_per_sample) {
 312         case 16:
 313                 bclk_rate *= 16;
 314                 break;
 315         case 20:
 316                 bclk_rate *= 20;
 317                 aif1 |= 0x20;
 318                 break;
 319         case 24:
 320                 bclk_rate *= 24;
 321                 aif1 |= 0x40;
 322                 break;
 323         case 32:
 324                 bclk_rate *= 32;
 325                 aif1 |= 0x60;
 326                 break;
 327         default:
 328                 return -1;
 329         }
 330
 331         /* Try to find an appropriate sample rate; look for an exact match. */
 332         for (i = 0; i < ARRAY_SIZE(src_rate); i++)
 333                 if (src_rate[i] == sampling_rate)
 334                         break;
 335
 336         if (i == ARRAY_SIZE(src_rate)) {
 337                 debug("%s: Could not get the best matching samplingrate\n",
 338                       __func__);
 339                 return -1;
 340         }
 341
 342         rate_val |= i << WM8994_AIF1_SR_SHIFT;
 343
 344         /* AIFCLK/fs ratio; look for a close match in either direction */
 345         best = 0;
 346         best_val = abs((fs_ratios[0] * sampling_rate) - priv->aifclk[id]);
 347
 348         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
 349                 cur_val = abs(fs_ratios[i] * sampling_rate - priv->aifclk[id]);
 350                 if (cur_val >= best_val)
 351                         continue;
 352                 best = i;
 353                 best_val = cur_val;
 354         }
 355
 356         rate_val |= best;
 357
 358         /*
 359          * We may not get quite the right frequency if using
 360          * approximate clocks so look for the closest match that is
 361          * higher than the target (we need to ensure that there enough
 362          * BCLKs to clock out the samples).
 363          */
 364         best = 0;
 365         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
 366                 cur_val = (priv->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
 367                 if (cur_val < 0) /* BCLK table is sorted */
 368                         break;
 369                 best = i;
 370         }
 371
 372         if (i ==  ARRAY_SIZE(bclk_divs)) {
 373                 debug("%s: Could not get the best matching bclk division\n",
 374                       __func__);
 375                 return -1;
 376         }
 377
 378         bclk_rate = priv->aifclk[id] * 10 / bclk_divs[best];
 379         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
 380
 381         if (wm8994_i2c_read(priv, aif1_reg, &reg_data) != 0) {
 382                 debug("%s: AIF1 register read Failed\n", __func__);
 383                 return -1;
 384         }
 385
 386         if ((channels == 1) && ((reg_data & 0x18) == 0x18))
 387                 aif2 |= WM8994_AIF1_MONO;
 388
 389         if (priv->aifclk[id] == 0) {
 390                 debug("%s:Audio interface clock not set\n", __func__);
 391                 return -1;
 392         }
 393
 394         ret = wm8994_bic_or(priv, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
 395         ret |= wm8994_bic_or(priv, aif2_reg, WM8994_AIF1_MONO, aif2);
 396         ret |= wm8994_bic_or(priv, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK,
 397                                   bclk);
 398         ret |= wm8994_bic_or(priv, rate_reg, WM8994_AIF1_SR_MASK |
 399                                   WM8994_AIF1CLK_RATE_MASK, rate_val);
 400
 401         debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
 402
 403         if (ret < 0) {
 404                 debug("%s: codec register access error\n", __func__);
 405                 return -1;
 406         }
 407
 408         return 0;
 409 }
 410
 411 /*
 412  * Configures Audio interface Clock
 413  *
 414  * @param priv          wm8994 information pointer
 415  * @param aif           Audio Interface ID
 416  *
 417  * @return -1 for error  and 0  Success.
 418  */
 419 static int configure_aif_clock(struct wm8994_priv *priv, int aif)
 420 {
 421         int rate;
 422         int reg1 = 0;
 423         int offset;
 424         int ret;
 425
 426         /* AIF(1/0) register adress offset calculated */
 427         if (aif-1)
 428                 offset = 4;
 429         else
 430                 offset = 0;
 431
 432         switch (priv->sysclk[aif - 1]) {
 433         case WM8994_SYSCLK_MCLK1:
 434                 reg1 |= SEL_MCLK1;
 435                 rate = priv->mclk[0];
 436                 break;
 437
 438         case WM8994_SYSCLK_MCLK2:
 439                 reg1 |= SEL_MCLK2;
 440                 rate = priv->mclk[1];
 441                 break;
 442
 443         case WM8994_SYSCLK_FLL1:
 444                 reg1 |= SEL_FLL1;
 445                 rate = priv->fll[0].out;
 446                 break;
 447
 448         case WM8994_SYSCLK_FLL2:
 449                 reg1 |= SEL_FLL2;
 450                 rate = priv->fll[1].out;
 451                 break;
 452
 453         default:
 454                 debug("%s: Invalid input clock selection [%d]\n",
 455                       __func__, priv->sysclk[aif - 1]);
 456                 return -1;
 457         }
 458
 459         /* if input clock frequenct is more than 135Mhz then divide */
 460         if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
 461                 rate /= 2;
 462                 reg1 |= WM8994_AIF1CLK_DIV;
 463         }
 464
 465         priv->aifclk[aif - 1] = rate;
 466
 467         ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_1 + offset,
 468                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 469                             reg1);
 470
 471         if (aif == WM8994_AIF1)
 472                 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
 473                         WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK,
 474                         WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
 475         else if (aif == WM8994_AIF2)
 476                 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
 477                         WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
 478                         WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
 479                         WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
 480
 481         if (ret < 0) {
 482                 debug("%s: codec register access error\n", __func__);
 483                 return -1;
 484         }
 485
 486         return 0;
 487 }
 488
 489 /*
 490  * Configures Audio interface  for the given frequency
 491  *
 492  * @param priv          wm8994 information
 493  * @param aif_id        Audio Interface
 494  * @param clk_id        Input Clock ID
 495  * @param freq          Sampling frequency in Hz
 496  *
 497  * @return -1 for error and 0 success.
 498  */
 499 static int wm8994_set_sysclk(struct wm8994_priv *priv, int aif_id, int clk_id,
 500                              unsigned int freq)
 501 {
 502         int i;
 503         int ret = 0;
 504
 505         priv->sysclk[aif_id - 1] = clk_id;
 506
 507         switch (clk_id) {
 508         case WM8994_SYSCLK_MCLK1:
 509                 priv->mclk[0] = freq;
 510                 if (aif_id == 2) {
 511                         ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_2,
 512                                             WM8994_AIF2DAC_DIV_MASK, 0);
 513                 }
 514                 break;
 515
 516         case WM8994_SYSCLK_MCLK2:
 517                 /* TODO: Set GPIO AF */
 518                 priv->mclk[1] = freq;
 519                 break;
 520
 521         case WM8994_SYSCLK_FLL1:
 522         case WM8994_SYSCLK_FLL2:
 523                 break;
 524
 525         case WM8994_SYSCLK_OPCLK:
 526                 /*
 527                  * Special case - a division (times 10) is given and
 528                  * no effect on main clocking.
 529                  */
 530                 if (freq) {
 531                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
 532                                 if (opclk_divs[i] == freq)
 533                                         break;
 534                         if (i == ARRAY_SIZE(opclk_divs)) {
 535                                 debug("%s frequency divisor not found\n",
 536                                       __func__);
 537                                 return -1;
 538                         }
 539                         ret = wm8994_bic_or(priv, WM8994_CLOCKING_2,
 540                                             WM8994_OPCLK_DIV_MASK, i);
 541                         ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
 542                                              WM8994_OPCLK_ENA,
 543                                              WM8994_OPCLK_ENA);
 544                 } else {
 545                         ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
 546                                              WM8994_OPCLK_ENA, 0);
 547                 }
 548
 549         default:
 550                 debug("%s Invalid input clock selection [%d]\n",
 551                       __func__, clk_id);
 552                 return -1;
 553         }
 554
 555         ret |= configure_aif_clock(priv, aif_id);
 556
 557         if (ret < 0) {
 558                 debug("%s: codec register access error\n", __func__);
 559                 return -1;
 560         }
 561
 562         return 0;
 563 }
 564
 565 /*
 566  * Initializes Volume for AIF2 to HP path
 567  *
 568  * @param priv          wm8994 information
 569  * @returns -1 for error  and 0 Success.
 570  *
 571  */
 572 static int wm8994_init_volume_aif2_dac1(struct wm8994_priv *priv)
 573 {
 574         int ret;
 575
 576         /* Unmute AIF2DAC */
 577         ret = wm8994_bic_or(priv, WM8994_AIF2_DAC_FILTERS_1,
 578                             WM8994_AIF2DAC_MUTE_MASK, 0);
 579
 580
 581         ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_LEFT_VOLUME,
 582                              WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
 583                              WM8994_AIF2DAC_VU | 0xff);
 584
 585         ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_RIGHT_VOLUME,
 586                              WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
 587                              WM8994_AIF2DAC_VU | 0xff);
 588
 589
 590         ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
 591                              WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
 592                              WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
 593
 594         ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
 595                              WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
 596                              WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
 597         /* Head Phone Volume */
 598         ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
 599         ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
 600
 601         if (ret < 0) {
 602                 debug("%s: codec register access error\n", __func__);
 603                 return -1;
 604         }
 605
 606         return 0;
 607 }
 608
 609 /*
 610  * Initializes Volume for AIF1 to HP path
 611  *
 612  * @param priv          wm8994 information
 613  * @returns -1 for error  and 0 Success.
 614  *
 615  */
 616 static int wm8994_init_volume_aif1_dac1(struct wm8994_priv *priv)
 617 {
 618         int ret = 0;
 619
 620         /* Unmute AIF1DAC */
 621         ret |= wm8994_i2c_write(priv, WM8994_AIF1_DAC_FILTERS_1, 0x0000);
 622
 623         ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
 624                              WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
 625                              WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
 626
 627         ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
 628                              WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
 629                              WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
 630         /* Head Phone Volume */
 631         ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
 632         ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
 633
 634         if (ret < 0) {
 635                 debug("%s: codec register access error\n", __func__);
 636                 return -1;
 637         }
 638
 639         return 0;
 640 }
 641
 642 /*
 643  * Intialise wm8994 codec device
 644  *
 645  * @param priv          wm8994 information
 646  *
 647  * @returns -1 for error  and 0 Success.
 648  */
 649 static int wm8994_device_init(struct wm8994_priv *priv)
 650 {
 651         const char *devname;
 652         unsigned short reg_data;
 653         int ret;
 654
 655         wm8994_i2c_write(priv, WM8994_SOFTWARE_RESET, WM8994_SW_RESET);
 656
 657         ret = wm8994_i2c_read(priv, WM8994_SOFTWARE_RESET, &reg_data);
 658         if (ret < 0) {
 659                 debug("Failed to read ID register\n");
 660                 return ret;
 661         }
 662
 663         if (reg_data == WM8994_ID) {
 664                 devname = "WM8994";
 665                 debug("Device registered as type %d\n", priv->type);
 666                 priv->type = WM8994;
 667         } else {
 668                 debug("Device is not a WM8994, ID is %x\n", ret);
 669                 return -ENXIO;
 670         }
 671
 672         ret = wm8994_i2c_read(priv, WM8994_CHIP_REVISION, &reg_data);
 673         if (ret < 0) {
 674                 debug("Failed to read revision register: %d\n", ret);
 675                 return ret;
 676         }
 677         priv->revision = reg_data;
 678         debug("%s revision %c\n", devname, 'A' + priv->revision);
 679
 680         return 0;
 681 }
 682
 683 static int wm8994_setup_interface(struct wm8994_priv *priv,
 684                                   enum en_audio_interface aif_id)
 685 {
 686         int ret;
 687
 688         /* VMID Selection */
 689         ret = wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
 690                             WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
 691
 692         /* Charge Pump Enable */
 693         ret |= wm8994_bic_or(priv, WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
 694                              WM8994_CP_ENA);
 695
 696         /* Head Phone Power Enable */
 697         ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
 698                              WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
 699
 700         ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
 701                              WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
 702
 703         if (aif_id == WM8994_AIF1) {
 704                 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_2,
 705                                         WM8994_TSHUT_ENA | WM8994_MIXINL_ENA |
 706                                         WM8994_MIXINR_ENA | WM8994_IN2L_ENA |
 707                                         WM8994_IN2R_ENA);
 708
 709                 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_4,
 710                                         WM8994_ADCL_ENA | WM8994_ADCR_ENA |
 711                                         WM8994_AIF1ADC1R_ENA |
 712                                         WM8994_AIF1ADC1L_ENA);
 713
 714                 /* Power enable for AIF1 and DAC1 */
 715                 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_5,
 716                                         WM8994_AIF1DACL_ENA |
 717                                         WM8994_AIF1DACR_ENA |
 718                                         WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
 719         } else if (aif_id == WM8994_AIF2) {
 720                 /* Power enable for AIF2 and DAC1 */
 721                 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_5,
 722                         WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
 723                         WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
 724                         WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
 725                         WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
 726         }
 727         /* Head Phone Initialisation */
 728         ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
 729                 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
 730                 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
 731
 732         ret |= wm8994_bic_or(priv, WM8994_DC_SERVO_1,
 733                         WM8994_DCS_ENA_CHAN_0_MASK |
 734                         WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
 735                         WM8994_DCS_ENA_CHAN_1);
 736
 737         ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
 738                         WM8994_HPOUT1L_DLY_MASK |
 739                         WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
 740                         WM8994_HPOUT1R_OUTP_MASK |
 741                         WM8994_HPOUT1L_RMV_SHORT_MASK |
 742                         WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
 743                         WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
 744                         WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
 745                         WM8994_HPOUT1R_RMV_SHORT);
 746
 747         /* MIXER Config DAC1 to HP */
 748         ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_1,
 749                              WM8994_DAC1L_TO_HPOUT1L_MASK,
 750                              WM8994_DAC1L_TO_HPOUT1L);
 751
 752         ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_2,
 753                              WM8994_DAC1R_TO_HPOUT1R_MASK,
 754                              WM8994_DAC1R_TO_HPOUT1R);
 755
 756         if (aif_id == WM8994_AIF1) {
 757                 /* Routing AIF1 to DAC1 */
 758                 ret |= wm8994_i2c_write(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
 759                                         WM8994_AIF1DAC1L_TO_DAC1L);
 760
 761                 ret |= wm8994_i2c_write(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
 762                                         WM8994_AIF1DAC1R_TO_DAC1R);
 763
 764                 /* GPIO Settings for AIF1 */
 765                 ret |=  wm8994_i2c_write(priv, WM8994_GPIO_1,
 766                                          WM8994_GPIO_DIR_OUTPUT |
 767                                          WM8994_GPIO_FUNCTION_I2S_CLK |
 768                                          WM8994_GPIO_INPUT_DEBOUNCE);
 769
 770                 ret |= wm8994_init_volume_aif1_dac1(priv);
 771         } else if (aif_id == WM8994_AIF2) {
 772                 /* Routing AIF2 to DAC1 */
 773                 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
 774                                      WM8994_AIF2DACL_TO_DAC1L_MASK,
 775                                      WM8994_AIF2DACL_TO_DAC1L);
 776
 777                 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
 778                                      WM8994_AIF2DACR_TO_DAC1R_MASK,
 779                                      WM8994_AIF2DACR_TO_DAC1R);
 780
 781                 /* GPIO Settings for AIF2 */
 782                 /* B CLK */
 783                 ret |= wm8994_bic_or(priv, WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
 784                                      WM8994_GPIO_FUNCTION_MASK,
 785                                      WM8994_GPIO_DIR_OUTPUT);
 786
 787                 /* LR CLK */
 788                 ret |= wm8994_bic_or(priv, WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
 789                                      WM8994_GPIO_FUNCTION_MASK,
 790                                      WM8994_GPIO_DIR_OUTPUT);
 791
 792                 /* DATA */
 793                 ret |= wm8994_bic_or(priv, WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
 794                                      WM8994_GPIO_FUNCTION_MASK,
 795                                      WM8994_GPIO_DIR_OUTPUT);
 796
 797                 ret |= wm8994_init_volume_aif2_dac1(priv);
 798         }
 799
 800         if (ret < 0)
 801                 goto err;
 802
 803         debug("%s: Codec chip setup ok\n", __func__);
 804         return 0;
 805 err:
 806         debug("%s: Codec chip setup error\n", __func__);
 807         return -1;
 808 }
 809
 810 /*
 811  * Gets fdt values for wm8994 config parameters
 812  *
 813  * @param pcodec_info   codec information structure
 814  * @param blob          FDT blob
 815  * @return              int value, 0 for success
 816  */
 817 static int get_codec_values(struct sound_codec_info *pcodec_info,
 818                             const void *blob)
 819 {
 820         int error = 0;
 821         enum fdt_compat_id compat;
 822         int node;
 823         int parent;
 824
 825         /* Get the node from FDT for codec */
 826         node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC);
 827         if (node <= 0) {
 828                 debug("EXYNOS_SOUND: No node for codec in device tree\n");
 829                 debug("node = %d\n", node);
 830                 return -1;
 831         }
 832
 833         parent = fdt_parent_offset(blob, node);
 834         if (parent < 0) {
 835                 debug("%s: Cannot find node parent\n", __func__);
 836                 return -1;
 837         }
 838
 839         compat = fdtdec_lookup(blob, parent);
 840         switch (compat) {
 841         case COMPAT_SAMSUNG_S3C2440_I2C:
 842                 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
 843                 error |= pcodec_info->i2c_bus;
 844                 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
 845                 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
 846                                                         "reg", 0);
 847                 error |= pcodec_info->i2c_dev_addr;
 848                 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
 849                 break;
 850         default:
 851                 debug("%s: Unknown compat id %d\n", __func__, compat);
 852                 return -1;
 853         }
 854
 855         if (error == -1) {
 856                 debug("fail to get wm8994 codec node properties\n");
 857                 return -1;
 858         }
 859
 860         return 0;
 861 }
 862
 863 static int _wm8994_init(struct wm8994_priv *priv,
 864                         enum en_audio_interface aif_id, int sampling_rate,
 865                         int mclk_freq, int bits_per_sample,
 866                         unsigned int channels)
 867 {
 868         int ret;
 869
 870         ret = wm8994_setup_interface(priv, aif_id);
 871         if (ret < 0) {
 872                 debug("%s: wm8994 codec chip init failed\n", __func__);
 873                 return ret;
 874         }
 875
 876         ret =  wm8994_set_sysclk(priv, aif_id, WM8994_SYSCLK_MCLK1, mclk_freq);
 877         if (ret < 0) {
 878                 debug("%s: wm8994 codec set sys clock failed\n", __func__);
 879                 return ret;
 880         }
 881
 882         ret = wm8994_hw_params(priv, aif_id, sampling_rate, bits_per_sample,
 883                                channels);
 884
 885         if (ret == 0) {
 886                 ret = wm8994_set_fmt(priv, aif_id, SND_SOC_DAIFMT_I2S |
 887                                      SND_SOC_DAIFMT_NB_NF |
 888                                      SND_SOC_DAIFMT_CBS_CFS);
 889         }
 890
 891         return ret;
 892 }
 893
 894 /* WM8994 Device Initialisation */
 895 int wm8994_init(const void *blob, enum en_audio_interface aif_id,
 896                 int sampling_rate, int mclk_freq, int bits_per_sample,
 897                 unsigned int channels)
 898 {
 899         struct sound_codec_info pcodec_info;
 900         struct wm8994_priv wm8994_info;
 901         int ret;
 902
 903         /* Get the codec Values */
 904         if (get_codec_values(&pcodec_info, blob) < 0) {
 905                 debug("FDT Codec values failed\n");
 906                 return -1;
 907         }
 908
 909         /* shift the device address by 1 for 7 bit addressing */
 910         wm8994_info.i2c_addr = pcodec_info.i2c_dev_addr;
 911         i2c_set_bus_num(pcodec_info.i2c_bus);
 912         ret = wm8994_device_init(&wm8994_info);
 913         if (ret < 0) {
 914                 debug("%s: wm8994 codec chip init failed\n", __func__);
 915                 return ret;
 916         }
 917
 918         return _wm8994_init(&wm8994_info, aif_id, sampling_rate, mclk_freq,
 919                             bits_per_sample, channels);
 920 }