drivers/sound/max98095.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * max98095.h -- MAX98095 ALSA SoC Audio driver
   4  *
   5  * Copyright 2011 Maxim Integrated Products
   6  */
   7
   8 #ifndef _MAX98095_H
   9 #define _MAX98095_H
  10
  11 #include "maxim_codec.h"
  12
  13 /*  Available audio interface ports in wm8994 codec */
  14 enum en_max_audio_interface {
  15         AIF1,
  16         AIF2,
  17 };
  18
  19 /*
  20  * MAX98095 Registers Definition
  21  */
  22
  23 #define M98095_000_HOST_DATA            0x00
  24 #define M98095_001_HOST_INT_STS         0x01
  25 #define M98095_002_HOST_RSP_STS         0x02
  26 #define M98095_003_HOST_CMD_STS         0x03
  27 #define M98095_004_CODEC_STS            0x04
  28 #define M98095_005_DAI1_ALC_STS         0x05
  29 #define M98095_006_DAI2_ALC_STS         0x06
  30 #define M98095_007_JACK_AUTO_STS        0x07
  31 #define M98095_008_JACK_MANUAL_STS      0x08
  32 #define M98095_009_JACK_VBAT_STS        0x09
  33 #define M98095_00A_ACC_ADC_STS          0x0A
  34 #define M98095_00B_MIC_NG_AGC_STS       0x0B
  35 #define M98095_00C_SPK_L_VOLT_STS       0x0C
  36 #define M98095_00D_SPK_R_VOLT_STS       0x0D
  37 #define M98095_00E_TEMP_SENSOR_STS      0x0E
  38 #define M98095_00F_HOST_CFG             0x0F
  39 #define M98095_010_HOST_INT_CFG         0x10
  40 #define M98095_011_HOST_INT_EN          0x11
  41 #define M98095_012_CODEC_INT_EN         0x12
  42 #define M98095_013_JACK_INT_EN          0x13
  43 #define M98095_014_JACK_INT_EN          0x14
  44 #define M98095_015_DEC                  0x15
  45 #define M98095_016_RESERVED             0x16
  46 #define M98095_017_RESERVED             0x17
  47 #define M98095_018_KEYCODE3             0x18
  48 #define M98095_019_KEYCODE2             0x19
  49 #define M98095_01A_KEYCODE1             0x1A
  50 #define M98095_01B_KEYCODE0             0x1B
  51 #define M98095_01C_OEMCODE1             0x1C
  52 #define M98095_01D_OEMCODE0             0x1D
  53 #define M98095_01E_XCFG1                0x1E
  54 #define M98095_01F_XCFG2                0x1F
  55 #define M98095_020_XCFG3                0x20
  56 #define M98095_021_XCFG4                0x21
  57 #define M98095_022_XCFG5                0x22
  58 #define M98095_023_XCFG6                0x23
  59 #define M98095_024_XGPIO                0x24
  60 #define M98095_025_XCLKCFG              0x25
  61 #define M98095_026_SYS_CLK              0x26
  62 #define M98095_027_DAI1_CLKMODE         0x27
  63 #define M98095_028_DAI1_CLKCFG_HI       0x28
  64 #define M98095_029_DAI1_CLKCFG_LO       0x29
  65 #define M98095_02A_DAI1_FORMAT          0x2A
  66 #define M98095_02B_DAI1_CLOCK           0x2B
  67 #define M98095_02C_DAI1_IOCFG           0x2C
  68 #define M98095_02D_DAI1_TDM             0x2D
  69 #define M98095_02E_DAI1_FILTERS         0x2E
  70 #define M98095_02F_DAI1_LVL1            0x2F
  71 #define M98095_030_DAI1_LVL2            0x30
  72 #define M98095_031_DAI2_CLKMODE         0x31
  73 #define M98095_032_DAI2_CLKCFG_HI       0x32
  74 #define M98095_033_DAI2_CLKCFG_LO       0x33
  75 #define M98095_034_DAI2_FORMAT          0x34
  76 #define M98095_035_DAI2_CLOCK           0x35
  77 #define M98095_036_DAI2_IOCFG           0x36
  78 #define M98095_037_DAI2_TDM             0x37
  79 #define M98095_038_DAI2_FILTERS         0x38
  80 #define M98095_039_DAI2_LVL1            0x39
  81 #define M98095_03A_DAI2_LVL2            0x3A
  82 #define M98095_03B_DAI3_CLKMODE         0x3B
  83 #define M98095_03C_DAI3_CLKCFG_HI       0x3C
  84 #define M98095_03D_DAI3_CLKCFG_LO       0x3D
  85 #define M98095_03E_DAI3_FORMAT          0x3E
  86 #define M98095_03F_DAI3_CLOCK           0x3F
  87 #define M98095_040_DAI3_IOCFG           0x40
  88 #define M98095_041_DAI3_TDM             0x41
  89 #define M98095_042_DAI3_FILTERS         0x42
  90 #define M98095_043_DAI3_LVL1            0x43
  91 #define M98095_044_DAI3_LVL2            0x44
  92 #define M98095_045_CFG_DSP              0x45
  93 #define M98095_046_DAC_CTRL1            0x46
  94 #define M98095_047_DAC_CTRL2            0x47
  95 #define M98095_048_MIX_DAC_LR           0x48
  96 #define M98095_049_MIX_DAC_M            0x49
  97 #define M98095_04A_MIX_ADC_LEFT         0x4A
  98 #define M98095_04B_MIX_ADC_RIGHT        0x4B
  99 #define M98095_04C_MIX_HP_LEFT          0x4C
 100 #define M98095_04D_MIX_HP_RIGHT         0x4D
 101 #define M98095_04E_CFG_HP               0x4E
 102 #define M98095_04F_MIX_RCV              0x4F
 103 #define M98095_050_MIX_SPK_LEFT         0x50
 104 #define M98095_051_MIX_SPK_RIGHT        0x51
 105 #define M98095_052_MIX_SPK_CFG          0x52
 106 #define M98095_053_MIX_LINEOUT1         0x53
 107 #define M98095_054_MIX_LINEOUT2         0x54
 108 #define M98095_055_MIX_LINEOUT_CFG      0x55
 109 #define M98095_056_LVL_SIDETONE_DAI12   0x56
 110 #define M98095_057_LVL_SIDETONE_DAI3    0x57
 111 #define M98095_058_LVL_DAI1_PLAY        0x58
 112 #define M98095_059_LVL_DAI1_EQ          0x59
 113 #define M98095_05A_LVL_DAI2_PLAY        0x5A
 114 #define M98095_05B_LVL_DAI2_EQ          0x5B
 115 #define M98095_05C_LVL_DAI3_PLAY        0x5C
 116 #define M98095_05D_LVL_ADC_L            0x5D
 117 #define M98095_05E_LVL_ADC_R            0x5E
 118 #define M98095_05F_LVL_MIC1             0x5F
 119 #define M98095_060_LVL_MIC2             0x60
 120 #define M98095_061_LVL_LINEIN           0x61
 121 #define M98095_062_LVL_LINEOUT1         0x62
 122 #define M98095_063_LVL_LINEOUT2         0x63
 123 #define M98095_064_LVL_HP_L             0x64
 124 #define M98095_065_LVL_HP_R             0x65
 125 #define M98095_066_LVL_RCV              0x66
 126 #define M98095_067_LVL_SPK_L            0x67
 127 #define M98095_068_LVL_SPK_R            0x68
 128 #define M98095_069_MICAGC_CFG           0x69
 129 #define M98095_06A_MICAGC_THRESH        0x6A
 130 #define M98095_06B_SPK_NOISEGATE        0x6B
 131 #define M98095_06C_DAI1_ALC1_TIME       0x6C
 132 #define M98095_06D_DAI1_ALC1_COMP       0x6D
 133 #define M98095_06E_DAI1_ALC1_EXPN       0x6E
 134 #define M98095_06F_DAI1_ALC1_GAIN       0x6F
 135 #define M98095_070_DAI1_ALC2_TIME       0x70
 136 #define M98095_071_DAI1_ALC2_COMP       0x71
 137 #define M98095_072_DAI1_ALC2_EXPN       0x72
 138 #define M98095_073_DAI1_ALC2_GAIN       0x73
 139 #define M98095_074_DAI1_ALC3_TIME       0x74
 140 #define M98095_075_DAI1_ALC3_COMP       0x75
 141 #define M98095_076_DAI1_ALC3_EXPN       0x76
 142 #define M98095_077_DAI1_ALC3_GAIN       0x77
 143 #define M98095_078_DAI2_ALC1_TIME       0x78
 144 #define M98095_079_DAI2_ALC1_COMP       0x79
 145 #define M98095_07A_DAI2_ALC1_EXPN       0x7A
 146 #define M98095_07B_DAI2_ALC1_GAIN       0x7B
 147 #define M98095_07C_DAI2_ALC2_TIME       0x7C
 148 #define M98095_07D_DAI2_ALC2_COMP       0x7D
 149 #define M98095_07E_DAI2_ALC2_EXPN       0x7E
 150 #define M98095_07F_DAI2_ALC2_GAIN       0x7F
 151 #define M98095_080_DAI2_ALC3_TIME       0x80
 152 #define M98095_081_DAI2_ALC3_COMP       0x81
 153 #define M98095_082_DAI2_ALC3_EXPN       0x82
 154 #define M98095_083_DAI2_ALC3_GAIN       0x83
 155 #define M98095_084_HP_NOISE_GATE        0x84
 156 #define M98095_085_AUX_ADC              0x85
 157 #define M98095_086_CFG_LINE             0x86
 158 #define M98095_087_CFG_MIC              0x87
 159 #define M98095_088_CFG_LEVEL            0x88
 160 #define M98095_089_JACK_DET_AUTO        0x89
 161 #define M98095_08A_JACK_DET_MANUAL      0x8A
 162 #define M98095_08B_JACK_KEYSCAN_DBC     0x8B
 163 #define M98095_08C_JACK_KEYSCAN_DLY     0x8C
 164 #define M98095_08D_JACK_KEY_THRESH      0x8D
 165 #define M98095_08E_JACK_DC_SLEW         0x8E
 166 #define M98095_08F_JACK_TEST_CFG        0x8F
 167 #define M98095_090_PWR_EN_IN            0x90
 168 #define M98095_091_PWR_EN_OUT           0x91
 169 #define M98095_092_PWR_EN_OUT           0x92
 170 #define M98095_093_BIAS_CTRL            0x93
 171 #define M98095_094_PWR_DAC_21           0x94
 172 #define M98095_095_PWR_DAC_03           0x95
 173 #define M98095_096_PWR_DAC_CK           0x96
 174 #define M98095_097_PWR_SYS              0x97
 175
 176 #define M98095_0FF_REV_ID               0xFF
 177
 178 #define M98095_REG_CNT                  (0xFF+1)
 179 #define M98095_REG_MAX_CACHED           0X97
 180
 181 /* MAX98095 Registers Bit Fields */
 182
 183 /* M98095_00F_HOST_CFG */
 184 #define M98095_SEG                      (1<<0)
 185 #define M98095_XTEN                     (1<<1)
 186 #define M98095_MDLLEN                   (1<<2)
 187
 188 /* M98095_027_DAI1_CLKMODE, M98095_031_DAI2_CLKMODE, M98095_03B_DAI3_CLKMODE */
 189 #define M98095_CLKMODE_MASK             0xFF
 190
 191 /* M98095_02A_DAI1_FORMAT, M98095_034_DAI2_FORMAT, M98095_03E_DAI3_FORMAT */
 192 #define M98095_DAI_MAS                  (1<<7)
 193 #define M98095_DAI_WCI                  (1<<6)
 194 #define M98095_DAI_BCI                  (1<<5)
 195 #define M98095_DAI_DLY                  (1<<4)
 196 #define M98095_DAI_TDM                  (1<<2)
 197 #define M98095_DAI_FSW                  (1<<1)
 198 #define M98095_DAI_WS                   (1<<0)
 199
 200 /* M98095_02B_DAI1_CLOCK, M98095_035_DAI2_CLOCK, M98095_03F_DAI3_CLOCK */
 201 #define M98095_DAI_BSEL64               (1<<0)
 202 #define M98095_DAI_DOSR_DIV2            (0<<5)
 203 #define M98095_DAI_DOSR_DIV4            (1<<5)
 204
 205 /* M98095_02C_DAI1_IOCFG, M98095_036_DAI2_IOCFG, M98095_040_DAI3_IOCFG */
 206 #define M98095_S1NORMAL                 (1<<6)
 207 #define M98095_S2NORMAL                 (2<<6)
 208 #define M98095_S3NORMAL                 (3<<6)
 209 #define M98095_SDATA                    (3<<0)
 210
 211 /* M98095_02E_DAI1_FILTERS, M98095_038_DAI2_FILTERS, M98095_042_DAI3_FILTERS */
 212 #define M98095_DAI_DHF                  (1<<3)
 213
 214 /* M98095_045_DSP_CFG */
 215 #define M98095_DSPNORMAL                (5<<4)
 216
 217 /* M98095_048_MIX_DAC_LR */
 218 #define M98095_DAI1L_TO_DACR            (1<<7)
 219 #define M98095_DAI1R_TO_DACR            (1<<6)
 220 #define M98095_DAI2M_TO_DACR            (1<<5)
 221 #define M98095_DAI1L_TO_DACL            (1<<3)
 222 #define M98095_DAI1R_TO_DACL            (1<<2)
 223 #define M98095_DAI2M_TO_DACL            (1<<1)
 224 #define M98095_DAI3M_TO_DACL            (1<<0)
 225
 226 /* M98095_049_MIX_DAC_M */
 227 #define M98095_DAI1L_TO_DACM            (1<<3)
 228 #define M98095_DAI1R_TO_DACM            (1<<2)
 229 #define M98095_DAI2M_TO_DACM            (1<<1)
 230 #define M98095_DAI3M_TO_DACM            (1<<0)
 231
 232 /* M98095_04E_MIX_HP_CFG */
 233 #define M98095_HPNORMAL                 (3<<4)
 234
 235 /* M98095_05F_LVL_MIC1, M98095_060_LVL_MIC2 */
 236 #define M98095_MICPRE_MASK              (3<<5)
 237 #define M98095_MICPRE_SHIFT             5
 238
 239 /* M98095_064_LVL_HP_L, M98095_065_LVL_HP_R */
 240 #define M98095_HP_MUTE                  (1<<7)
 241
 242 /* M98095_066_LVL_RCV */
 243 #define M98095_REC_MUTE                 (1<<7)
 244
 245 /* M98095_067_LVL_SPK_L, M98095_068_LVL_SPK_R */
 246 #define M98095_SP_MUTE                  (1<<7)
 247
 248 /* M98095_087_CFG_MIC */
 249 #define M98095_MICSEL_MASK              (3<<0)
 250 #define M98095_DIGMIC_L                 (1<<2)
 251 #define M98095_DIGMIC_R                 (1<<3)
 252 #define M98095_DIGMIC2L                 (1<<4)
 253 #define M98095_DIGMIC2R                 (1<<5)
 254
 255 /* M98095_088_CFG_LEVEL */
 256 #define M98095_VSEN                     (1<<6)
 257 #define M98095_ZDEN                     (1<<5)
 258 #define M98095_BQ2EN                    (1<<3)
 259 #define M98095_BQ1EN                    (1<<2)
 260 #define M98095_EQ2EN                    (1<<1)
 261 #define M98095_EQ1EN                    (1<<0)
 262
 263 /* M98095_090_PWR_EN_IN */
 264 #define M98095_INEN                     (1<<7)
 265 #define M98095_MB2EN                    (1<<3)
 266 #define M98095_MB1EN                    (1<<2)
 267 #define M98095_MBEN                     (3<<2)
 268 #define M98095_ADREN                    (1<<1)
 269 #define M98095_ADLEN                    (1<<0)
 270
 271 /* M98095_091_PWR_EN_OUT */
 272 #define M98095_HPLEN                    (1<<7)
 273 #define M98095_HPREN                    (1<<6)
 274 #define M98095_SPLEN                    (1<<5)
 275 #define M98095_SPREN                    (1<<4)
 276 #define M98095_RECEN                    (1<<3)
 277 #define M98095_DALEN                    (1<<1)
 278 #define M98095_DAREN                    (1<<0)
 279
 280 /* M98095_092_PWR_EN_OUT */
 281 #define M98095_SPK_FIXEDSPECTRUM        (0<<4)
 282 #define M98095_SPK_SPREADSPECTRUM       (1<<4)
 283
 284 /* M98095_097_PWR_SYS */
 285 #define M98095_SHDNRUN                  (1<<7)
 286 #define M98095_PERFMODE                 (1<<3)
 287 #define M98095_HPPLYBACK                (1<<2)
 288 #define M98095_PWRSV8K                  (1<<1)
 289 #define M98095_PWRSV                    (1<<0)
 290
 291 #define M98095_COEFS_PER_BAND           5
 292
 293 /* Equalizer filter coefficients */
 294 #define M98095_110_DAI1_EQ_BASE         0x10
 295 #define M98095_142_DAI2_EQ_BASE         0x42
 296
 297 /* Biquad filter coefficients */
 298 #define M98095_174_DAI1_BQ_BASE         0x74
 299 #define M98095_17E_DAI2_BQ_BASE         0x7E
 300
 301 /* function prototype */
 302
 303 /*
 304  * intialise max98095 sound codec device for the given configuration
 305  *
 306  * @param blob                  FDT node for codec values
 307  * @param sampling_rate         Sampling rate (Hz)
 308  * @param mclk_freq             MCLK Frequency (Hz)
 309  * @param bits_per_sample       bits per Sample (must be 16 or 24)
 310  *
 311  * @returns -1 for error and 0 Success.
 312  */
 313 int max98095_init(const void *blob, enum en_max_audio_interface aif_id,
 314                   int sampling_rate, int mclk_freq, int bits_per_sample);
 315
 316 #endif