1 // SPDX-License-Identifier: GPL-2.0+
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011 Maxim Integrated Products
9 #include <audio_codec.h>
17 #include "maxim_codec.h"
21 * Sets hw params for max98090
23 * @priv: max98090 information pointer
24 * @rate: Sampling rate
25 * @bits_per_sample: Bits per sample
27 * @return -EIO for error, 0 for success.
29 int max98090_hw_params(struct maxim_priv *priv, unsigned int rate,
30 unsigned int bits_per_sample)
35 switch (bits_per_sample) {
37 maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
38 error = maxim_bic_or(priv, M98090_REG_INTERFACE_FORMAT,
40 maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
43 debug("%s: Illegal bits per sample %d.\n",
44 __func__, bits_per_sample);
48 /* Update filter mode */
50 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
53 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
54 M98090_MODE_MASK, M98090_MODE_MASK);
56 /* Update sample rate mode */
58 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
61 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
62 M98090_DHF_MASK, M98090_DHF_MASK);
65 debug("%s: Error setting hardware params.\n", __func__);
74 * Configures Audio interface system clock for the given frequency
76 * @priv: max98090 information
77 * @freq: Sampling frequency in Hz
79 * @return -EIO for error, 0 for success.
81 int max98090_set_sysclk(struct maxim_priv *priv, unsigned int freq)
85 /* Requested clock frequency is already setup */
86 if (freq == priv->sysclk)
89 /* Setup clocks for slave mode, and using the PLL
90 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
91 * 0x02 (when master clk is 20MHz to 40MHz)..
92 * 0x03 (when master clk is 40MHz to 60MHz)..
94 if (freq >= 10000000 && freq < 20000000) {
95 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
97 } else if (freq >= 20000000 && freq < 40000000) {
98 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
100 } else if (freq >= 40000000 && freq < 60000000) {
101 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
104 debug("%s: Invalid master clock frequency\n", __func__);
108 debug("%s: Clock at %uHz\n", __func__, freq);
119 * Sets Max98090 I2S format
121 * @priv: max98090 information
122 * @fmt: i2S format - supports a subset of the options defined in i2s.h.
124 * @return -EIO for error, 0 for success.
126 int max98090_set_fmt(struct maxim_priv *priv, int fmt)
131 if (fmt == priv->fmt)
136 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
137 case SND_SOC_DAIFMT_CBS_CFS:
138 /* Set to slave mode PLL - MAS mode off */
139 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB,
141 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB,
143 error |= maxim_bic_or(priv, M98090_REG_CLOCK_MODE,
144 M98090_USE_M1_MASK, 0);
146 case SND_SOC_DAIFMT_CBM_CFM:
147 /* Set to master mode */
148 debug("Master mode not supported\n");
150 case SND_SOC_DAIFMT_CBS_CFM:
151 case SND_SOC_DAIFMT_CBM_CFS:
153 debug("%s: Clock mode unsupported\n", __func__);
157 error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, regval);
160 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
161 case SND_SOC_DAIFMT_I2S:
162 regval |= M98090_DLY_MASK;
164 case SND_SOC_DAIFMT_LEFT_J:
166 case SND_SOC_DAIFMT_RIGHT_J:
167 regval |= M98090_RJ_MASK;
169 case SND_SOC_DAIFMT_DSP_A:
170 /* Not supported mode */
172 debug("%s: Unrecognized format.\n", __func__);
176 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
177 case SND_SOC_DAIFMT_NB_NF:
179 case SND_SOC_DAIFMT_NB_IF:
180 regval |= M98090_WCI_MASK;
182 case SND_SOC_DAIFMT_IB_NF:
183 regval |= M98090_BCI_MASK;
185 case SND_SOC_DAIFMT_IB_IF:
186 regval |= M98090_BCI_MASK | M98090_WCI_MASK;
189 debug("%s: Unrecognized inversion settings.\n", __func__);
193 error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, regval);
196 debug("%s: Error setting i2s format.\n", __func__);
204 * resets the audio codec
206 * @priv: max98090 information
207 * @return -EIO for error, 0 for success.
209 static int max98090_reset(struct maxim_priv *priv)
214 * Gracefully reset the DSP core and the codec hardware in a proper
217 ret = maxim_i2c_write(priv, M98090_REG_SOFTWARE_RESET,
218 M98090_SWRESET_MASK);
220 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
229 * Initialise max98090 codec device
231 * @priv: max98090 information
233 * @return -EIO for error, 0 for success.
235 int max98090_device_init(struct maxim_priv *priv)
240 /* reset the codec, the DSP core, and disable all interrupts */
241 error = max98090_reset(priv);
247 /* initialize private data */
252 error = maxim_i2c_read(priv, M98090_REG_REVISION_ID, &id);
254 debug("%s: Failure reading hardware revision: %d\n",
258 debug("%s: Hardware revision: %d\n", __func__, id);
263 static int max98090_setup_interface(struct maxim_priv *priv)
268 /* Reading interrupt status to clear them */
269 error = maxim_i2c_read(priv, M98090_REG_DEVICE_STATUS, &id);
271 error |= maxim_i2c_write(priv, M98090_REG_DAC_CONTROL,
273 error |= maxim_i2c_write(priv, M98090_REG_BIAS_CONTROL,
274 M98090_VCM_MODE_MASK);
276 error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_MIXER, 0x1);
277 error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_MIXER, 0x2);
279 error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_VOLUME, 0x25);
280 error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_VOLUME, 0x25);
282 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB, 0x0);
283 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB, 0x0);
284 error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, 0x0);
285 error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, 0x0);
286 error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
288 error |= maxim_i2c_write(priv, M98090_REG_DEVICE_SHUTDOWN,
290 error |= maxim_i2c_write(priv, M98090_REG_OUTPUT_ENABLE,
291 M98090_HPREN_MASK | M98090_HPLEN_MASK |
292 M98090_SPREN_MASK | M98090_SPLEN_MASK |
293 M98090_DAREN_MASK | M98090_DALEN_MASK);
294 error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
295 M98090_SDOEN_MASK | M98090_SDIEN_MASK);
303 static int max98090_do_init(struct maxim_priv *priv, int sampling_rate,
304 int mclk_freq, int bits_per_sample)
308 ret = max98090_setup_interface(priv);
310 debug("%s: max98090 setup interface failed\n", __func__);
314 ret = max98090_set_sysclk(priv, mclk_freq);
316 debug("%s: max98090 codec set sys clock failed\n", __func__);
320 ret = max98090_hw_params(priv, sampling_rate, bits_per_sample);
323 ret = max98090_set_fmt(priv, SND_SOC_DAIFMT_I2S |
324 SND_SOC_DAIFMT_NB_NF |
325 SND_SOC_DAIFMT_CBS_CFS);
331 static int max98090_set_params(struct udevice *dev, int interface, int rate,
332 int mclk_freq, int bits_per_sample,
335 struct maxim_priv *priv = dev_get_priv(dev);
337 return max98090_do_init(priv, rate, mclk_freq, bits_per_sample);
340 static int max98090_probe(struct udevice *dev)
342 struct maxim_priv *priv = dev_get_priv(dev);
346 ret = max98090_device_init(priv);
348 debug("%s: max98090 codec chip init failed\n", __func__);
355 static const struct audio_codec_ops max98090_ops = {
356 .set_params = max98090_set_params,
359 static const struct udevice_id max98090_ids[] = {
360 { .compatible = "maxim,max98090" },
364 U_BOOT_DRIVER(max98090) = {
366 .id = UCLASS_AUDIO_CODEC,
367 .of_match = max98090_ids,
368 .probe = max98090_probe,
369 .ops = &max98090_ops,
370 .priv_auto_alloc_size = sizeof(struct maxim_priv),