1 // SPDX-License-Identifier: GPL-2.0+
3 * max98088.c -- MAX98088 ALSA SoC Audio driver
5 * Copyright 2010 Maxim Integrated Products
7 * Modified for U-Boot by Chih-Chung Chang (chihchung@chromium.org),
8 * following the changes made in max98095.c
12 #include <audio_codec.h>
20 #include "maxim_codec.h"
23 /* codec mclk clock divider coefficients. Index 0 is reserved. */
24 static const int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000,
25 44100, 48000, 88200, 96000};
28 * codec mclk clock divider coefficients based on sampling rate
30 * @param rate sampling rate
31 * @param value address of indexvalue to be stored
33 * @return 0 for success or negative error code.
35 static int rate_value(int rate, u8 *value)
39 for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
40 if (rate_table[i] >= rate) {
51 * Sets hw params for max98088
53 * @priv: max98088 information pointer
54 * @rate: Sampling rate
55 * @bits_per_sample: Bits per sample
57 * @return -EIO for error, 0 for success.
59 int max98088_hw_params(struct maxim_priv *priv, unsigned int rate,
60 unsigned int bits_per_sample)
65 switch (bits_per_sample) {
67 error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
71 error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
72 M98088_DAI_WS, M98088_DAI_WS);
75 debug("%s: Illegal bits per sample %d.\n",
76 __func__, bits_per_sample);
80 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN, 0);
82 if (rate_value(rate, ®val)) {
83 debug("%s: Failed to set sample rate to %d.\n",
88 error |= maxim_bic_or(priv, M98088_REG_DAI1_CLKMODE,
89 M98088_CLKMODE_MASK, regval << 4);
92 /* Update sample rate mode */
94 error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
97 error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
98 M98088_DAI_DHF, M98088_DAI_DHF);
100 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN,
104 debug("%s: Error setting hardware params.\n", __func__);
113 * Configures Audio interface system clock for the given frequency
115 * @priv: max98088 information
116 * @freq: Sampling frequency in Hz
118 * @return -EIO for error, 0 for success.
120 int max98088_set_sysclk(struct maxim_priv *priv, unsigned int freq)
125 /* Requested clock frequency is already setup */
126 if (freq == priv->sysclk)
130 * Setup clocks for slave mode, and using the PLL
131 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
132 * 0x02 (when master clk is 20MHz to 30MHz)..
134 if (freq >= 10000000 && freq < 20000000) {
135 error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x10);
136 } else if ((freq >= 20000000) && (freq < 30000000)) {
137 error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x20);
139 debug("%s: Invalid master clock frequency\n", __func__);
143 error |= maxim_i2c_read(priv, M98088_REG_PWR_SYS, &pwr);
144 if (pwr & M98088_SHDNRUN) {
145 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
147 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
148 M98088_SHDNRUN, M98088_SHDNRUN);
151 debug("%s: Clock at %uHz\n", __func__, freq);
161 * Sets Max98090 I2S format
163 * @priv: max98088 information
164 * @fmt: i2S format - supports a subset of the options defined in i2s.h.
166 * @return -EIO for error, 0 for success.
168 int max98088_set_fmt(struct maxim_priv *priv, int fmt)
174 if (fmt == priv->fmt)
179 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
180 case SND_SOC_DAIFMT_CBS_CFS:
182 error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_HI,
184 error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_LO,
187 case SND_SOC_DAIFMT_CBM_CFM:
188 /* Set to master mode */
189 reg14val |= M98088_DAI_MAS;
191 case SND_SOC_DAIFMT_CBS_CFM:
192 case SND_SOC_DAIFMT_CBM_CFS:
194 debug("%s: Clock mode unsupported\n", __func__);
198 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
199 case SND_SOC_DAIFMT_I2S:
200 reg14val |= M98088_DAI_DLY;
202 case SND_SOC_DAIFMT_LEFT_J:
205 debug("%s: Unrecognized format.\n", __func__);
209 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
210 case SND_SOC_DAIFMT_NB_NF:
212 case SND_SOC_DAIFMT_NB_IF:
213 reg14val |= M98088_DAI_WCI;
215 case SND_SOC_DAIFMT_IB_NF:
216 reg14val |= M98088_DAI_BCI;
218 case SND_SOC_DAIFMT_IB_IF:
219 reg14val |= M98088_DAI_BCI | M98088_DAI_WCI;
222 debug("%s: Unrecognized inversion settings.\n", __func__);
226 error |= maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
227 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
228 M98088_DAI_WCI, reg14val);
229 reg15val = M98088_DAI_BSEL64;
230 error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLOCK, reg15val);
233 debug("%s: Error setting i2s format.\n", __func__);
241 * max98088_reset() - reset the audio codec
243 * @priv: max98088 information
244 * @return -EIO for error, 0 for success.
246 static int max98088_reset(struct maxim_priv *priv)
252 * Reset to hardware default for registers, as there is not a soft
253 * reset hardware control register.
255 for (i = M98088_REG_IRQ_ENABLE; i <= M98088_REG_PWR_SYS; i++) {
257 case M98088_REG_BIAS_CNTL:
260 case M98088_REG_DAC_BIAS2:
266 ret = maxim_i2c_write(priv, i, val);
268 debug("%s: Failed to reset: %d\n", __func__, ret);
277 * max98088_device_init() - Initialise max98088 codec device
279 * @priv: max98088 information
281 * @return -EIO for error, 0 for success.
283 static int max98088_device_init(struct maxim_priv *priv)
288 /* reset the codec, the DSP core, and disable all interrupts */
289 error = max98088_reset(priv);
295 /* initialize private data */
300 error = maxim_i2c_read(priv, M98088_REG_REV_ID, &id);
302 debug("%s: Failure reading hardware revision: %d\n",
306 debug("%s: Hardware revision: %d\n", __func__, id);
311 static int max98088_setup_interface(struct maxim_priv *priv)
315 /* Reading interrupt status to clear them */
316 error = maxim_i2c_write(priv, M98088_REG_PWR_SYS, M98088_PWRSV);
317 error |= maxim_i2c_write(priv, M98088_REG_IRQ_ENABLE, 0x00);
320 * initialize registers to hardware default configuring audio
323 error |= maxim_i2c_write(priv, M98088_REG_MIX_DAC,
324 M98088_DAI1L_TO_DACL | M98088_DAI1R_TO_DACR);
325 error |= maxim_i2c_write(priv, M98088_REG_BIAS_CNTL, 0xF0);
326 error |= maxim_i2c_write(priv, M98088_REG_DAC_BIAS2, 0x0F);
327 error |= maxim_i2c_write(priv, M98088_REG_DAI1_IOCFG,
328 M98088_S2NORMAL | M98088_SDATA);
331 * route DACL and DACR output to headphone and speakers
332 * Ordering: DACL, DACR, DACL, DACR
334 error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_LEFT, 1);
335 error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_RIGHT, 1);
336 error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_LEFT, 1);
337 error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_RIGHT, 1);
339 /* set volume: -12db */
340 error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_L, 0x0f);
341 error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_R, 0x0f);
343 /* set volume: -22db */
344 error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_L, 0x0d);
345 error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_R, 0x0d);
348 error |= maxim_i2c_write(priv, M98088_REG_PWR_EN_OUT,
349 M98088_HPLEN | M98088_HPREN | M98088_SPLEN |
350 M98088_SPREN | M98088_DALEN | M98088_DAREN);
357 static int max98088_do_init(struct maxim_priv *priv, int sampling_rate,
358 int mclk_freq, int bits_per_sample)
362 ret = max98088_setup_interface(priv);
364 debug("%s: max98088 setup interface failed\n", __func__);
368 ret = max98088_set_sysclk(priv, mclk_freq);
370 debug("%s: max98088 codec set sys clock failed\n", __func__);
374 ret = max98088_hw_params(priv, sampling_rate, bits_per_sample);
377 ret = max98088_set_fmt(priv, SND_SOC_DAIFMT_I2S |
378 SND_SOC_DAIFMT_NB_NF |
379 SND_SOC_DAIFMT_CBS_CFS);
385 static int max98088_set_params(struct udevice *dev, int interface, int rate,
386 int mclk_freq, int bits_per_sample,
389 struct maxim_priv *priv = dev_get_priv(dev);
391 return max98088_do_init(priv, rate, mclk_freq, bits_per_sample);
394 static int max98088_probe(struct udevice *dev)
396 struct maxim_priv *priv = dev_get_priv(dev);
400 ret = max98088_device_init(priv);
402 debug("%s: max98088 codec chip init failed\n", __func__);
409 static const struct audio_codec_ops max98088_ops = {
410 .set_params = max98088_set_params,
413 static const struct udevice_id max98088_ids[] = {
414 { .compatible = "maxim,max98088" },
418 U_BOOT_DRIVER(max98088) = {
420 .id = UCLASS_AUDIO_CODEC,
421 .of_match = max98088_ids,
422 .probe = max98088_probe,
423 .ops = &max98088_ops,
424 .priv_auto_alloc_size = sizeof(struct maxim_priv),