1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
5 #include <asm/arch-rockchip/hardware.h>
9 #include <linux/iopoll.h>
10 #include <linux/string.h>
13 #define RK_HW_RNG_MAX 32
15 #define _SBF(s, v) ((v) << (s))
17 /* start of CRYPTO V1 register define */
18 #define CRYPTO_V1_CTRL 0x0008
19 #define CRYPTO_V1_RNG_START BIT(8)
20 #define CRYPTO_V1_RNG_FLUSH BIT(9)
22 #define CRYPTO_V1_TRNG_CTRL 0x0200
23 #define CRYPTO_V1_OSC_ENABLE BIT(16)
24 #define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x)
26 #define CRYPTO_V1_TRNG_DOUT_0 0x0204
27 /* end of CRYPTO V1 register define */
29 /* start of CRYPTO V2 register define */
30 #define CRYPTO_V2_RNG_CTL 0x0400
31 #define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
32 #define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
33 #define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
34 #define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03)
35 #define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00)
36 #define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01)
37 #define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02)
38 #define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
39 #define CRYPTO_V2_RNG_ENABLE BIT(1)
40 #define CRYPTO_V2_RNG_START BIT(0)
41 #define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
42 #define CRYPTO_V2_RNG_DOUT_0 0x0410
43 /* end of CRYPTO V2 register define */
45 #define RK_RNG_TIME_OUT 50000 /* max 50ms */
47 struct rk_rng_soc_data {
48 int (*rk_rng_read)(struct udevice *dev, void *data, size_t len);
51 struct rk_rng_platdata {
53 struct rk_rng_soc_data *soc_data;
56 static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size)
58 u32 count = RK_HW_RNG_MAX / sizeof(u32);
61 if (size > RK_HW_RNG_MAX)
64 while (size && count) {
66 tmp_len = min(size, sizeof(u32));
67 memcpy(buf, ®, tmp_len);
77 static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len)
79 struct rk_rng_platdata *pdata = dev_get_priv(dev);
83 if (len > RK_HW_RNG_MAX)
86 /* enable osc_ring to get entropy, sample period is set as 100 */
87 writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100),
88 pdata->base + CRYPTO_V1_TRNG_CTRL);
90 rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START,
93 retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg,
94 !(reg & CRYPTO_V1_RNG_START),
99 rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len);
103 rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START);
108 static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len)
110 struct rk_rng_platdata *pdata = dev_get_priv(dev);
114 if (len > RK_HW_RNG_MAX)
117 /* enable osc_ring to get entropy, sample period is set as 100 */
118 writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT);
120 reg |= CRYPTO_V2_RNG_256_BIT_LEN;
121 reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
122 reg |= CRYPTO_V2_RNG_ENABLE;
123 reg |= CRYPTO_V2_RNG_START;
125 rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg);
127 retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg,
128 !(reg & CRYPTO_V2_RNG_START),
133 rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len);
137 rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff);
142 static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
144 unsigned char *buf = data;
148 struct rk_rng_platdata *pdata = dev_get_priv(dev);
153 if (!pdata->soc_data || !pdata->soc_data->rk_rng_read)
156 for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) {
157 ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX);
162 if (len % RK_HW_RNG_MAX)
163 ret = pdata->soc_data->rk_rng_read(dev, buf,
164 len % RK_HW_RNG_MAX);
170 static int rockchip_rng_ofdata_to_platdata(struct udevice *dev)
172 struct rk_rng_platdata *pdata = dev_get_priv(dev);
174 memset(pdata, 0x00, sizeof(*pdata));
176 pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev);
183 static int rockchip_rng_probe(struct udevice *dev)
185 struct rk_rng_platdata *pdata = dev_get_priv(dev);
187 pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev);
192 static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
193 .rk_rng_read = rk_v1_rng_read,
196 static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
197 .rk_rng_read = rk_v2_rng_read,
200 static const struct dm_rng_ops rockchip_rng_ops = {
201 .read = rockchip_rng_read,
204 static const struct udevice_id rockchip_rng_match[] = {
206 .compatible = "rockchip,cryptov1-rng",
207 .data = (ulong)&rk_rng_v1_soc_data,
210 .compatible = "rockchip,cryptov2-rng",
211 .data = (ulong)&rk_rng_v2_soc_data,
216 U_BOOT_DRIVER(rockchip_rng) = {
217 .name = "rockchip-rng",
219 .of_match = rockchip_rng_match,
220 .ops = &rockchip_rng_ops,
221 .probe = rockchip_rng_probe,
222 .ofdata_to_platdata = rockchip_rng_ofdata_to_platdata,
223 .priv_auto_alloc_size = sizeof(struct rk_rng_platdata),