drivers/ram/stm32mp1/stm32mp1_tuning.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
   4  */
   5 #include <common.h>
   6 #include <console.h>
   7 #include <clk.h>
   8 #include <log.h>
   9 #include <ram.h>
  10 #include <rand.h>
  11 #include <reset.h>
  12 #include <asm/io.h>
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/iopoll.h>
  16
  17 #include "stm32mp1_ddr_regs.h"
  18 #include "stm32mp1_ddr.h"
  19 #include "stm32mp1_tests.h"
  20
  21 #define MAX_DQS_PHASE_IDX _144deg
  22 #define MAX_DQS_UNIT_IDX 7
  23 #define MAX_GSL_IDX 5
  24 #define MAX_GPS_IDX 3
  25
  26 /* Number of bytes used in this SW. ( min 1--> max 4). */
  27 #define NUM_BYTES 4
  28
  29 enum dqs_phase_enum {
  30         _36deg = 0,
  31         _54deg = 1,
  32         _72deg = 2,
  33         _90deg = 3,
  34         _108deg = 4,
  35         _126deg = 5,
  36         _144deg = 6
  37 };
  38
  39 /* BIST Result struct */
  40 struct BIST_result {
  41         /* Overall test result:
  42          * 0 Fail (any bit failed) ,
  43          * 1 Success (All bits success)
  44          */
  45         bool test_result;
  46         /* 1: true, all fail /  0: False, not all bits fail */
  47         bool all_bits_fail;
  48         bool bit_i_test_result[8];  /* 0 fail / 1 success */
  49 };
  50
  51 /* a struct that defines tuning parameters of a byte. */
  52 struct tuning_position {
  53         u8 phase; /* DQS phase */
  54         u8 unit; /* DQS unit delay */
  55         u32 bits_delay; /* Bits deskew in this byte */
  56 };
  57
  58 /* 36deg, 54deg, 72deg, 90deg, 108deg, 126deg, 144deg */
  59 const u8 dx_dll_phase[7] = {3, 2, 1, 0, 14, 13, 12};
  60
  61 static u8 BIST_error_max = 1;
  62 static u32 BIST_seed = 0x1234ABCD;
  63
  64 static u8 get_nb_bytes(struct stm32mp1_ddrctl *ctl)
  65 {
  66         u32 data_bus = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
  67         u8 nb_bytes = NUM_BYTES;
  68
  69         switch (data_bus) {
  70         case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
  71                 nb_bytes /= 2;
  72                 break;
  73         case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
  74                 nb_bytes /= 4;
  75                 break;
  76         default:
  77                 break;
  78         }
  79
  80         return nb_bytes;
  81 }
  82
  83 static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl)
  84 {
  85         /* Count bank address bits */
  86         u8 bits = 0;
  87         u32 reg, val;
  88
  89         reg = readl(&ctl->addrmap1);
  90         /* addrmap1.addrmap_bank_b1 */
  91         val = (reg & GENMASK(5, 0)) >> 0;
  92         if (val <= 31)
  93                 bits++;
  94         /* addrmap1.addrmap_bank_b2 */
  95         val = (reg & GENMASK(13, 8)) >> 8;
  96         if (val <= 31)
  97                 bits++;
  98         /* addrmap1.addrmap_bank_b3 */
  99         val = (reg & GENMASK(21, 16)) >> 16;
 100         if (val <= 31)
 101                 bits++;
 102
 103         return bits;
 104 }
 105
 106 static u8 get_nb_col(struct stm32mp1_ddrctl *ctl)
 107 {
 108         u8 bits;
 109         u32 reg, val;
 110
 111         /* Count column address bits, start at 2 for b0 and b1 (fixed) */
 112         bits = 2;
 113
 114         reg = readl(&ctl->addrmap2);
 115         /* addrmap2.addrmap_col_b2 */
 116         val = (reg & GENMASK(3, 0)) >> 0;
 117         if (val <= 7)
 118                 bits++;
 119         /* addrmap2.addrmap_col_b3 */
 120         val = (reg & GENMASK(11, 8)) >> 8;
 121         if (val <= 7)
 122                 bits++;
 123         /* addrmap2.addrmap_col_b4 */
 124         val = (reg & GENMASK(19, 16)) >> 16;
 125         if (val <= 7)
 126                 bits++;
 127         /* addrmap2.addrmap_col_b5 */
 128         val = (reg & GENMASK(27, 24)) >> 24;
 129         if (val <= 7)
 130                 bits++;
 131
 132         reg = readl(&ctl->addrmap3);
 133         /* addrmap3.addrmap_col_b6 */
 134         val = (reg & GENMASK(3, 0)) >> 0;
 135         if (val <= 7)
 136                 bits++;
 137         /* addrmap3.addrmap_col_b7 */
 138         val = (reg & GENMASK(11, 8)) >> 8;
 139         if (val <= 7)
 140                 bits++;
 141         /* addrmap3.addrmap_col_b8 */
 142         val = (reg & GENMASK(19, 16)) >> 16;
 143         if (val <= 7)
 144                 bits++;
 145         /* addrmap3.addrmap_col_b9 */
 146         val = (reg & GENMASK(27, 24)) >> 24;
 147         if (val <= 7)
 148                 bits++;
 149
 150         reg = readl(&ctl->addrmap4);
 151         /* addrmap4.addrmap_col_b10 */
 152         val = (reg & GENMASK(3, 0)) >> 0;
 153         if (val <= 7)
 154                 bits++;
 155         /* addrmap4.addrmap_col_b11 */
 156         val = (reg & GENMASK(11, 8)) >> 8;
 157         if (val <= 7)
 158                 bits++;
 159
 160         return bits;
 161 }
 162
 163 static u8 get_nb_row(struct stm32mp1_ddrctl *ctl)
 164 {
 165         /* Count row address bits */
 166         u8 bits = 0;
 167         u32 reg, val;
 168
 169         reg = readl(&ctl->addrmap5);
 170         /* addrmap5.addrmap_row_b0 */
 171         val = (reg & GENMASK(3, 0)) >> 0;
 172         if (val <= 11)
 173                 bits++;
 174         /* addrmap5.addrmap_row_b1 */
 175         val = (reg & GENMASK(11, 8)) >> 8;
 176         if (val <= 11)
 177                 bits++;
 178         /* addrmap5.addrmap_row_b2_10 */
 179         val = (reg & GENMASK(19, 16)) >> 16;
 180         if (val <= 11)
 181                 bits += 9;
 182         else
 183                 printf("warning: addrmap5.addrmap_row_b2_10 not supported\n");
 184         /* addrmap5.addrmap_row_b11 */
 185         val = (reg & GENMASK(27, 24)) >> 24;
 186         if (val <= 11)
 187                 bits++;
 188
 189         reg = readl(&ctl->addrmap6);
 190         /* addrmap6.addrmap_row_b12 */
 191         val = (reg & GENMASK(3, 0)) >> 0;
 192         if (val <= 7)
 193                 bits++;
 194         /* addrmap6.addrmap_row_b13 */
 195         val = (reg & GENMASK(11, 8)) >> 8;
 196         if (val <= 7)
 197                 bits++;
 198         /* addrmap6.addrmap_row_b14 */
 199         val = (reg & GENMASK(19, 16)) >> 16;
 200         if (val <= 7)
 201                 bits++;
 202         /* addrmap6.addrmap_row_b15 */
 203         val = (reg & GENMASK(27, 24)) >> 24;
 204         if (val <= 7)
 205                 bits++;
 206
 207         return bits;
 208 }
 209
 210 static void itm_soft_reset(struct stm32mp1_ddrphy *phy)
 211 {
 212         stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
 213 }
 214
 215 /* Read DQ unit delay register and provides the retrieved value for DQS
 216  * We are assuming that we have the same delay when clocking
 217  * by DQS and when clocking by DQSN
 218  */
 219 static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit)
 220 {
 221         u32 index;
 222         u32 addr = DXNDQTR(phy, byte);
 223
 224         /* We are assuming that we have the same delay when clocking by DQS
 225          * and when clocking by DQSN : use only the low bits
 226          */
 227         index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
 228                 & DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
 229
 230         pr_debug("%s: [%x]: %x => DQ unit index = %x\n",
 231                  __func__, addr, readl(addr), index);
 232
 233         return index;
 234 }
 235
 236 /* Sets the DQS phase delay for a byte lane.
 237  *phase delay is specified by giving the index of the desired delay
 238  * in the dx_dll_phase array.
 239  */
 240 static void DQS_phase_delay(struct stm32mp1_ddrphy *phy, u8 byte, u8 phase_idx)
 241 {
 242         u8 sdphase_val = 0;
 243
 244         /*      Write DXNDLLCR.SDPHASE = dx_dll_phase(phase_index); */
 245         sdphase_val = dx_dll_phase[phase_idx];
 246         clrsetbits_le32(DXNDLLCR(phy, byte),
 247                         DDRPHYC_DXNDLLCR_SDPHASE_MASK,
 248                         sdphase_val << DDRPHYC_DXNDLLCR_SDPHASE_SHIFT);
 249 }
 250
 251 /* Sets the DQS unit delay for a byte lane.
 252  * unit delay is specified by giving the index of the desired delay
 253  * for dgsdly and dqsndly (same value).
 254  */
 255 static void DQS_unit_delay(struct stm32mp1_ddrphy *phy,
 256                            u8 byte, u8 unit_dly_idx)
 257 {
 258         /* Write the same value in DXNDQSTR.DQSDLY and DXNDQSTR.DQSNDLY */
 259         clrsetbits_le32(DXNDQSTR(phy, byte),
 260                         DDRPHYC_DXNDQSTR_DQSDLY_MASK |
 261                         DDRPHYC_DXNDQSTR_DQSNDLY_MASK,
 262                         (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSDLY_SHIFT) |
 263                         (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT));
 264
 265         /* After changing this value, an ITM soft reset (PIR.ITMSRST=1,
 266          * plus PIR.INIT=1) must be issued.
 267          */
 268         stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
 269 }
 270
 271 /* Sets the DQ unit delay for a bit line in particular byte lane.
 272  * unit delay is specified by giving the desired delay
 273  */
 274 static void set_DQ_unit_delay(struct stm32mp1_ddrphy *phy,
 275                               u8 byte, u8 bit,
 276                               u8 dq_delay_index)
 277 {
 278         u8 dq_bit_delay_val = dq_delay_index | (dq_delay_index << 2);
 279
 280         /* same value on delay for clock DQ an DQS_b */
 281         clrsetbits_le32(DXNDQTR(phy, byte),
 282                         DDRPHYC_DXNDQTR_DQDLY_MASK
 283                         << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit),
 284                         dq_bit_delay_val << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit));
 285 }
 286
 287 static void set_r0dgsl_delay(struct stm32mp1_ddrphy *phy,
 288                              u8 byte, u8 r0dgsl_idx)
 289 {
 290         clrsetbits_le32(DXNDQSTR(phy, byte),
 291                         DDRPHYC_DXNDQSTR_R0DGSL_MASK,
 292                         r0dgsl_idx << DDRPHYC_DXNDQSTR_R0DGSL_SHIFT);
 293 }
 294
 295 static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy,
 296                              u8 byte, u8 r0dgps_idx)
 297 {
 298         clrsetbits_le32(DXNDQSTR(phy, byte),
 299                         DDRPHYC_DXNDQSTR_R0DGPS_MASK,
 300                         r0dgps_idx << DDRPHYC_DXNDQSTR_R0DGPS_SHIFT);
 301 }
 302
 303 /* Basic BIST configuration for data lane tests. */
 304 static void config_BIST(struct stm32mp1_ddrctl *ctl,
 305                         struct stm32mp1_ddrphy *phy)
 306 {
 307         u8 nb_bank = get_nb_bank(ctl);
 308         u8 nb_row = get_nb_row(ctl);
 309         u8 nb_col = get_nb_col(ctl);
 310
 311         /* Selects the SDRAM bank address to be used during BIST. */
 312         u32 bbank = 0;
 313         /* Selects the SDRAM row address to be used during BIST. */
 314         u32 brow = 0;
 315         /* Selects the SDRAM column address to be used during BIST. */
 316         u32 bcol = 0;
 317         /* Selects the value by which the SDRAM address is incremented
 318          * for each write/read access.
 319          */
 320         u32 bainc = 0x00000008;
 321         /* Specifies the maximum SDRAM rank to be used during BIST.
 322          * The default value is set to maximum ranks minus 1.
 323          * must be 0 with single rank
 324          */
 325         u32 bmrank = 0;
 326         /* Selects the SDRAM rank to be used during BIST.
 327          * must be 0 with single rank
 328          */
 329         u32 brank = 0;
 330
 331         /* Specifies the maximum SDRAM bank address to be used during
 332          * BIST before the address & increments to the next rank.
 333          */
 334         u32 bmbank = (1 << nb_bank) - 1;
 335         /* Specifies the maximum SDRAM row address to be used during
 336          * BIST before the address & increments to the next bank.
 337          */
 338         u32 bmrow = (1 << nb_row) - 1;
 339         /* Specifies the maximum SDRAM column address to be used during
 340          * BIST before the address & increments to the next row.
 341          */
 342         u32 bmcol = (1 << nb_col) - 1;
 343
 344         u32 bmode_conf = 0x00000001;  /* DRam mode */
 345         u32 bdxen_conf = 0x00000001;  /* BIST on Data byte */
 346         u32 bdpat_conf = 0x00000002;  /* Select LFSR pattern */
 347
 348         /*Setup BIST for DRAM mode,  and LFSR-random data pattern.*/
 349         /*Write BISTRR.BMODE = 1?b1;*/
 350         /*Write BISTRR.BDXEN = 1?b1;*/
 351         /*Write BISTRR.BDPAT = 2?b10;*/
 352
 353         /* reset BIST */
 354         writel(0x3, &phy->bistrr);
 355
 356         writel((bmode_conf << 3) | (bdxen_conf << 14) | (bdpat_conf << 17),
 357                &phy->bistrr);
 358
 359         /*Setup BIST Word Count*/
 360         /*Write BISTWCR.BWCNT = 16?b0008;*/
 361         writel(0x00000200, &phy->bistwcr); /* A multiple of BL/2 */
 362
 363         writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0);
 364         writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1);
 365         writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2);
 366 }
 367
 368 /* Select the Byte lane to be tested by BIST. */
 369 static void BIST_datx8_sel(struct stm32mp1_ddrphy *phy, u8 datx8)
 370 {
 371         clrsetbits_le32(&phy->bistrr,
 372                         DDRPHYC_BISTRR_BDXSEL_MASK,
 373                         datx8 << DDRPHYC_BISTRR_BDXSEL_SHIFT);
 374
 375         /*(For example, selecting Byte Lane 3, BISTRR.BDXSEL = 4?b0011)*/
 376         /* Write BISTRR.BDXSEL = datx8; */
 377 }
 378
 379 /* Perform BIST Write_Read test on a byte lane and return test result. */
 380 static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte,
 381                       struct BIST_result *bist)
 382 {
 383         bool result = true; /* BIST_SUCCESS */
 384         u32 cnt = 0;
 385         u32 error = 0;
 386         u32 val;
 387         int ret;
 388
 389         bist->test_result = true;
 390
 391 run:
 392         itm_soft_reset(phy);
 393
 394         /*Perform BIST Reset*/
 395         /* Write BISTRR.BINST = 3?b011; */
 396         clrsetbits_le32(&phy->bistrr,
 397                         0x00000007,
 398                         0x00000003);
 399
 400         /*Re-seed LFSR*/
 401         /* Write BISTLSR.SEED = 32'h1234ABCD; */
 402         if (BIST_seed)
 403                 writel(BIST_seed, &phy->bistlsr);
 404         else
 405                 writel(rand(), &phy->bistlsr);
 406
 407         /* some delay to reset BIST */
 408         udelay(10);
 409
 410         /*Perform BIST Run*/
 411         clrsetbits_le32(&phy->bistrr,
 412                         0x00000007,
 413                         0x00000001);
 414         /* Write BISTRR.BINST = 3?b001; */
 415
 416         /* poll on BISTGSR.BDONE and wait max 1000 us */
 417         ret = readl_poll_timeout(&phy->bistgsr, val,
 418                                  val & DDRPHYC_BISTGSR_BDDONE, 1000);
 419
 420         if (ret < 0) {
 421                 printf("warning: BIST timeout\n");
 422                 result = false; /* BIST_FAIL; */
 423                 /*Perform BIST Stop */
 424                 clrsetbits_le32(&phy->bistrr, 0x00000007, 0x00000002);
 425         } else {
 426                 /*Check if received correct number of words*/
 427                 /* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */
 428                 if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT)
 429                     == readl(&phy->bistwcr)) {
 430                         /*Determine if there is a data comparison error*/
 431                         /* if (Read BISTGSR.BDXERR = 1?b0) */
 432                         if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR)
 433                                 result = false; /* BIST_FAIL; */
 434                         else
 435                                 result = true; /* BIST_SUCCESS; */
 436                 } else {
 437                         result = false; /* BIST_FAIL; */
 438                 }
 439         }
 440
 441         /* loop while success */
 442         cnt++;
 443         if (result && cnt != 1000)
 444                 goto run;
 445
 446         if (!result)
 447                 error++;
 448
 449         if (error < BIST_error_max) {
 450                 if (cnt != 1000)
 451                         goto run;
 452                 bist->test_result = true;
 453         } else {
 454                 bist->test_result = false;
 455         }
 456 }
 457
 458 /* After running the deskew algo, this function applies the new DQ delays
 459  * by reading them from the array "deskew_delay"and writing in PHY registers.
 460  * The bits that are not deskewed parfectly (too much skew on them,
 461  * or data eye very wide) are marked in the array deskew_non_converge.
 462  */
 463 static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte,
 464                                  u8 deskew_delay[NUM_BYTES][8],
 465                                  u8 deskew_non_converge[NUM_BYTES][8])
 466 {
 467         u8  bit_i;
 468         u8  index;
 469
 470         for (bit_i = 0; bit_i < 8; bit_i++) {
 471                 set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
 472                 index = DQ_unit_index(phy, byte, bit_i);
 473                 pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
 474                          byte, bit_i, deskew_delay[byte][bit_i],
 475                          index, index - 3);
 476                 printf("Byte %d, bit %d, DQ delay = %d",
 477                        byte, bit_i, deskew_delay[byte][bit_i]);
 478                 if (deskew_non_converge[byte][bit_i] == 1)
 479                         pr_debug(" - not converged : still more skew");
 480                 printf("\n");
 481         }
 482 }
 483
 484 /* DQ Bit de-skew algorithm.
 485  * Deskews data lines as much as possible.
 486  * 1. Add delay to DQS line until finding the failure
 487  *    (normally a hold time violation)
 488  * 2. Reduce DQS line by small steps until finding the very first time
 489  *    we go back to "Pass" condition.
 490  * 3. For each DQ line, Reduce DQ delay until finding the very first failure
 491  *    (normally a hold time fail)
 492  * 4. When all bits are at their first failure delay, we can consider them
 493  *    aligned.
 494  * Handle conrer situation (Can't find Pass-fail, or fail-pass transitions
 495  * at any step)
 496  * TODO Provide a return Status. Improve doc
 497  */
 498 static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
 499                                    struct stm32mp1_ddrphy *phy, char *string)
 500 {
 501         /* New DQ delay value (index), set during Deskew algo */
 502         u8 deskew_delay[NUM_BYTES][8];
 503         /*If there is still skew on a bit, mark this bit. */
 504         u8 deskew_non_converge[NUM_BYTES][8];
 505         struct BIST_result result;
 506         s8 dqs_unit_delay_index = 0;
 507         u8 datx8 = 0;
 508         u8 bit_i = 0;
 509         s8 phase_idx = 0;
 510         s8 bit_i_delay_index = 0;
 511         u8 success = 0;
 512         struct tuning_position last_right_ok;
 513         u8 force_stop = 0;
 514         u8 fail_found;
 515         u8 error = 0;
 516         u8 nb_bytes = get_nb_bytes(ctl);
 517         /* u8 last_pass_dqs_unit = 0; */
 518
 519         memset(deskew_delay, 0, sizeof(deskew_delay));
 520         memset(deskew_non_converge, 0, sizeof(deskew_non_converge));
 521
 522         /*Disable DQS Drift Compensation*/
 523         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
 524         /*Disable all bytes*/
 525         /* Disable automatic power down of DLL and IOs when disabling
 526          * a byte (To avoid having to add programming and  delay
 527          * for a DLL re-lock when later re-enabling a disabled Byte Lane)
 528          */
 529         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
 530
 531         /* Disable all data bytes */
 532         clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
 533         clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
 534         clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
 535         clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
 536
 537         /* Config the BIST block */
 538         config_BIST(ctl, phy);
 539         pr_debug("BIST Config done.\n");
 540
 541         /* Train each byte */
 542         for (datx8 = 0; datx8 < nb_bytes; datx8++) {
 543                 if (ctrlc()) {
 544                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 545                                 datx8 + 1, nb_bytes, error);
 546                         return TEST_FAILED;
 547                 }
 548                 pr_debug("\n======================\n");
 549                 pr_debug("Start deskew byte %d .\n", datx8);
 550                 pr_debug("======================\n");
 551                 /* Enable Byte (DXNGCR, bit DXEN) */
 552                 setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
 553
 554                 /* Select the byte lane for comparison of read data */
 555                 BIST_datx8_sel(phy, datx8);
 556
 557                 /* Set all DQDLYn to maximum value. All bits within the byte
 558                  * will be delayed with DQSTR = 2 instead of max = 3
 559                  * to avoid inter bits fail influence
 560                  */
 561                 writel(0xAAAAAAAA, DXNDQTR(phy, datx8));
 562
 563                 /* Set the DQS phase delay to 90 DEG (default).
 564                  * What is defined here is the index of the desired config
 565                  * in the PHASE array.
 566                  */
 567                 phase_idx = _90deg;
 568
 569                 /* Set DQS unit delay to the max value. */
 570                 dqs_unit_delay_index = MAX_DQS_UNIT_IDX;
 571                 DQS_unit_delay(phy, datx8, dqs_unit_delay_index);
 572                 DQS_phase_delay(phy, datx8, phase_idx);
 573
 574                 /* Issue a DLL soft reset */
 575                 clrbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
 576                 setbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
 577
 578                 /* Test this typical init condition */
 579                 BIST_test(phy, datx8, &result);
 580                 success = result.test_result;
 581
 582                 /* If the test pass in this typical condition,
 583                  * start the algo with it.
 584                  * Else, look for Pass init condition
 585                  */
 586                 if (!success) {
 587                         pr_debug("Fail at init condtion. Let's look for a good init condition.\n");
 588                         success = 0; /* init */
 589                         /* Make sure we start with a PASS condition before
 590                          * looking for a fail condition.
 591                          * Find the first PASS PHASE condition
 592                          */
 593
 594                         /* escape if we find a PASS */
 595                         pr_debug("increase Phase idx\n");
 596                         while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
 597                                 DQS_phase_delay(phy, datx8, phase_idx);
 598                                 BIST_test(phy, datx8, &result);
 599                                 success = result.test_result;
 600                                 phase_idx++;
 601                         }
 602                         /* if ended with success
 603                          * ==>> Restore the fist success condition
 604                          */
 605                         if (success)
 606                                 phase_idx--; /* because it ended with ++ */
 607                 }
 608                 if (ctrlc()) {
 609                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 610                                 datx8 + 1, nb_bytes, error);
 611                         return TEST_FAILED;
 612                 }
 613                 /* We couldn't find a successful condition, its seems
 614                  * we have hold violation, lets try reduce DQS_unit Delay
 615                  */
 616                 if (!success) {
 617                         /* We couldn't find a successful condition, its seems
 618                          * we have hold violation, lets try reduce DQS_unit
 619                          * Delay
 620                          */
 621                         pr_debug("Still fail. Try decrease DQS Unit delay\n");
 622
 623                         phase_idx = 0;
 624                         dqs_unit_delay_index = 0;
 625                         DQS_phase_delay(phy, datx8, phase_idx);
 626
 627                         /* escape if we find a PASS */
 628                         while (!success &&
 629                                (dqs_unit_delay_index <=
 630                                 MAX_DQS_UNIT_IDX)) {
 631                                 DQS_unit_delay(phy, datx8,
 632                                                dqs_unit_delay_index);
 633                                 BIST_test(phy, datx8, &result);
 634                                 success = result.test_result;
 635                                 dqs_unit_delay_index++;
 636                         }
 637                         if (success) {
 638                                 /* Restore the first success condition*/
 639                                 dqs_unit_delay_index--;
 640                                 /* last_pass_dqs_unit = dqs_unit_delay_index;*/
 641                                 DQS_unit_delay(phy, datx8,
 642                                                dqs_unit_delay_index);
 643                         } else {
 644                                 /* No need to continue,
 645                                  * there is no pass region.
 646                                  */
 647                                 force_stop = 1;
 648                         }
 649                 }
 650
 651                 /* There is an initial PASS condition
 652                  * Look for the first failing condition by PHASE stepping.
 653                  * This part of the algo can finish without converging.
 654                  */
 655                 if (force_stop) {
 656                         printf("Result: Failed ");
 657                         printf("[Cannot Deskew lines, ");
 658                         printf("there is no PASS region]\n");
 659                         error++;
 660                         continue;
 661                 }
 662                 if (ctrlc()) {
 663                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 664                                 datx8 + 1, nb_bytes, error);
 665                         return TEST_FAILED;
 666                 }
 667
 668                 pr_debug("there is a pass region for phase idx %d\n",
 669                          phase_idx);
 670                 pr_debug("Step1: Find the first failing condition\n");
 671                 /* Look for the first failing condition by PHASE stepping.
 672                  * This part of the algo can finish without converging.
 673                  */
 674
 675                 /* escape if we find a fail (hold time violation)
 676                  * condition at any bit or if out of delay range.
 677                  */
 678                 while (success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
 679                         DQS_phase_delay(phy, datx8, phase_idx);
 680                         BIST_test(phy, datx8, &result);
 681                         success = result.test_result;
 682                         phase_idx++;
 683                 }
 684                 if (ctrlc()) {
 685                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 686                                 datx8 + 1, nb_bytes, error);
 687                         return TEST_FAILED;
 688                 }
 689
 690                 /* if the loop ended with a failing condition at any bit,
 691                  * lets look for the first previous success condition by unit
 692                  * stepping (minimal delay)
 693                  */
 694                 if (!success) {
 695                         pr_debug("Fail region (PHASE) found phase idx %d\n",
 696                                  phase_idx);
 697                         pr_debug("Let's look for first success by DQS Unit steps\n");
 698                         /* This part, the algo always converge */
 699                         phase_idx--;
 700
 701                         /* escape if we find a success condition
 702                          * or if out of delay range.
 703                          */
 704                         while (!success && dqs_unit_delay_index >= 0) {
 705                                 DQS_unit_delay(phy, datx8,
 706                                                dqs_unit_delay_index);
 707                                 BIST_test(phy, datx8, &result);
 708                                 success = result.test_result;
 709                                 dqs_unit_delay_index--;
 710                         }
 711                         /* if the loop ended with a success condition,
 712                          * the last delay Right OK (before hold violation)
 713                          *  condition is then defined as following:
 714                          */
 715                         if (success) {
 716                                 /* Hold the dely parameters of the the last
 717                                  * delay Right OK condition.
 718                                  * -1 to get back to current condition
 719                                  */
 720                                 last_right_ok.phase = phase_idx;
 721                                 /*+1 to get back to current condition */
 722                                 last_right_ok.unit = dqs_unit_delay_index + 1;
 723                                 last_right_ok.bits_delay = 0xFFFFFFFF;
 724                                 pr_debug("Found %d\n", dqs_unit_delay_index);
 725                         } else {
 726                                 /* the last OK condition is then with the
 727                                  * previous phase_idx.
 728                                  * -2 instead of -1 because at the last
 729                                  * iteration of the while(),
 730                                  * we incremented phase_idx
 731                                  */
 732                                 last_right_ok.phase = phase_idx - 1;
 733                                 /* Nominal+1. Because we want the previous
 734                                  * delay after reducing the phase delay.
 735                                  */
 736                                 last_right_ok.unit = 1;
 737                                 last_right_ok.bits_delay = 0xFFFFFFFF;
 738                                 pr_debug("Not Found : try previous phase %d\n",
 739                                          phase_idx - 1);
 740
 741                                 DQS_phase_delay(phy, datx8, phase_idx - 1);
 742                                 dqs_unit_delay_index = 0;
 743                                 success = true;
 744                                 while (success &&
 745                                        (dqs_unit_delay_index <
 746                                         MAX_DQS_UNIT_IDX)) {
 747                                         DQS_unit_delay(phy, datx8,
 748                                                        dqs_unit_delay_index);
 749                                         BIST_test(phy, datx8, &result);
 750                                         success = result.test_result;
 751                                         dqs_unit_delay_index++;
 752                                         pr_debug("dqs_unit_delay_index = %d, result = %d\n",
 753                                                  dqs_unit_delay_index, success);
 754                                 }
 755
 756                                 if (!success) {
 757                                         last_right_ok.unit =
 758                                                  dqs_unit_delay_index - 1;
 759                                 } else {
 760                                         last_right_ok.unit = 0;
 761                                         pr_debug("ERROR: failed region not FOUND");
 762                                 }
 763                         }
 764                 } else {
 765                         /* we can't find a failing  condition at all bits
 766                          * ==> Just hold the last test condition
 767                          * (the max DQS delay)
 768                          * which is the most likely,
 769                          * the closest to a hold violation
 770                          * If we can't find a Fail condition after
 771                          * the Pass region, stick at this position
 772                          * In order to have max chances to find a fail
 773                          * when reducing DQ delays.
 774                          */
 775                         last_right_ok.phase = MAX_DQS_PHASE_IDX;
 776                         last_right_ok.unit = MAX_DQS_UNIT_IDX;
 777                         last_right_ok.bits_delay = 0xFFFFFFFF;
 778                         pr_debug("Can't find the a fail condition\n");
 779                 }
 780
 781                 /* step 2:
 782                  * if we arrive at this stage, it means that we found the last
 783                  * Right OK condition (by tweeking the DQS delay). Or we simply
 784                  * pushed DQS delay to the max
 785                  * This means that by reducing the delay on some DQ bits,
 786                  * we should find a failing condition.
 787                  */
 788                 printf("Byte %d, DQS unit = %d, phase = %d\n",
 789                        datx8, last_right_ok.unit, last_right_ok.phase);
 790                 pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
 791                          last_right_ok.unit, last_right_ok.phase,
 792                          last_right_ok.bits_delay);
 793
 794                 /* Restore the last_right_ok condtion. */
 795                 DQS_unit_delay(phy, datx8, last_right_ok.unit);
 796                 DQS_phase_delay(phy, datx8, last_right_ok.phase);
 797                 writel(last_right_ok.bits_delay, DXNDQTR(phy, datx8));
 798
 799                 /* train each bit
 800                  * reduce delay on each bit, and perform a write/read test
 801                  * and stop at the very first time it fails.
 802                  * the goal is the find the first failing condition
 803                  * for each bit.
 804                  * When we achieve this condition<  for all the bits,
 805                  * we are sure they are aligned (+/- step resolution)
 806                  */
 807                 fail_found = 0;
 808                 for (bit_i = 0; bit_i < 8; bit_i++) {
 809                         if (ctrlc()) {
 810                                 sprintf(string,
 811                                         "interrupted at byte %d/%d, error=%d",
 812                                         datx8 + 1, nb_bytes, error);
 813                                 return error;
 814                         }
 815                         pr_debug("deskewing bit %d:\n", bit_i);
 816                         success = 1; /* init */
 817                         /* Set all DQDLYn to maximum value.
 818                          * Only bit_i will be down-delayed
 819                          * ==> if we have a fail, it will be definitely
 820                          *     from bit_i
 821                          */
 822                         writel(0xFFFFFFFF, DXNDQTR(phy, datx8));
 823                         /* Arriving at this stage,
 824                          * we have a success condition with delay = 3;
 825                          */
 826                         bit_i_delay_index = 3;
 827
 828                         /* escape if bit delay is out of range or
 829                          * if a fatil occurs
 830                          */
 831                         while ((bit_i_delay_index >= 0) && success) {
 832                                 set_DQ_unit_delay(phy, datx8,
 833                                                   bit_i,
 834                                                   bit_i_delay_index);
 835                                 BIST_test(phy, datx8, &result);
 836                                 success = result.test_result;
 837                                 bit_i_delay_index--;
 838                         }
 839
 840                         /* if escape with a fail condition
 841                          * ==> save this position for bit_i
 842                          */
 843                         if (!success) {
 844                                 /* save the delay position.
 845                                  * Add 1 because the while loop ended with a --,
 846                                  * and that we need to hold the last success
 847                                  *  delay
 848                                  */
 849                                 deskew_delay[datx8][bit_i] =
 850                                         bit_i_delay_index + 2;
 851                                 if (deskew_delay[datx8][bit_i] > 3)
 852                                         deskew_delay[datx8][bit_i] = 3;
 853
 854                                 /* A flag that states we found at least a fail
 855                                  * at one bit.
 856                                  */
 857                                 fail_found = 1;
 858                                 pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
 859                                          bit_i, bit_i_delay_index + 1,
 860                                          datx8, bit_i,
 861                                          deskew_delay[datx8][bit_i]);
 862                         } else {
 863                                 /* if we can find a success condition by
 864                                  * back-delaying this bit, just set the delay
 865                                  * to 0 (the best deskew
 866                                  * possible) and mark the bit.
 867                                  */
 868                                 deskew_delay[datx8][bit_i] = 0;
 869                                 /* set a flag that will be used later
 870                                  * in the report.
 871                                  */
 872                                 deskew_non_converge[datx8][bit_i] = 1;
 873                                 pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
 874                                          bit_i, datx8, bit_i,
 875                                          deskew_delay[datx8][bit_i]);
 876                         }
 877                 }
 878                 pr_debug("**********byte %d tuning complete************\n",
 879                          datx8);
 880                 /* If we can't find any failure by back delaying DQ lines,
 881                  * hold the default values
 882                  */
 883                 if (!fail_found) {
 884                         for (bit_i = 0; bit_i < 8; bit_i++)
 885                                 deskew_delay[datx8][bit_i] = 0;
 886                         pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
 887                 }
 888
 889                 apply_deskew_results(phy, datx8, deskew_delay,
 890                                      deskew_non_converge);
 891                 /* Restore nominal value for DQS delay */
 892                 DQS_phase_delay(phy, datx8, 3);
 893                 DQS_unit_delay(phy, datx8, 3);
 894                 /* disable byte after byte bits deskew */
 895                 clrbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
 896         }  /* end of byte deskew */
 897
 898         /* re-enable all data bytes */
 899         setbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
 900         setbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
 901         setbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
 902         setbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
 903
 904         if (error) {
 905                 sprintf(string, "error = %d", error);
 906                 return TEST_FAILED;
 907         }
 908
 909         return TEST_PASSED;
 910 } /* end function */
 911
 912 /* Trim DQS timings and set it in the centre of data eye.
 913  * Look for a PPPPF region, then look for a FPPP region and finally select
 914  * the mid of the FPPPPPF region
 915  */
 916 static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
 917                                      struct stm32mp1_ddrphy *phy, char *string)
 918 {
 919         /*Stores the DQS trim values (PHASE index, unit index) */
 920         u8 eye_training_val[NUM_BYTES][2];
 921         u8 byte = 0;
 922         struct BIST_result result;
 923         s8 dqs_unit_delay_index = 0;
 924         s8 phase_idx = 0;
 925         s8 dqs_unit_delay_index_pass = 0;
 926         s8 phase_idx_pass = 0;
 927         u8 success = 0;
 928         u8 left_phase_bound_found, right_phase_bound_found;
 929         u8 left_unit_bound_found, right_unit_bound_found;
 930         u8 left_bound_found, right_bound_found;
 931         struct tuning_position left_bound, right_bound;
 932         u8 error = 0;
 933         u8 nb_bytes = get_nb_bytes(ctl);
 934
 935         /*Disable DQS Drift Compensation*/
 936         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
 937         /*Disable all bytes*/
 938         /* Disable automatic power down of DLL and IOs when disabling a byte
 939          * (To avoid having to add programming and  delay
 940          * for a DLL re-lock when later re-enabling a disabled Byte Lane)
 941          */
 942         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
 943
 944         /*Disable all data bytes */
 945         clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
 946         clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
 947         clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
 948         clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
 949
 950         /* Config the BIST block */
 951         config_BIST(ctl, phy);
 952
 953         for (byte = 0; byte < nb_bytes; byte++) {
 954                 if (ctrlc()) {
 955                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 956                                 byte + 1, nb_bytes, error);
 957                         return TEST_FAILED;
 958                 }
 959                 right_bound.phase = 0;
 960                 right_bound.unit = 0;
 961
 962                 left_bound.phase = 0;
 963                 left_bound.unit = 0;
 964
 965                 left_phase_bound_found = 0;
 966                 right_phase_bound_found = 0;
 967
 968                 left_unit_bound_found = 0;
 969                 right_unit_bound_found = 0;
 970
 971                 left_bound_found = 0;
 972                 right_bound_found = 0;
 973
 974                 /* Enable Byte (DXNGCR, bit DXEN) */
 975                 setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
 976
 977                 /* Select the byte lane for comparison of read data */
 978                 BIST_datx8_sel(phy, byte);
 979
 980                 /* Set DQS phase delay to the nominal value. */
 981                 phase_idx = _90deg;
 982                 phase_idx_pass = phase_idx;
 983
 984                 /* Set DQS unit delay to the nominal value. */
 985                 dqs_unit_delay_index = 3;
 986                 dqs_unit_delay_index_pass = dqs_unit_delay_index;
 987                 success = 0;
 988
 989                 pr_debug("STEP0: Find Init delay\n");
 990                 /* STEP0: Find Init delay: a delay that put the system
 991                  * in a "Pass" condition then (TODO) update
 992                  * dqs_unit_delay_index_pass & phase_idx_pass
 993                  */
 994                 DQS_unit_delay(phy, byte, dqs_unit_delay_index);
 995                 DQS_phase_delay(phy, byte, phase_idx);
 996                 BIST_test(phy, byte, &result);
 997                 success = result.test_result;
 998                 /* If we have a fail in the nominal condition */
 999                 if (!success) {
1000                         /* Look at the left */
1001                         while (phase_idx >= 0 && !success) {
1002                                 phase_idx--;
1003                                 DQS_phase_delay(phy, byte, phase_idx);
1004                                 BIST_test(phy, byte, &result);
1005                                 success = result.test_result;
1006                         }
1007                 }
1008                 if (!success) {
1009                         /* if we can't find pass condition,
1010                          * then look at the right
1011                          */
1012                         phase_idx = _90deg;
1013                         while (phase_idx <= MAX_DQS_PHASE_IDX &&
1014                                !success) {
1015                                 phase_idx++;
1016                                 DQS_phase_delay(phy, byte,
1017                                                 phase_idx);
1018                                 BIST_test(phy, byte, &result);
1019                                 success = result.test_result;
1020                         }
1021                 }
1022                 /* save the pass condition */
1023                 if (success) {
1024                         phase_idx_pass = phase_idx;
1025                 } else {
1026                         printf("Result: Failed ");
1027                         printf("[Cannot DQS timings, ");
1028                         printf("there is no PASS region]\n");
1029                         error++;
1030                         continue;
1031                 }
1032
1033                 if (ctrlc()) {
1034                         sprintf(string, "interrupted at byte %d/%d, error=%d",
1035                                 byte + 1, nb_bytes, error);
1036                         return TEST_FAILED;
1037                 }
1038                 pr_debug("STEP1: Find LEFT PHASE DQS Bound\n");
1039                 /* STEP1: Find LEFT PHASE DQS Bound */
1040                 while ((phase_idx >= 0) &&
1041                        (phase_idx <= MAX_DQS_PHASE_IDX) &&
1042                        !left_phase_bound_found) {
1043                         DQS_unit_delay(phy, byte,
1044                                        dqs_unit_delay_index);
1045                         DQS_phase_delay(phy, byte,
1046                                         phase_idx);
1047                         BIST_test(phy, byte, &result);
1048                         success = result.test_result;
1049
1050                         /*TODO: Manage the case were at the beginning
1051                          * there is already a fail
1052                          */
1053                         if (!success) {
1054                                 /* the last pass condition */
1055                                 left_bound.phase = ++phase_idx;
1056                                 left_phase_bound_found = 1;
1057                         } else if (success) {
1058                                 phase_idx--;
1059                         }
1060                 }
1061                 if (!left_phase_bound_found) {
1062                         left_bound.phase = 0;
1063                         phase_idx = 0;
1064                 }
1065                 /* If not found, lets take 0 */
1066
1067                 if (ctrlc()) {
1068                         sprintf(string, "interrupted at byte %d/%d, error=%d",
1069                                 byte + 1, nb_bytes, error);
1070                         return TEST_FAILED;
1071                 }
1072                 pr_debug("STEP2: Find UNIT left bound\n");
1073                 /* STEP2: Find UNIT left bound */
1074                 while ((dqs_unit_delay_index >= 0) &&
1075                        !left_unit_bound_found) {
1076                         DQS_unit_delay(phy, byte,
1077                                        dqs_unit_delay_index);
1078                         DQS_phase_delay(phy, byte, phase_idx);
1079                         BIST_test(phy, byte, &result);
1080                         success = result.test_result;
1081                         if (!success) {
1082                                 left_bound.unit =
1083                                         ++dqs_unit_delay_index;
1084                                 left_unit_bound_found = 1;
1085                                 left_bound_found = 1;
1086                         } else if (success) {
1087                                 dqs_unit_delay_index--;
1088                         }
1089                 }
1090
1091                 /* If not found, lets take 0 */
1092                 if (!left_unit_bound_found)
1093                         left_bound.unit = 0;
1094
1095                 if (ctrlc()) {
1096                         sprintf(string, "interrupted at byte %d/%d, error=%d",
1097                                 byte + 1, nb_bytes, error);
1098                         return TEST_FAILED;
1099                 }
1100                 pr_debug("STEP3: Find PHase right bound\n");
1101                 /* STEP3: Find PHase right bound, start with "pass"
1102                  * condition
1103                  */
1104
1105                 /* Set DQS phase delay to the pass value. */
1106                 phase_idx = phase_idx_pass;
1107
1108                 /* Set DQS unit delay to the pass value. */
1109                 dqs_unit_delay_index = dqs_unit_delay_index_pass;
1110
1111                 while ((phase_idx <= MAX_DQS_PHASE_IDX) &&
1112                        !right_phase_bound_found) {
1113                         DQS_unit_delay(phy, byte,
1114                                        dqs_unit_delay_index);
1115                         DQS_phase_delay(phy, byte, phase_idx);
1116                         BIST_test(phy, byte, &result);
1117                         success = result.test_result;
1118                         if (!success) {
1119                                 /* the last pass condition */
1120                                 right_bound.phase = --phase_idx;
1121                                 right_phase_bound_found = 1;
1122                         } else if (success) {
1123                                 phase_idx++;
1124                         }
1125                 }
1126
1127                 /* If not found, lets take the max value */
1128                 if (!right_phase_bound_found) {
1129                         right_bound.phase = MAX_DQS_PHASE_IDX;
1130                         phase_idx = MAX_DQS_PHASE_IDX;
1131                 }
1132
1133                 if (ctrlc()) {
1134                         sprintf(string, "interrupted at byte %d/%d, error=%d",
1135                                 byte + 1, nb_bytes, error);
1136                         return TEST_FAILED;
1137                 }
1138                 pr_debug("STEP4: Find UNIT right bound\n");
1139                 /* STEP4: Find UNIT right bound */
1140                 while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
1141                        !right_unit_bound_found) {
1142                         DQS_unit_delay(phy, byte,
1143                                        dqs_unit_delay_index);
1144                         DQS_phase_delay(phy, byte, phase_idx);
1145                         BIST_test(phy, byte, &result);
1146                         success = result.test_result;
1147                         if (!success) {
1148                                 right_bound.unit =
1149                                         --dqs_unit_delay_index;
1150                                 right_unit_bound_found = 1;
1151                                 right_bound_found = 1;
1152                         } else if (success) {
1153                                 dqs_unit_delay_index++;
1154                         }
1155                 }
1156                 /* If not found, lets take the max value */
1157                 if (!right_unit_bound_found)
1158                         right_bound.unit = MAX_DQS_UNIT_IDX;
1159
1160                 /* If we found a regular FAil Pass FAil pattern
1161                  * FFPPPPPPFF
1162                  * OR PPPPPFF  Or FFPPPPP
1163                  */
1164
1165                 if (left_bound_found || right_bound_found) {
1166                         eye_training_val[byte][0] = (right_bound.phase +
1167                                                  left_bound.phase) / 2;
1168                         eye_training_val[byte][1] = (right_bound.unit +
1169                                                  left_bound.unit) / 2;
1170
1171                         /* If we already lost 1/2PHASE Tuning,
1172                          * let's try to recover by ++ on unit
1173                          */
1174                         if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
1175                             eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
1176                                 eye_training_val[byte][1]++;
1177                         pr_debug("** found phase : %d -  %d & unit %d - %d\n",
1178                                  right_bound.phase, left_bound.phase,
1179                                  right_bound.unit, left_bound.unit);
1180                         pr_debug("** calculating mid region: phase: %d  unit: %d (nominal is 3)\n",
1181                                  eye_training_val[byte][0],
1182                                  eye_training_val[byte][1]);
1183                 } else {
1184                         /* PPPPPPPPPP, we're already good.
1185                          * Set nominal values.
1186                          */
1187                         eye_training_val[byte][0] = 3;
1188                         eye_training_val[byte][1] = 3;
1189                 }
1190                 DQS_phase_delay(phy, byte, eye_training_val[byte][0]);
1191                 DQS_unit_delay(phy, byte, eye_training_val[byte][1]);
1192
1193                 printf("Byte %d, DQS unit = %d, phase = %d\n",
1194                        byte,
1195                        eye_training_val[byte][1],
1196                        eye_training_val[byte][0]);
1197         }
1198
1199         if (error) {
1200                 sprintf(string, "error = %d", error);
1201                 return TEST_FAILED;
1202         }
1203
1204         return TEST_PASSED;
1205 }
1206
1207 static void display_reg_results(struct stm32mp1_ddrphy *phy, u8 byte)
1208 {
1209         u8 i = 0;
1210
1211         printf("Byte %d Dekew result, bit0 delay, bit1 delay...bit8 delay\n  ",
1212                byte);
1213
1214         for (i = 0; i < 8; i++)
1215                 printf("%d ", DQ_unit_index(phy, byte, i));
1216         printf("\n");
1217
1218         printf("dxndllcr: [%08x] val:%08x\n",
1219                DXNDLLCR(phy, byte),
1220                readl(DXNDLLCR(phy, byte)));
1221         printf("dxnqdstr: [%08x] val:%08x\n",
1222                DXNDQSTR(phy, byte),
1223                readl(DXNDQSTR(phy, byte)));
1224         printf("dxndqtr: [%08x] val:%08x\n",
1225                DXNDQTR(phy, byte),
1226                readl(DXNDQTR(phy, byte)));
1227 }
1228
1229 /* analyse the dgs gating log table, and determine the midpoint.*/
1230 static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
1231                                        u8 dqs_gating[NUM_BYTES]
1232                                                     [MAX_GSL_IDX + 1]
1233                                                     [MAX_GPS_IDX + 1])
1234 {
1235         /* stores the dqs gate values (gsl index, gps index) */
1236         u8 dqs_gate_values[NUM_BYTES][2];
1237         u8 gsl_idx, gps_idx = 0;
1238         u8 left_bound_idx[2] = {0, 0};
1239         u8 right_bound_idx[2] = {0, 0};
1240         u8 left_bound_found = 0;
1241         u8 right_bound_found = 0;
1242         u8 intermittent = 0;
1243         u8 value;
1244
1245         for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
1246                 for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
1247                         value = dqs_gating[byte][gsl_idx][gps_idx];
1248                         if (value == 1 && left_bound_found == 0) {
1249                                 left_bound_idx[0] = gsl_idx;
1250                                 left_bound_idx[1] = gps_idx;
1251                                 left_bound_found = 1;
1252                         } else if (value == 0 &&
1253                                    left_bound_found == 1 &&
1254                                    !right_bound_found) {
1255                                 if (gps_idx == 0) {
1256                                         right_bound_idx[0] = gsl_idx - 1;
1257                                         right_bound_idx[1] = MAX_GPS_IDX;
1258                                 } else {
1259                                         right_bound_idx[0] = gsl_idx;
1260                                         right_bound_idx[1] = gps_idx - 1;
1261                                 }
1262                                 right_bound_found = 1;
1263                         } else if (value == 1 &&
1264                                    right_bound_found == 1) {
1265                                 intermittent = 1;
1266                         }
1267                 }
1268         }
1269
1270         /* if only ppppppp is found, there is no mid region. */
1271         if (left_bound_idx[0] == 0 && left_bound_idx[1] == 0 &&
1272             right_bound_idx[0] == 0 && right_bound_idx[1] == 0)
1273                 intermittent = 1;
1274
1275         /*if we found a regular fail pass fail pattern ffppppppff
1276          * or pppppff  or ffppppp
1277          */
1278         if (!intermittent) {
1279                 /*if we found a regular fail pass fail pattern ffppppppff
1280                  * or pppppff  or ffppppp
1281                  */
1282                 if (left_bound_found || right_bound_found) {
1283                         pr_debug("idx0(%d): %d %d      idx1(%d) : %d %d\n",
1284                                  left_bound_found,
1285                                  right_bound_idx[0], left_bound_idx[0],
1286                                  right_bound_found,
1287                                  right_bound_idx[1], left_bound_idx[1]);
1288                         dqs_gate_values[byte][0] =
1289                                 (right_bound_idx[0] + left_bound_idx[0]) / 2;
1290                         dqs_gate_values[byte][1] =
1291                                 (right_bound_idx[1] + left_bound_idx[1]) / 2;
1292                         /* if we already lost 1/2gsl tuning,
1293                          * let's try to recover by ++ on gps
1294                          */
1295                         if (((right_bound_idx[0] +
1296                               left_bound_idx[0]) % 2 == 1) &&
1297                             dqs_gate_values[byte][1] != MAX_GPS_IDX)
1298                                 dqs_gate_values[byte][1]++;
1299                         /* if we already lost 1/2gsl tuning and gps is on max*/
1300                         else if (((right_bound_idx[0] +
1301                                    left_bound_idx[0]) % 2 == 1) &&
1302                                  dqs_gate_values[byte][1] == MAX_GPS_IDX) {
1303                                 dqs_gate_values[byte][1] = 0;
1304                                 dqs_gate_values[byte][0]++;
1305                         }
1306                         /* if we have gsl left and write limit too close
1307                          * (difference=1)
1308                          */
1309                         if (((right_bound_idx[0] - left_bound_idx[0]) == 1)) {
1310                                 dqs_gate_values[byte][1] = (left_bound_idx[1] +
1311                                                             right_bound_idx[1] +
1312                                                             4) / 2;
1313                                 if (dqs_gate_values[byte][1] >= 4) {
1314                                         dqs_gate_values[byte][0] =
1315                                                 right_bound_idx[0];
1316                                         dqs_gate_values[byte][1] -= 4;
1317                                 } else {
1318                                         dqs_gate_values[byte][0] =
1319                                                 left_bound_idx[0];
1320                                 }
1321                         }
1322                         pr_debug("*******calculating mid region: system latency: %d  phase: %d********\n",
1323                                  dqs_gate_values[byte][0],
1324                                  dqs_gate_values[byte][1]);
1325                         pr_debug("*******the nominal values were system latency: 0  phase: 2*******\n");
1326                 }
1327         } else {
1328                 /* if intermitant, restore defaut values */
1329                 pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
1330                 dqs_gate_values[byte][0] = 0;
1331                 dqs_gate_values[byte][1] = 2;
1332         }
1333         set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]);
1334         set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]);
1335         printf("Byte %d, R0DGSL = %d, R0DGPS = %d\n",
1336                byte, dqs_gate_values[byte][0], dqs_gate_values[byte][1]);
1337
1338         /* return 0 if intermittent or if both left_bound
1339          * and right_bound are not found
1340          */
1341         return !(intermittent || (left_bound_found && right_bound_found));
1342 }
1343
1344 static enum test_result read_dqs_gating(struct stm32mp1_ddrctl *ctl,
1345                                         struct stm32mp1_ddrphy *phy,
1346                                         char *string)
1347 {
1348         /* stores the log of pass/fail */
1349         u8 dqs_gating[NUM_BYTES][MAX_GSL_IDX + 1][MAX_GPS_IDX + 1];
1350         u8 byte, gsl_idx, gps_idx = 0;
1351         struct BIST_result result;
1352         u8 success = 0;
1353         u8 nb_bytes = get_nb_bytes(ctl);
1354
1355         memset(dqs_gating, 0x0, sizeof(dqs_gating));
1356
1357         /*disable dqs drift compensation*/
1358         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
1359         /*disable all bytes*/
1360         /* disable automatic power down of dll and ios when disabling a byte
1361          * (to avoid having to add programming and  delay
1362          * for a dll re-lock when later re-enabling a disabled byte lane)
1363          */
1364         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
1365
1366         /* disable all data bytes */
1367         clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
1368         clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
1369         clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
1370         clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
1371
1372         /* config the bist block */
1373         config_BIST(ctl, phy);
1374
1375         for (byte = 0; byte < nb_bytes; byte++) {
1376                 if (ctrlc()) {
1377                         sprintf(string, "interrupted at byte %d/%d",
1378                                 byte + 1, nb_bytes);
1379                         return TEST_FAILED;
1380                 }
1381                 /* enable byte x (dxngcr, bit dxen) */
1382                 setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
1383
1384                 /* select the byte lane for comparison of read data */
1385                 BIST_datx8_sel(phy, byte);
1386                 for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
1387                         for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
1388                                 if (ctrlc()) {
1389                                         sprintf(string,
1390                                                 "interrupted at byte %d/%d",
1391                                                 byte + 1, nb_bytes);
1392                                         return TEST_FAILED;
1393                                 }
1394                                 /* write cfg to dxndqstr */
1395                                 set_r0dgsl_delay(phy, byte, gsl_idx);
1396                                 set_r0dgps_delay(phy, byte, gps_idx);
1397
1398                                 BIST_test(phy, byte, &result);
1399                                 success = result.test_result;
1400                                 if (success)
1401                                         dqs_gating[byte][gsl_idx][gps_idx] = 1;
1402                                 itm_soft_reset(phy);
1403                         }
1404                 }
1405                 set_midpoint_read_dqs_gating(phy, byte, dqs_gating);
1406                 /* dummy reads */
1407                 readl(0xc0000000);
1408                 readl(0xc0000000);
1409         }
1410
1411         /* re-enable drift compensation */
1412         /* setbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); */
1413         return TEST_PASSED;
1414 }
1415
1416 /****************************************************************
1417  * TEST
1418  ****************************************************************
1419  */
1420 static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl,
1421                                            struct stm32mp1_ddrphy *phy,
1422                                            char *string, int argc,
1423                                            char *argv[])
1424 {
1425         u32 rfshctl3 = readl(&ctl->rfshctl3);
1426         u32 pwrctl = readl(&ctl->pwrctl);
1427         u32 derateen = readl(&ctl->derateen);
1428         enum test_result res;
1429
1430         writel(0x0, &ctl->derateen);
1431         stm32mp1_refresh_disable(ctl);
1432
1433         res = read_dqs_gating(ctl, phy, string);
1434
1435         stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
1436         writel(derateen, &ctl->derateen);
1437
1438         return res;
1439 }
1440
1441 static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl,
1442                                       struct stm32mp1_ddrphy *phy,
1443                                       char *string, int argc, char *argv[])
1444 {
1445         u32 rfshctl3 = readl(&ctl->rfshctl3);
1446         u32 pwrctl = readl(&ctl->pwrctl);
1447         u32 derateen = readl(&ctl->derateen);
1448         enum test_result res;
1449
1450         writel(0x0, &ctl->derateen);
1451         stm32mp1_refresh_disable(ctl);
1452
1453         res = bit_deskew(ctl, phy, string);
1454
1455         stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
1456         writel(derateen, &ctl->derateen);
1457
1458         return res;
1459 }
1460
1461 static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl,
1462                                         struct stm32mp1_ddrphy *phy,
1463                                         char *string, int argc, char *argv[])
1464 {
1465         u32 rfshctl3 = readl(&ctl->rfshctl3);
1466         u32 pwrctl = readl(&ctl->pwrctl);
1467         u32 derateen = readl(&ctl->derateen);
1468         enum test_result res;
1469
1470         writel(0x0, &ctl->derateen);
1471         stm32mp1_refresh_disable(ctl);
1472
1473         res = eye_training(ctl, phy, string);
1474
1475         stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
1476         writel(derateen, &ctl->derateen);
1477
1478         return res;
1479 }
1480
1481 static enum test_result do_display(struct stm32mp1_ddrctl *ctl,
1482                                    struct stm32mp1_ddrphy *phy,
1483                                    char *string, int argc, char *argv[])
1484 {
1485         int byte;
1486         u8 nb_bytes = get_nb_bytes(ctl);
1487
1488         for (byte = 0; byte < nb_bytes; byte++)
1489                 display_reg_results(phy, byte);
1490
1491         return TEST_PASSED;
1492 }
1493
1494 static enum test_result do_bist_config(struct stm32mp1_ddrctl *ctl,
1495                                        struct stm32mp1_ddrphy *phy,
1496                                        char *string, int argc, char *argv[])
1497 {
1498         unsigned long value;
1499
1500         if (argc > 0) {
1501                 if (strict_strtoul(argv[0], 0, &value) < 0) {
1502                         sprintf(string, "invalid nbErr %s", argv[0]);
1503                         return TEST_FAILED;
1504                 }
1505                 BIST_error_max = value;
1506         }
1507         if (argc > 1) {
1508                 if (strict_strtoul(argv[1], 0, &value) < 0) {
1509                         sprintf(string, "invalid Seed %s", argv[1]);
1510                         return TEST_FAILED;
1511                 }
1512                 BIST_seed = value;
1513         }
1514         printf("Bist.nbErr = %d\n", BIST_error_max);
1515         if (BIST_seed)
1516                 printf("Bist.Seed = 0x%x\n", BIST_seed);
1517         else
1518                 printf("Bist.Seed = random\n");
1519
1520         return TEST_PASSED;
1521 }
1522
1523 /****************************************************************
1524  * TEST Description
1525  ****************************************************************
1526  */
1527
1528 const struct test_desc tuning[] = {
1529         {do_read_dqs_gating, "Read DQS gating",
1530                 "software read DQS Gating", "", 0 },
1531         {do_bit_deskew, "Bit de-skew", "", "", 0 },
1532         {do_eye_training, "Eye Training", "or DQS training", "", 0 },
1533         {do_display, "Display registers", "", "", 0 },
1534         {do_bist_config, "Bist config", "[nbErr] [seed]",
1535          "configure Bist test", 2},
1536 };
1537
1538 const int tuning_nb = ARRAY_SIZE(tuning);