drivers/ram/stm32_sdram.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <ram.h>
  13 #include <asm/io.h>
  14 #include <dm/device_compat.h>
  15
  16 #define MEM_MODE_MASK   GENMASK(2, 0)
  17 #define SWP_FMC_OFFSET 10
  18 #define SWP_FMC_MASK    GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET)
  19 #define NOT_FOUND       0xff
  20
  21 struct stm32_fmc_regs {
  22         /* 0x0 */
  23         u32 bcr1;       /* NOR/PSRAM Chip select control register 1 */
  24         u32 btr1;       /* SRAM/NOR-Flash Chip select timing register 1 */
  25         u32 bcr2;       /* NOR/PSRAM Chip select Control register 2 */
  26         u32 btr2;       /* SRAM/NOR-Flash Chip select timing register 2 */
  27         u32 bcr3;       /* NOR/PSRAMChip select Control register 3 */
  28         u32 btr3;       /* SRAM/NOR-Flash Chip select timing register 3 */
  29         u32 bcr4;       /* NOR/PSRAM Chip select Control register 4 */
  30         u32 btr4;       /* SRAM/NOR-Flash Chip select timing register 4 */
  31         u32 reserved1[24];
  32
  33         /* 0x80 */
  34         u32 pcr;        /* NAND Flash control register */
  35         u32 sr;         /* FIFO status and interrupt register */
  36         u32 pmem;       /* Common memory space timing register */
  37         u32 patt;       /* Attribute memory space timing registers  */
  38         u32 reserved2[1];
  39         u32 eccr;       /* ECC result registers */
  40         u32 reserved3[27];
  41
  42         /* 0x104 */
  43         u32 bwtr1;      /* SRAM/NOR-Flash write timing register 1 */
  44         u32 reserved4[1];
  45         u32 bwtr2;      /* SRAM/NOR-Flash write timing register 2 */
  46         u32 reserved5[1];
  47         u32 bwtr3;      /* SRAM/NOR-Flash write timing register 3 */
  48         u32 reserved6[1];
  49         u32 bwtr4;      /* SRAM/NOR-Flash write timing register 4 */
  50         u32 reserved7[8];
  51
  52         /* 0x140 */
  53         u32 sdcr1;      /* SDRAM Control register 1 */
  54         u32 sdcr2;      /* SDRAM Control register 2 */
  55         u32 sdtr1;      /* SDRAM Timing register 1 */
  56         u32 sdtr2;      /* SDRAM Timing register 2 */
  57         u32 sdcmr;      /* SDRAM Mode register */
  58         u32 sdrtr;      /* SDRAM Refresh timing register */
  59         u32 sdsr;       /* SDRAM Status register */
  60 };
  61
  62 /*
  63  * NOR/PSRAM Control register BCR1
  64  * FMC controller Enable, only availabe for H7
  65  */
  66 #define FMC_BCR1_FMCEN          BIT(31)
  67
  68 /* Control register SDCR */
  69 #define FMC_SDCR_RPIPE_SHIFT    13      /* RPIPE bit shift */
  70 #define FMC_SDCR_RBURST_SHIFT   12      /* RBURST bit shift */
  71 #define FMC_SDCR_SDCLK_SHIFT    10      /* SDRAM clock divisor shift */
  72 #define FMC_SDCR_WP_SHIFT       9       /* Write protection shift */
  73 #define FMC_SDCR_CAS_SHIFT      7       /* CAS latency shift */
  74 #define FMC_SDCR_NB_SHIFT       6       /* Number of banks shift */
  75 #define FMC_SDCR_MWID_SHIFT     4       /* Memory width shift */
  76 #define FMC_SDCR_NR_SHIFT       2       /* Number of row address bits shift */
  77 #define FMC_SDCR_NC_SHIFT       0       /* Number of col address bits shift */
  78
  79 /* Timings register SDTR */
  80 #define FMC_SDTR_TMRD_SHIFT     0       /* Load mode register to active */
  81 #define FMC_SDTR_TXSR_SHIFT     4       /* Exit self-refresh time */
  82 #define FMC_SDTR_TRAS_SHIFT     8       /* Self-refresh time */
  83 #define FMC_SDTR_TRC_SHIFT      12      /* Row cycle delay */
  84 #define FMC_SDTR_TWR_SHIFT      16      /* Recovery delay */
  85 #define FMC_SDTR_TRP_SHIFT      20      /* Row precharge delay */
  86 #define FMC_SDTR_TRCD_SHIFT     24      /* Row-to-column delay */
  87
  88 #define FMC_SDCMR_NRFS_SHIFT    5
  89
  90 #define FMC_SDCMR_MODE_NORMAL           0
  91 #define FMC_SDCMR_MODE_START_CLOCK      1
  92 #define FMC_SDCMR_MODE_PRECHARGE        2
  93 #define FMC_SDCMR_MODE_AUTOREFRESH      3
  94 #define FMC_SDCMR_MODE_WRITE_MODE       4
  95 #define FMC_SDCMR_MODE_SELFREFRESH      5
  96 #define FMC_SDCMR_MODE_POWERDOWN        6
  97
  98 #define FMC_SDCMR_BANK_1                BIT(4)
  99 #define FMC_SDCMR_BANK_2                BIT(3)
 100
 101 #define FMC_SDCMR_MODE_REGISTER_SHIFT   9
 102
 103 #define FMC_SDSR_BUSY                   BIT(5)
 104
 105 #define FMC_BUSY_WAIT(regs)     do { \
 106                 __asm__ __volatile__ ("dsb" : : : "memory"); \
 107                 while (regs->sdsr & FMC_SDSR_BUSY) \
 108                         ; \
 109         } while (0)
 110
 111 struct stm32_sdram_control {
 112         u8 no_columns;
 113         u8 no_rows;
 114         u8 memory_width;
 115         u8 no_banks;
 116         u8 cas_latency;
 117         u8 sdclk;
 118         u8 rd_burst;
 119         u8 rd_pipe_delay;
 120 };
 121
 122 struct stm32_sdram_timing {
 123         u8 tmrd;
 124         u8 txsr;
 125         u8 tras;
 126         u8 trc;
 127         u8 trp;
 128         u8 twr;
 129         u8 trcd;
 130 };
 131 enum stm32_fmc_bank {
 132         SDRAM_BANK1,
 133         SDRAM_BANK2,
 134         MAX_SDRAM_BANK,
 135 };
 136
 137 enum stm32_fmc_family {
 138         STM32F7_FMC,
 139         STM32H7_FMC,
 140 };
 141
 142 struct bank_params {
 143         struct stm32_sdram_control *sdram_control;
 144         struct stm32_sdram_timing *sdram_timing;
 145         u32 sdram_ref_count;
 146         enum stm32_fmc_bank target_bank;
 147 };
 148
 149 struct stm32_sdram_params {
 150         struct stm32_fmc_regs *base;
 151         u8 no_sdram_banks;
 152         struct bank_params bank_params[MAX_SDRAM_BANK];
 153         enum stm32_fmc_family family;
 154 };
 155
 156 #define SDRAM_MODE_BL_SHIFT     0
 157 #define SDRAM_MODE_CAS_SHIFT    4
 158 #define SDRAM_MODE_BL           0
 159
 160 int stm32_sdram_init(struct udevice *dev)
 161 {
 162         struct stm32_sdram_params *params = dev_get_platdata(dev);
 163         struct stm32_sdram_control *control;
 164         struct stm32_sdram_timing *timing;
 165         struct stm32_fmc_regs *regs = params->base;
 166         enum stm32_fmc_bank target_bank;
 167         u32 ctb; /* SDCMR register: Command Target Bank */
 168         u32 ref_count;
 169         u8 i;
 170
 171         /* disable the FMC controller */
 172         if (params->family == STM32H7_FMC)
 173                 clrbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
 174
 175         for (i = 0; i < params->no_sdram_banks; i++) {
 176                 control = params->bank_params[i].sdram_control;
 177                 timing = params->bank_params[i].sdram_timing;
 178                 target_bank = params->bank_params[i].target_bank;
 179                 ref_count = params->bank_params[i].sdram_ref_count;
 180
 181                 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
 182                         | control->cas_latency << FMC_SDCR_CAS_SHIFT
 183                         | control->no_banks << FMC_SDCR_NB_SHIFT
 184                         | control->memory_width << FMC_SDCR_MWID_SHIFT
 185                         | control->no_rows << FMC_SDCR_NR_SHIFT
 186                         | control->no_columns << FMC_SDCR_NC_SHIFT
 187                         | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
 188                         | control->rd_burst << FMC_SDCR_RBURST_SHIFT,
 189                         &regs->sdcr1);
 190
 191                 if (target_bank == SDRAM_BANK2)
 192                         writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
 193                                 | control->no_banks << FMC_SDCR_NB_SHIFT
 194                                 | control->memory_width << FMC_SDCR_MWID_SHIFT
 195                                 | control->no_rows << FMC_SDCR_NR_SHIFT
 196                                 | control->no_columns << FMC_SDCR_NC_SHIFT,
 197                                 &regs->sdcr2);
 198
 199                 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
 200                         | timing->trp << FMC_SDTR_TRP_SHIFT
 201                         | timing->twr << FMC_SDTR_TWR_SHIFT
 202                         | timing->trc << FMC_SDTR_TRC_SHIFT
 203                         | timing->tras << FMC_SDTR_TRAS_SHIFT
 204                         | timing->txsr << FMC_SDTR_TXSR_SHIFT
 205                         | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
 206                         &regs->sdtr1);
 207
 208                 if (target_bank == SDRAM_BANK2)
 209                         writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
 210                                 | timing->trp << FMC_SDTR_TRP_SHIFT
 211                                 | timing->twr << FMC_SDTR_TWR_SHIFT
 212                                 | timing->trc << FMC_SDTR_TRC_SHIFT
 213                                 | timing->tras << FMC_SDTR_TRAS_SHIFT
 214                                 | timing->txsr << FMC_SDTR_TXSR_SHIFT
 215                                 | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
 216                                 &regs->sdtr2);
 217
 218                 if (target_bank == SDRAM_BANK1)
 219                         ctb = FMC_SDCMR_BANK_1;
 220                 else
 221                         ctb = FMC_SDCMR_BANK_2;
 222
 223                 writel(ctb | FMC_SDCMR_MODE_START_CLOCK, &regs->sdcmr);
 224                 udelay(200);    /* 200 us delay, page 10, "Power-Up" */
 225                 FMC_BUSY_WAIT(regs);
 226
 227                 writel(ctb | FMC_SDCMR_MODE_PRECHARGE, &regs->sdcmr);
 228                 udelay(100);
 229                 FMC_BUSY_WAIT(regs);
 230
 231                 writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
 232                        &regs->sdcmr);
 233                 udelay(100);
 234                 FMC_BUSY_WAIT(regs);
 235
 236                 writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
 237                        | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
 238                        << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
 239                        &regs->sdcmr);
 240                 udelay(100);
 241                 FMC_BUSY_WAIT(regs);
 242
 243                 writel(ctb | FMC_SDCMR_MODE_NORMAL, &regs->sdcmr);
 244                 FMC_BUSY_WAIT(regs);
 245
 246                 /* Refresh timer */
 247                 writel(ref_count << 1, &regs->sdrtr);
 248         }
 249
 250         /* enable the FMC controller */
 251         if (params->family == STM32H7_FMC)
 252                 setbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
 253
 254         return 0;
 255 }
 256
 257 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
 258 {
 259         struct stm32_sdram_params *params = dev_get_platdata(dev);
 260         struct bank_params *bank_params;
 261         struct ofnode_phandle_args args;
 262         u32 *syscfg_base;
 263         u32 mem_remap;
 264         u32 swp_fmc;
 265         ofnode bank_node;
 266         char *bank_name;
 267         u8 bank = 0;
 268         int ret;
 269
 270         ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
 271                                                  &args);
 272         if (ret) {
 273                 dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
 274         } else {
 275                 syscfg_base = (u32 *)ofnode_get_addr(args.node);
 276
 277                 mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
 278                 if (mem_remap != NOT_FOUND) {
 279                         /* set memory mapping selection */
 280                         clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
 281                 } else {
 282                         dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
 283                 }
 284
 285                 swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
 286                 if (swp_fmc != NOT_FOUND) {
 287                         /* set fmc swapping selection */
 288                         clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
 289                 } else {
 290                         dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
 291                 }
 292
 293                 dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
 294         }
 295
 296         dev_for_each_subnode(bank_node, dev) {
 297                 /* extract the bank index from DT */
 298                 bank_name = (char *)ofnode_get_name(bank_node);
 299                 strsep(&bank_name, "@");
 300                 if (!bank_name) {
 301                         pr_err("missing sdram bank index");
 302                         return -EINVAL;
 303                 }
 304
 305                 bank_params = &params->bank_params[bank];
 306                 strict_strtoul(bank_name, 10,
 307                                (long unsigned int *)&bank_params->target_bank);
 308
 309                 if (bank_params->target_bank >= MAX_SDRAM_BANK) {
 310                         pr_err("Found bank %d , but only bank 0 and 1 are supported",
 311                               bank_params->target_bank);
 312                         return -EINVAL;
 313                 }
 314
 315                 debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
 316
 317                 params->bank_params[bank].sdram_control =
 318                         (struct stm32_sdram_control *)
 319                          ofnode_read_u8_array_ptr(bank_node,
 320                                                   "st,sdram-control",
 321                                                   sizeof(struct stm32_sdram_control));
 322
 323                 if (!params->bank_params[bank].sdram_control) {
 324                         pr_err("st,sdram-control not found for %s",
 325                               ofnode_get_name(bank_node));
 326                         return -EINVAL;
 327                 }
 328
 329
 330                 params->bank_params[bank].sdram_timing =
 331                         (struct stm32_sdram_timing *)
 332                          ofnode_read_u8_array_ptr(bank_node,
 333                                                   "st,sdram-timing",
 334                                                   sizeof(struct stm32_sdram_timing));
 335
 336                 if (!params->bank_params[bank].sdram_timing) {
 337                         pr_err("st,sdram-timing not found for %s",
 338                               ofnode_get_name(bank_node));
 339                         return -EINVAL;
 340                 }
 341
 342
 343                 bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
 344                                                 "st,sdram-refcount", 8196);
 345                 bank++;
 346         }
 347
 348         params->no_sdram_banks = bank;
 349         debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
 350
 351         return 0;
 352 }
 353
 354 static int stm32_fmc_probe(struct udevice *dev)
 355 {
 356         struct stm32_sdram_params *params = dev_get_platdata(dev);
 357         int ret;
 358         fdt_addr_t addr;
 359
 360         addr = dev_read_addr(dev);
 361         if (addr == FDT_ADDR_T_NONE)
 362                 return -EINVAL;
 363
 364         params->base = (struct stm32_fmc_regs *)addr;
 365         params->family = dev_get_driver_data(dev);
 366
 367 #ifdef CONFIG_CLK
 368         struct clk clk;
 369
 370         ret = clk_get_by_index(dev, 0, &clk);
 371         if (ret < 0)
 372                 return ret;
 373
 374         ret = clk_enable(&clk);
 375
 376         if (ret) {
 377                 dev_err(dev, "failed to enable clock\n");
 378                 return ret;
 379         }
 380 #endif
 381         ret = stm32_sdram_init(dev);
 382         if (ret)
 383                 return ret;
 384
 385         return 0;
 386 }
 387
 388 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
 389 {
 390         return 0;
 391 }
 392
 393 static struct ram_ops stm32_fmc_ops = {
 394         .get_info = stm32_fmc_get_info,
 395 };
 396
 397 static const struct udevice_id stm32_fmc_ids[] = {
 398         { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
 399         { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
 400         { }
 401 };
 402
 403 U_BOOT_DRIVER(stm32_fmc) = {
 404         .name = "stm32_fmc",
 405         .id = UCLASS_RAM,
 406         .of_match = stm32_fmc_ids,
 407         .ops = &stm32_fmc_ops,
 408         .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
 409         .probe = stm32_fmc_probe,
 410         .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),
 411 };