drivers/ram/rockchip/sdram_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2016-2017 Rockchip Inc.
   4  *
   5  * Adapted from coreboot.
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <ram.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/cru_rk3399.h>
  18 #include <asm/arch-rockchip/grf_rk3399.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include <asm/arch-rockchip/sdram_common.h>
  21 #include <asm/arch-rockchip/sdram_rk3399.h>
  22 #include <linux/err.h>
  23 #include <time.h>
  24
  25 #define PRESET_SGRF_HOLD(n)     ((0x1 << (6 + 16)) | ((n) << 6))
  26 #define PRESET_GPIO0_HOLD(n)    ((0x1 << (7 + 16)) | ((n) << 7))
  27 #define PRESET_GPIO1_HOLD(n)    ((0x1 << (8 + 16)) | ((n) << 8))
  28
  29 #define PHY_DRV_ODT_HI_Z        0x0
  30 #define PHY_DRV_ODT_240         0x1
  31 #define PHY_DRV_ODT_120         0x8
  32 #define PHY_DRV_ODT_80          0x9
  33 #define PHY_DRV_ODT_60          0xc
  34 #define PHY_DRV_ODT_48          0xd
  35 #define PHY_DRV_ODT_40          0xe
  36 #define PHY_DRV_ODT_34_3        0xf
  37
  38 #define PHY_BOOSTP_EN           0x1
  39 #define PHY_BOOSTN_EN           0x1
  40 #define PHY_SLEWP_EN            0x1
  41 #define PHY_SLEWN_EN            0x1
  42 #define PHY_RX_CM_INPUT         0x1
  43 #define CS0_MR22_VAL            0
  44 #define CS1_MR22_VAL            3
  45
  46 #define CRU_SFTRST_DDR_CTRL(ch, n)      ((0x1 << (8 + 16 + (ch) * 4)) | \
  47                                         ((n) << (8 + (ch) * 4)))
  48 #define CRU_SFTRST_DDR_PHY(ch, n)       ((0x1 << (9 + 16 + (ch) * 4)) | \
  49                                         ((n) << (9 + (ch) * 4)))
  50 struct chan_info {
  51         struct rk3399_ddr_pctl_regs *pctl;
  52         struct rk3399_ddr_pi_regs *pi;
  53         struct rk3399_ddr_publ_regs *publ;
  54         struct rk3399_msch_regs *msch;
  55 };
  56
  57 struct dram_info {
  58 #if defined(CONFIG_TPL_BUILD) || \
  59         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  60         u32 pwrup_srefresh_exit[2];
  61         struct chan_info chan[2];
  62         struct clk ddr_clk;
  63         struct rk3399_cru *cru;
  64         struct rk3399_grf_regs *grf;
  65         struct rk3399_pmucru *pmucru;
  66         struct rk3399_pmusgrf_regs *pmusgrf;
  67         struct rk3399_ddr_cic_regs *cic;
  68 #endif
  69         struct ram_info info;
  70         struct rk3399_pmugrf_regs *pmugrf;
  71 };
  72
  73 #if defined(CONFIG_TPL_BUILD) || \
  74         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  75
  76 struct rockchip_dmc_plat {
  77 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  78         struct dtd_rockchip_rk3399_dmc dtplat;
  79 #else
  80         struct rk3399_sdram_params sdram_params;
  81 #endif
  82         struct regmap *map;
  83 };
  84
  85 struct io_setting {
  86         u32 mhz;
  87         u32 mr5;
  88         /* dram side */
  89         u32 dq_odt;
  90         u32 ca_odt;
  91         u32 pdds;
  92         u32 dq_vref;
  93         u32 ca_vref;
  94         /* phy side */
  95         u32 rd_odt;
  96         u32 wr_dq_drv;
  97         u32 wr_ca_drv;
  98         u32 wr_ckcs_drv;
  99         u32 rd_odt_en;
 100         u32 rd_vref;
 101 } lpddr4_io_setting[] = {
 102         {
 103                 50 * MHz,
 104                 0,
 105                 /* dram side */
 106                 0,      /* dq_odt; */
 107                 0,      /* ca_odt; */
 108                 6,      /* pdds; */
 109                 0x72,   /* dq_vref; */
 110                 0x72,   /* ca_vref; */
 111                 /* phy side */
 112                 PHY_DRV_ODT_HI_Z,       /* rd_odt; */
 113                 PHY_DRV_ODT_40, /* wr_dq_drv; */
 114                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 115                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 116                 0,      /* rd_odt_en;*/
 117                 41,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 118         },
 119         {
 120                 600 * MHz,
 121                 0,
 122                 /* dram side */
 123                 1,      /* dq_odt; */
 124                 0,      /* ca_odt; */
 125                 6,      /* pdds; */
 126                 0x72,   /* dq_vref; */
 127                 0x72,   /* ca_vref; */
 128                 /* phy side */
 129                 PHY_DRV_ODT_HI_Z,       /* rd_odt; */
 130                 PHY_DRV_ODT_48, /* wr_dq_drv; */
 131                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 132                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 133                 0,      /* rd_odt_en; */
 134                 32,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 135         },
 136         {
 137                 800 * MHz,
 138                 0,
 139                 /* dram side */
 140                 1,      /* dq_odt; */
 141                 0,      /* ca_odt; */
 142                 1,      /* pdds; */
 143                 0x72,   /* dq_vref; */
 144                 0x72,   /* ca_vref; */
 145                 /* phy side */
 146                 PHY_DRV_ODT_40, /* rd_odt; */
 147                 PHY_DRV_ODT_48, /* wr_dq_drv; */
 148                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 149                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 150                 1,      /* rd_odt_en; */
 151                 17,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 152         },
 153         {
 154                 933 * MHz,
 155                 0,
 156                 /* dram side */
 157                 3,      /* dq_odt; */
 158                 0,      /* ca_odt; */
 159                 6,      /* pdds; */
 160                 0x59,   /* dq_vref; 32% */
 161                 0x72,   /* ca_vref; */
 162                 /* phy side */
 163                 PHY_DRV_ODT_HI_Z,       /* rd_odt; */
 164                 PHY_DRV_ODT_48, /* wr_dq_drv; */
 165                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 166                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 167                 0,      /* rd_odt_en; */
 168                 32,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 169         },
 170         {
 171                 1066 * MHz,
 172                 0,
 173                 /* dram side */
 174                 6,      /* dq_odt; */
 175                 0,      /* ca_odt; */
 176                 1,      /* pdds; */
 177                 0x10,   /* dq_vref; */
 178                 0x72,   /* ca_vref; */
 179                 /* phy side */
 180                 PHY_DRV_ODT_40, /* rd_odt; */
 181                 PHY_DRV_ODT_60, /* wr_dq_drv; */
 182                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 183                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 184                 1,      /* rd_odt_en; */
 185                 17,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 186         },
 187 };
 188
 189 /**
 190  * phy = 0, PHY boot freq
 191  * phy = 1, PHY index 0
 192  * phy = 2, PHY index 1
 193  */
 194 static struct io_setting *
 195 lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
 196 {
 197         struct io_setting *io = NULL;
 198         u32 n;
 199
 200         for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {
 201                 io = &lpddr4_io_setting[n];
 202
 203                 if (io->mr5 != 0) {
 204                         if (io->mhz >= params->base.ddr_freq &&
 205                             io->mr5 == mr5)
 206                                 break;
 207                 } else {
 208                         if (io->mhz >= params->base.ddr_freq)
 209                                 break;
 210                 }
 211         }
 212
 213         return io;
 214 }
 215
 216 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
 217 {
 218         return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
 219 }
 220
 221 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
 222 {
 223         int i;
 224
 225         for (i = 0; i < n / sizeof(u32); i++) {
 226                 writel(*src, dest);
 227                 src++;
 228                 dest++;
 229         }
 230 }
 231
 232 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
 233                             u32 phy)
 234 {
 235         channel &= 0x1;
 236         ctl &= 0x1;
 237         phy &= 0x1;
 238         writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
 239                                    CRU_SFTRST_DDR_PHY(channel, phy),
 240                                    &cru->softrst_con[4]);
 241 }
 242
 243 static void phy_pctrl_reset(struct rk3399_cru *cru,  u32 channel)
 244 {
 245         rkclk_ddr_reset(cru, channel, 1, 1);
 246         udelay(10);
 247
 248         rkclk_ddr_reset(cru, channel, 1, 0);
 249         udelay(10);
 250
 251         rkclk_ddr_reset(cru, channel, 0, 0);
 252         udelay(10);
 253 }
 254
 255 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
 256                                u32 freq)
 257 {
 258         u32 *denali_phy = ddr_publ_regs->denali_phy;
 259
 260         /* From IP spec, only freq small than 125 can enter dll bypass mode */
 261         if (freq <= 125) {
 262                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 263                 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 264                 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 265                 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 266                 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 267
 268                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 269                 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 270                 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 271                 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 272         } else {
 273                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 274                 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 275                 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 276                 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 277                 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 278
 279                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 280                 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 281                 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 282                 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 283         }
 284 }
 285
 286 static void set_memory_map(const struct chan_info *chan, u32 channel,
 287                            const struct rk3399_sdram_params *params)
 288 {
 289         const struct rk3399_sdram_channel *sdram_ch = &params->ch[channel];
 290         u32 *denali_ctl = chan->pctl->denali_ctl;
 291         u32 *denali_pi = chan->pi->denali_pi;
 292         u32 cs_map;
 293         u32 reduc;
 294         u32 row;
 295
 296         /* Get row number from ddrconfig setting */
 297         if (sdram_ch->cap_info.ddrconfig < 2 ||
 298             sdram_ch->cap_info.ddrconfig == 4)
 299                 row = 16;
 300         else if (sdram_ch->cap_info.ddrconfig == 3)
 301                 row = 14;
 302         else
 303                 row = 15;
 304
 305         cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
 306         reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
 307
 308         /* Set the dram configuration to ctrl */
 309         clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
 310         clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
 311                         ((3 - sdram_ch->cap_info.bk) << 16) |
 312                         ((16 - row) << 24));
 313
 314         clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
 315                         cs_map | (reduc << 16));
 316
 317         /* PI_199 PI_COL_DIFF:RW:0:4 */
 318         clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
 319
 320         /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
 321         clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
 322                         ((3 - sdram_ch->cap_info.bk) << 16) |
 323                         ((16 - row) << 24));
 324
 325         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 326                 if (cs_map == 1)
 327                         cs_map = 0x5;
 328                 else if (cs_map == 2)
 329                         cs_map = 0xa;
 330                 else
 331                         cs_map = 0xF;
 332         }
 333
 334         /* PI_41 PI_CS_MAP:RW:24:4 */
 335         clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
 336         if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
 337                 writel(0x2EC7FFFF, &denali_pi[34]);
 338 }
 339
 340 static int phy_io_config(const struct chan_info *chan,
 341                          const struct rk3399_sdram_params *params, u32 mr5)
 342 {
 343         u32 *denali_phy = chan->publ->denali_phy;
 344         u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
 345         u32 mode_sel;
 346         u32 reg_value;
 347         u32 drv_value, odt_value;
 348         u32 speed;
 349
 350         /* vref setting */
 351         if (params->base.dramtype == LPDDR4) {
 352                 struct io_setting *io = lpddr4_get_io_settings(params, mr5);
 353                 u32 rd_vref = io->rd_vref * 1000;
 354
 355                 if (rd_vref < 36700) {
 356                         /* MODE_LV[2:0] = LPDDR4 (Range 2)*/
 357                         vref_mode_dq = 0x7;
 358                         vref_value_dq = (rd_vref - 3300) / 521;
 359                 } else {
 360                         /* MODE_LV[2:0] = LPDDR4 (Range 1)*/
 361                         vref_mode_dq = 0x6;
 362                         vref_value_dq = (rd_vref - 15300) / 521;
 363                 }
 364                 vref_mode_ac = 0x6;
 365                 vref_value_ac = 0x1f;
 366                 mode_sel = 0x6;
 367         } else if (params->base.dramtype == LPDDR3) {
 368                 if (params->base.odt == 1) {
 369                         vref_mode_dq = 0x5;  /* LPDDR3 ODT */
 370                         drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
 371                         odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
 372                         if (drv_value == PHY_DRV_ODT_48) {
 373                                 switch (odt_value) {
 374                                 case PHY_DRV_ODT_240:
 375                                         vref_value_dq = 0x16;
 376                                         break;
 377                                 case PHY_DRV_ODT_120:
 378                                         vref_value_dq = 0x26;
 379                                         break;
 380                                 case PHY_DRV_ODT_60:
 381                                         vref_value_dq = 0x36;
 382                                         break;
 383                                 default:
 384                                         debug("Invalid ODT value.\n");
 385                                         return -EINVAL;
 386                                 }
 387                         } else if (drv_value == PHY_DRV_ODT_40) {
 388                                 switch (odt_value) {
 389                                 case PHY_DRV_ODT_240:
 390                                         vref_value_dq = 0x19;
 391                                         break;
 392                                 case PHY_DRV_ODT_120:
 393                                         vref_value_dq = 0x23;
 394                                         break;
 395                                 case PHY_DRV_ODT_60:
 396                                         vref_value_dq = 0x31;
 397                                         break;
 398                                 default:
 399                                         debug("Invalid ODT value.\n");
 400                                         return -EINVAL;
 401                                 }
 402                         } else if (drv_value == PHY_DRV_ODT_34_3) {
 403                                 switch (odt_value) {
 404                                 case PHY_DRV_ODT_240:
 405                                         vref_value_dq = 0x17;
 406                                         break;
 407                                 case PHY_DRV_ODT_120:
 408                                         vref_value_dq = 0x20;
 409                                         break;
 410                                 case PHY_DRV_ODT_60:
 411                                         vref_value_dq = 0x2e;
 412                                         break;
 413                                 default:
 414                                         debug("Invalid ODT value.\n");
 415                                         return -EINVAL;
 416                                 }
 417                         } else {
 418                                 debug("Invalid DRV value.\n");
 419                                 return -EINVAL;
 420                         }
 421                 } else {
 422                         vref_mode_dq = 0x2;  /* LPDDR3 */
 423                         vref_value_dq = 0x1f;
 424                 }
 425                 vref_mode_ac = 0x2;
 426                 vref_value_ac = 0x1f;
 427                 mode_sel = 0x0;
 428         } else if (params->base.dramtype == DDR3) {
 429                 /* DDR3L */
 430                 vref_mode_dq = 0x1;
 431                 vref_value_dq = 0x1f;
 432                 vref_mode_ac = 0x1;
 433                 vref_value_ac = 0x1f;
 434                 mode_sel = 0x1;
 435         } else {
 436                 debug("Unknown DRAM type.\n");
 437                 return -EINVAL;
 438         }
 439
 440         reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
 441
 442         /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
 443         clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
 444         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
 445         clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
 446         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
 447         clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
 448         /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
 449         clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
 450
 451         reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
 452
 453         /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
 454         clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 455
 456         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 457         clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
 458         /* PHY_926 PHY_PAD_DATA_DRIVE */
 459         clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
 460         /* PHY_927 PHY_PAD_DQS_DRIVE */
 461         clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
 462         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 463         clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
 464         /* PHY_929 PHY_PAD_CLK_DRIVE */
 465         clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
 466         /* PHY_935 PHY_PAD_CKE_DRIVE */
 467         clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
 468         /* PHY_937 PHY_PAD_RST_DRIVE */
 469         clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
 470         /* PHY_939 PHY_PAD_CS_DRIVE */
 471         clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 472
 473         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 474                 /* BOOSTP_EN & BOOSTN_EN */
 475                 reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
 476                 /* PHY_925 PHY_PAD_FDBK_DRIVE2 */
 477                 clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
 478                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 479                 clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
 480                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 481                 clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
 482                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 483                 clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
 484                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 485                 clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
 486                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 487                 clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
 488                 /* PHY_937 PHY_PAD_RST_DRIVE */
 489                 clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
 490                 /* PHY_939 PHY_PAD_CS_DRIVE */
 491                 clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
 492
 493                 /* SLEWP_EN & SLEWN_EN */
 494                 reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
 495                 /* PHY_924 PHY_PAD_FDBK_DRIVE */
 496                 clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
 497                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 498                 clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
 499                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 500                 clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
 501                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 502                 clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
 503                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 504                 clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
 505                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 506                 clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
 507                 /* PHY_937 PHY_PAD_RST_DRIVE */
 508                 clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
 509                 /* PHY_939 PHY_PAD_CS_DRIVE */
 510                 clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
 511         }
 512
 513         /* speed setting */
 514         if (params->base.ddr_freq < 400)
 515                 speed = 0x0;
 516         else if (params->base.ddr_freq < 800)
 517                 speed = 0x1;
 518         else if (params->base.ddr_freq < 1200)
 519                 speed = 0x2;
 520         else
 521                 speed = 0x3;
 522
 523         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 524         clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
 525         /* PHY_926 PHY_PAD_DATA_DRIVE */
 526         clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
 527         /* PHY_927 PHY_PAD_DQS_DRIVE */
 528         clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
 529         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 530         clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
 531         /* PHY_929 PHY_PAD_CLK_DRIVE */
 532         clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
 533         /* PHY_935 PHY_PAD_CKE_DRIVE */
 534         clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
 535         /* PHY_937 PHY_PAD_RST_DRIVE */
 536         clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
 537         /* PHY_939 PHY_PAD_CS_DRIVE */
 538         clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 539
 540         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 541                 /* RX_CM_INPUT */
 542                 reg_value = PHY_RX_CM_INPUT;
 543                 /* PHY_924 PHY_PAD_FDBK_DRIVE */
 544                 clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
 545                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 546                 clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
 547                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 548                 clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
 549                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 550                 clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
 551                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 552                 clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
 553                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 554                 clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
 555                 /* PHY_937 PHY_PAD_RST_DRIVE */
 556                 clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
 557                 /* PHY_939 PHY_PAD_CS_DRIVE */
 558                 clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
 559         }
 560
 561         return 0;
 562 }
 563
 564 static void set_ds_odt(const struct chan_info *chan,
 565                        const struct rk3399_sdram_params *params, u32 mr5)
 566 {
 567         u32 *denali_phy = chan->publ->denali_phy;
 568         u32 *denali_ctl = chan->pctl->denali_ctl;
 569         u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 570         u32 tsel_idle_select_p, tsel_rd_select_p;
 571         u32 tsel_idle_select_n, tsel_rd_select_n;
 572         u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
 573         u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
 574         u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
 575         struct io_setting *io = NULL;
 576         u32 soc_odt = 0;
 577         u32 reg_value;
 578
 579         if (params->base.dramtype == LPDDR4) {
 580                 io = lpddr4_get_io_settings(params, mr5);
 581
 582                 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
 583                 tsel_rd_select_n = io->rd_odt;
 584
 585                 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 586                 tsel_idle_select_n = PHY_DRV_ODT_240;
 587
 588                 tsel_wr_select_dq_p = io->wr_dq_drv;
 589                 tsel_wr_select_dq_n = PHY_DRV_ODT_40;
 590
 591                 tsel_wr_select_ca_p = io->wr_ca_drv;
 592                 tsel_wr_select_ca_n = PHY_DRV_ODT_40;
 593
 594                 tsel_ckcs_select_p = io->wr_ckcs_drv;
 595                 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 596                 switch (tsel_rd_select_n) {
 597                 case PHY_DRV_ODT_240:
 598                         soc_odt = 1;
 599                         break;
 600                 case PHY_DRV_ODT_120:
 601                         soc_odt = 2;
 602                         break;
 603                 case PHY_DRV_ODT_80:
 604                         soc_odt = 3;
 605                         break;
 606                 case PHY_DRV_ODT_60:
 607                         soc_odt = 4;
 608                         break;
 609                 case PHY_DRV_ODT_48:
 610                         soc_odt = 5;
 611                         break;
 612                 case PHY_DRV_ODT_40:
 613                         soc_odt = 6;
 614                         break;
 615                 case PHY_DRV_ODT_34_3:
 616                         soc_odt = 6;
 617                         printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n",
 618                                __func__);
 619                         break;
 620                 case PHY_DRV_ODT_HI_Z:
 621                 default:
 622                         soc_odt = 0;
 623                         break;
 624                 }
 625         } else if (params->base.dramtype == LPDDR3) {
 626                 tsel_rd_select_p = PHY_DRV_ODT_240;
 627                 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
 628
 629                 tsel_idle_select_p = PHY_DRV_ODT_240;
 630                 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 631
 632                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 633                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 634
 635                 tsel_wr_select_ca_p = PHY_DRV_ODT_48;
 636                 tsel_wr_select_ca_n = PHY_DRV_ODT_48;
 637
 638                 tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
 639                 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 640         } else {
 641                 tsel_rd_select_p = PHY_DRV_ODT_240;
 642                 tsel_rd_select_n = PHY_DRV_ODT_240;
 643
 644                 tsel_idle_select_p = PHY_DRV_ODT_240;
 645                 tsel_idle_select_n = PHY_DRV_ODT_240;
 646
 647                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 648                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 649
 650                 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
 651                 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
 652
 653                 tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
 654                 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 655         }
 656
 657         if (params->base.odt == 1) {
 658                 tsel_rd_en = 1;
 659
 660                 if (params->base.dramtype == LPDDR4)
 661                         tsel_rd_en = io->rd_odt_en;
 662         } else {
 663                 tsel_rd_en = 0;
 664         }
 665
 666         tsel_wr_en = 0;
 667         tsel_idle_en = 0;
 668
 669         /* F0_0 */
 670         clrsetbits_le32(&denali_ctl[145], 0xFF << 16,
 671                         (soc_odt | (CS0_MR22_VAL << 3)) << 16);
 672         /* F2_0, F1_0 */
 673         clrsetbits_le32(&denali_ctl[146], 0xFF00FF,
 674                         ((soc_odt | (CS0_MR22_VAL << 3)) << 16) |
 675                         (soc_odt | (CS0_MR22_VAL << 3)));
 676         /* F0_1 */
 677         clrsetbits_le32(&denali_ctl[159], 0xFF << 16,
 678                         (soc_odt | (CS1_MR22_VAL << 3)) << 16);
 679         /* F2_1, F1_1 */
 680         clrsetbits_le32(&denali_ctl[160], 0xFF00FF,
 681                         ((soc_odt | (CS1_MR22_VAL << 3)) << 16) |
 682                         (soc_odt | (CS1_MR22_VAL << 3)));
 683
 684         /*
 685          * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
 686          * sets termination values for read/idle cycles and drive strength
 687          * for write cycles for DQ/DM
 688          */
 689         reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
 690                     (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
 691                     (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
 692         clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
 693         clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
 694         clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
 695         clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
 696
 697         /*
 698          * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
 699          * sets termination values for read/idle cycles and drive strength
 700          * for write cycles for DQS
 701          */
 702         clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
 703         clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
 704         clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
 705         clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
 706
 707         /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 708         reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
 709         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 710                 /* LPDDR4 these register read always return 0, so
 711                  * can not use clrsetbits_le32(), need to write32
 712                  */
 713                 writel((0x300 << 8) | reg_value, &denali_phy[544]);
 714                 writel((0x300 << 8) | reg_value, &denali_phy[672]);
 715                 writel((0x300 << 8) | reg_value, &denali_phy[800]);
 716         } else {
 717                 clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
 718                 clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
 719                 clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
 720         }
 721
 722         /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 723         clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 724
 725         /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
 726         clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 727
 728         /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
 729         clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 730
 731         /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
 732         clrsetbits_le32(&denali_phy[939], 0xff,
 733                         tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
 734
 735         /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
 736         clrsetbits_le32(&denali_phy[929], 0xff,
 737                         tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
 738
 739         /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
 740         clrsetbits_le32(&denali_phy[924], 0xff,
 741                         tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
 742         clrsetbits_le32(&denali_phy[925], 0xff,
 743                         tsel_rd_select_n | (tsel_rd_select_p << 4));
 744
 745         /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
 746         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 747                 << 16;
 748         clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
 749         clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
 750         clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
 751         clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
 752
 753         /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
 754         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 755                 << 24;
 756         clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
 757         clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
 758         clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
 759         clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
 760
 761         /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
 762         reg_value = tsel_wr_en << 8;
 763         clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
 764         clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
 765         clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
 766
 767         /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
 768         reg_value = tsel_wr_en << 17;
 769         clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
 770         /*
 771          * pad_rst/cke/cs/clk_term tsel 1bits
 772          * DENALI_PHY_938/936/940/934 offset_17
 773          */
 774         clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
 775         clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
 776         clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
 777         clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
 778
 779         /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 780         clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 781
 782         phy_io_config(chan, params, mr5);
 783 }
 784
 785 static void pctl_start(struct dram_info *dram, u8 channel)
 786 {
 787         const struct chan_info *chan = &dram->chan[channel];
 788         u32 *denali_ctl = chan->pctl->denali_ctl;
 789         u32 *denali_phy = chan->publ->denali_phy;
 790         u32 *ddrc0_con = get_ddrc0_con(dram, channel);
 791         u32 count = 0;
 792         u32 byte, tmp;
 793
 794         writel(0x01000000, &ddrc0_con);
 795
 796         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 797
 798         while (!(readl(&denali_ctl[203]) & (1 << 3))) {
 799                 if (count > 1000) {
 800                         printf("%s: Failed to init pctl for channel %d\n",
 801                                __func__, channel);
 802                         while (1)
 803                                 ;
 804                 }
 805
 806                 udelay(1);
 807                 count++;
 808         }
 809
 810         writel(0x01000100, &ddrc0_con);
 811
 812         for (byte = 0; byte < 4; byte++) {
 813                 tmp = 0x820;
 814                 writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]);
 815                 writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]);
 816                 writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]);
 817                 writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]);
 818                 writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]);
 819
 820                 clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp);
 821         }
 822
 823         clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
 824                         dram->pwrup_srefresh_exit[channel]);
 825 }
 826
 827 static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 828                     u32 channel, struct rk3399_sdram_params *params)
 829 {
 830         u32 *denali_ctl = chan->pctl->denali_ctl;
 831         u32 *denali_pi = chan->pi->denali_pi;
 832         u32 *denali_phy = chan->publ->denali_phy;
 833         const u32 *params_ctl = params->pctl_regs.denali_ctl;
 834         const u32 *params_phy = params->phy_regs.denali_phy;
 835         u32 tmp, tmp1, tmp2;
 836
 837         /*
 838          * work around controller bug:
 839          * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
 840          */
 841         copy_to_reg(&denali_ctl[1], &params_ctl[1],
 842                     sizeof(struct rk3399_ddr_pctl_regs) - 4);
 843         writel(params_ctl[0], &denali_ctl[0]);
 844
 845         /*
 846          * two channel init at the same time, then ZQ Cal Start
 847          * at the same time, it will use the same RZQ, but cannot
 848          * start at the same time.
 849          *
 850          * So, increase tINIT3 for channel 1, will avoid two
 851          * channel ZQ Cal Start at the same time
 852          */
 853         if (params->base.dramtype == LPDDR4 && channel == 1) {
 854                 tmp = ((params->base.ddr_freq * MHz + 999) / 1000);
 855                 tmp1 = readl(&denali_ctl[14]);
 856                 writel(tmp + tmp1, &denali_ctl[14]);
 857         }
 858
 859         copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
 860                     sizeof(struct rk3399_ddr_pi_regs));
 861
 862         /* rank count need to set for init */
 863         set_memory_map(chan, channel, params);
 864
 865         writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
 866         writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
 867         writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
 868
 869         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 870                 writel(params->phy_regs.denali_phy[898], &denali_phy[898]);
 871                 writel(params->phy_regs.denali_phy[919], &denali_phy[919]);
 872         }
 873
 874         dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
 875                                              PWRUP_SREFRESH_EXIT;
 876         clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
 877
 878         /* PHY_DLL_RST_EN */
 879         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
 880
 881         setbits_le32(&denali_pi[0], START);
 882         setbits_le32(&denali_ctl[0], START);
 883
 884         /**
 885          * LPDDR4 use PLL bypass mode for init
 886          * not need to wait for the PLL to lock
 887          */
 888         if (params->base.dramtype != LPDDR4) {
 889                 /* Waiting for phy DLL lock */
 890                 while (1) {
 891                         tmp = readl(&denali_phy[920]);
 892                         tmp1 = readl(&denali_phy[921]);
 893                         tmp2 = readl(&denali_phy[922]);
 894                         if ((((tmp >> 16) & 0x1) == 0x1) &&
 895                             (((tmp1 >> 16) & 0x1) == 0x1) &&
 896                             (((tmp1 >> 0) & 0x1) == 0x1) &&
 897                             (((tmp2 >> 0) & 0x1) == 0x1))
 898                                 break;
 899                 }
 900         }
 901
 902         copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
 903         copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
 904         copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
 905         copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
 906         copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
 907         copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
 908         copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
 909         copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
 910         set_ds_odt(chan, params, 0);
 911
 912         /*
 913          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
 914          * dqs_tsel_wr_end[7:4] add Half cycle
 915          */
 916         tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
 917         clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
 918         tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
 919         clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
 920         tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
 921         clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
 922         tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
 923         clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
 924
 925         /*
 926          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
 927          * dq_tsel_wr_end[7:4] add Half cycle
 928          */
 929         tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
 930         clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
 931         tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
 932         clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
 933         tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
 934         clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
 935         tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
 936         clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 937
 938         return 0;
 939 }
 940
 941 static void select_per_cs_training_index(const struct chan_info *chan,
 942                                          u32 rank)
 943 {
 944         u32 *denali_phy = chan->publ->denali_phy;
 945
 946         /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
 947         if ((readl(&denali_phy[84]) >> 16) & 1) {
 948                 /*
 949                  * PHY_8/136/264/392
 950                  * phy_per_cs_training_index_X 1bit offset_24
 951                  */
 952                 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
 953                 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
 954                 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
 955                 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
 956         }
 957 }
 958
 959 static void override_write_leveling_value(const struct chan_info *chan)
 960 {
 961         u32 *denali_ctl = chan->pctl->denali_ctl;
 962         u32 *denali_phy = chan->publ->denali_phy;
 963         u32 byte;
 964
 965         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 966         setbits_le32(&denali_phy[896], 1);
 967
 968         /*
 969          * PHY_8/136/264/392
 970          * phy_per_cs_training_multicast_en_X 1bit offset_16
 971          */
 972         clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
 973         clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
 974         clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
 975         clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
 976
 977         for (byte = 0; byte < 4; byte++)
 978                 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
 979                                 0x200 << 16);
 980
 981         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 982         clrbits_le32(&denali_phy[896], 1);
 983
 984         /* CTL_200 ctrlupd_req 1bit offset_8 */
 985         clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
 986 }
 987
 988 static int data_training_ca(const struct chan_info *chan, u32 channel,
 989                             const struct rk3399_sdram_params *params)
 990 {
 991         u32 *denali_pi = chan->pi->denali_pi;
 992         u32 *denali_phy = chan->publ->denali_phy;
 993         u32 i, tmp;
 994         u32 obs_0, obs_1, obs_2, obs_err = 0;
 995         u32 rank = params->ch[channel].cap_info.rank;
 996         u32 rank_mask;
 997
 998         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 999         writel(0x00003f7c, (&denali_pi[175]));
1000
1001         if (params->base.dramtype == LPDDR4)
1002                 rank_mask = (rank == 1) ? 0x5 : 0xf;
1003         else
1004                 rank_mask = (rank == 1) ? 0x1 : 0x3;
1005
1006         for (i = 0; i < 4; i++) {
1007                 if (!(rank_mask & (1 << i)))
1008                         continue;
1009
1010                 select_per_cs_training_index(chan, i);
1011
1012                 /* PI_100 PI_CALVL_EN:RW:8:2 */
1013                 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
1014
1015                 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
1016                 clrsetbits_le32(&denali_pi[92],
1017                                 (0x1 << 16) | (0x3 << 24),
1018                                 (0x1 << 16) | (i << 24));
1019
1020                 /* Waiting for training complete */
1021                 while (1) {
1022                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1023                         tmp = readl(&denali_pi[174]) >> 8;
1024                         /*
1025                          * check status obs
1026                          * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
1027                          */
1028                         obs_0 = readl(&denali_phy[532]);
1029                         obs_1 = readl(&denali_phy[660]);
1030                         obs_2 = readl(&denali_phy[788]);
1031                         if (((obs_0 >> 30) & 0x3) ||
1032                             ((obs_1 >> 30) & 0x3) ||
1033                             ((obs_2 >> 30) & 0x3))
1034                                 obs_err = 1;
1035                         if ((((tmp >> 11) & 0x1) == 0x1) &&
1036                             (((tmp >> 13) & 0x1) == 0x1) &&
1037                             (((tmp >> 5) & 0x1) == 0x0) &&
1038                             obs_err == 0)
1039                                 break;
1040                         else if ((((tmp >> 5) & 0x1) == 0x1) ||
1041                                  (obs_err == 1))
1042                                 return -EIO;
1043                 }
1044
1045                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1046                 writel(0x00003f7c, (&denali_pi[175]));
1047         }
1048
1049         clrbits_le32(&denali_pi[100], 0x3 << 8);
1050
1051         return 0;
1052 }
1053
1054 static int data_training_wl(const struct chan_info *chan, u32 channel,
1055                             const struct rk3399_sdram_params *params)
1056 {
1057         u32 *denali_pi = chan->pi->denali_pi;
1058         u32 *denali_phy = chan->publ->denali_phy;
1059         u32 i, tmp;
1060         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
1061         u32 rank = params->ch[channel].cap_info.rank;
1062
1063         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1064         writel(0x00003f7c, (&denali_pi[175]));
1065
1066         for (i = 0; i < rank; i++) {
1067                 select_per_cs_training_index(chan, i);
1068
1069                 /* PI_60 PI_WRLVL_EN:RW:8:2 */
1070                 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
1071
1072                 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
1073                 clrsetbits_le32(&denali_pi[59],
1074                                 (0x1 << 8) | (0x3 << 16),
1075                                 (0x1 << 8) | (i << 16));
1076
1077                 /* Waiting for training complete */
1078                 while (1) {
1079                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1080                         tmp = readl(&denali_pi[174]) >> 8;
1081
1082                         /*
1083                          * check status obs, if error maybe can not
1084                          * get leveling done PHY_40/168/296/424
1085                          * phy_wrlvl_status_obs_X:0:13
1086                          */
1087                         obs_0 = readl(&denali_phy[40]);
1088                         obs_1 = readl(&denali_phy[168]);
1089                         obs_2 = readl(&denali_phy[296]);
1090                         obs_3 = readl(&denali_phy[424]);
1091                         if (((obs_0 >> 12) & 0x1) ||
1092                             ((obs_1 >> 12) & 0x1) ||
1093                             ((obs_2 >> 12) & 0x1) ||
1094                             ((obs_3 >> 12) & 0x1))
1095                                 obs_err = 1;
1096                         if ((((tmp >> 10) & 0x1) == 0x1) &&
1097                             (((tmp >> 13) & 0x1) == 0x1) &&
1098                             (((tmp >> 4) & 0x1) == 0x0) &&
1099                             obs_err == 0)
1100                                 break;
1101                         else if ((((tmp >> 4) & 0x1) == 0x1) ||
1102                                  (obs_err == 1))
1103                                 return -EIO;
1104                 }
1105
1106                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1107                 writel(0x00003f7c, (&denali_pi[175]));
1108         }
1109
1110         override_write_leveling_value(chan);
1111         clrbits_le32(&denali_pi[60], 0x3 << 8);
1112
1113         return 0;
1114 }
1115
1116 static int data_training_rg(const struct chan_info *chan, u32 channel,
1117                             const struct rk3399_sdram_params *params)
1118 {
1119         u32 *denali_pi = chan->pi->denali_pi;
1120         u32 *denali_phy = chan->publ->denali_phy;
1121         u32 i, tmp;
1122         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
1123         u32 rank = params->ch[channel].cap_info.rank;
1124
1125         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1126         writel(0x00003f7c, (&denali_pi[175]));
1127
1128         for (i = 0; i < rank; i++) {
1129                 select_per_cs_training_index(chan, i);
1130
1131                 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
1132                 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
1133
1134                 /*
1135                  * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
1136                  * PI_RDLVL_CS:RW:24:2
1137                  */
1138                 clrsetbits_le32(&denali_pi[74],
1139                                 (0x1 << 16) | (0x3 << 24),
1140                                 (0x1 << 16) | (i << 24));
1141
1142                 /* Waiting for training complete */
1143                 while (1) {
1144                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1145                         tmp = readl(&denali_pi[174]) >> 8;
1146
1147                         /*
1148                          * check status obs
1149                          * PHY_43/171/299/427
1150                          *     PHY_GTLVL_STATUS_OBS_x:16:8
1151                          */
1152                         obs_0 = readl(&denali_phy[43]);
1153                         obs_1 = readl(&denali_phy[171]);
1154                         obs_2 = readl(&denali_phy[299]);
1155                         obs_3 = readl(&denali_phy[427]);
1156                         if (((obs_0 >> (16 + 6)) & 0x3) ||
1157                             ((obs_1 >> (16 + 6)) & 0x3) ||
1158                             ((obs_2 >> (16 + 6)) & 0x3) ||
1159                             ((obs_3 >> (16 + 6)) & 0x3))
1160                                 obs_err = 1;
1161                         if ((((tmp >> 9) & 0x1) == 0x1) &&
1162                             (((tmp >> 13) & 0x1) == 0x1) &&
1163                             (((tmp >> 3) & 0x1) == 0x0) &&
1164                             obs_err == 0)
1165                                 break;
1166                         else if ((((tmp >> 3) & 0x1) == 0x1) ||
1167                                  (obs_err == 1))
1168                                 return -EIO;
1169                 }
1170
1171                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1172                 writel(0x00003f7c, (&denali_pi[175]));
1173         }
1174
1175         clrbits_le32(&denali_pi[80], 0x3 << 24);
1176
1177         return 0;
1178 }
1179
1180 static int data_training_rl(const struct chan_info *chan, u32 channel,
1181                             const struct rk3399_sdram_params *params)
1182 {
1183         u32 *denali_pi = chan->pi->denali_pi;
1184         u32 i, tmp;
1185         u32 rank = params->ch[channel].cap_info.rank;
1186
1187         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1188         writel(0x00003f7c, (&denali_pi[175]));
1189
1190         for (i = 0; i < rank; i++) {
1191                 select_per_cs_training_index(chan, i);
1192
1193                 /* PI_80 PI_RDLVL_EN:RW:16:2 */
1194                 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
1195
1196                 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
1197                 clrsetbits_le32(&denali_pi[74],
1198                                 (0x1 << 8) | (0x3 << 24),
1199                                 (0x1 << 8) | (i << 24));
1200
1201                 /* Waiting for training complete */
1202                 while (1) {
1203                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1204                         tmp = readl(&denali_pi[174]) >> 8;
1205
1206                         /*
1207                          * make sure status obs not report error bit
1208                          * PHY_46/174/302/430
1209                          *     phy_rdlvl_status_obs_X:16:8
1210                          */
1211                         if ((((tmp >> 8) & 0x1) == 0x1) &&
1212                             (((tmp >> 13) & 0x1) == 0x1) &&
1213                             (((tmp >> 2) & 0x1) == 0x0))
1214                                 break;
1215                         else if (((tmp >> 2) & 0x1) == 0x1)
1216                                 return -EIO;
1217                 }
1218
1219                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1220                 writel(0x00003f7c, (&denali_pi[175]));
1221         }
1222
1223         clrbits_le32(&denali_pi[80], 0x3 << 16);
1224
1225         return 0;
1226 }
1227
1228 static int data_training_wdql(const struct chan_info *chan, u32 channel,
1229                               const struct rk3399_sdram_params *params)
1230 {
1231         u32 *denali_pi = chan->pi->denali_pi;
1232         u32 i, tmp;
1233         u32 rank = params->ch[channel].cap_info.rank;
1234         u32 rank_mask;
1235
1236         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1237         writel(0x00003f7c, (&denali_pi[175]));
1238
1239         if (params->base.dramtype == LPDDR4)
1240                 rank_mask = (rank == 1) ? 0x5 : 0xf;
1241         else
1242                 rank_mask = (rank == 1) ? 0x1 : 0x3;
1243
1244         for (i = 0; i < 4; i++) {
1245                 if (!(rank_mask & (1 << i)))
1246                         continue;
1247
1248                 select_per_cs_training_index(chan, i);
1249
1250                 /*
1251                  * disable PI_WDQLVL_VREF_EN before wdq leveling?
1252                  * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
1253                  */
1254                 clrbits_le32(&denali_pi[181], 0x1 << 8);
1255
1256                 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
1257                 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
1258
1259                 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
1260                 clrsetbits_le32(&denali_pi[121],
1261                                 (0x1 << 8) | (0x3 << 16),
1262                                 (0x1 << 8) | (i << 16));
1263
1264                 /* Waiting for training complete */
1265                 while (1) {
1266                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1267                         tmp = readl(&denali_pi[174]) >> 8;
1268                         if ((((tmp >> 12) & 0x1) == 0x1) &&
1269                             (((tmp >> 13) & 0x1) == 0x1) &&
1270                             (((tmp >> 6) & 0x1) == 0x0))
1271                                 break;
1272                         else if (((tmp >> 6) & 0x1) == 0x1)
1273                                 return -EIO;
1274                 }
1275
1276                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1277                 writel(0x00003f7c, (&denali_pi[175]));
1278         }
1279
1280         clrbits_le32(&denali_pi[124], 0x3 << 16);
1281
1282         return 0;
1283 }
1284
1285 static int data_training(const struct chan_info *chan, u32 channel,
1286                          const struct rk3399_sdram_params *params,
1287                          u32 training_flag)
1288 {
1289         u32 *denali_phy = chan->publ->denali_phy;
1290         int ret;
1291
1292         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
1293         setbits_le32(&denali_phy[927], (1 << 22));
1294
1295         if (training_flag == PI_FULL_TRAINING) {
1296                 if (params->base.dramtype == LPDDR4) {
1297                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
1298                                         PI_READ_GATE_TRAINING |
1299                                         PI_READ_LEVELING | PI_WDQ_LEVELING;
1300                 } else if (params->base.dramtype == LPDDR3) {
1301                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
1302                                         PI_READ_GATE_TRAINING;
1303                 } else if (params->base.dramtype == DDR3) {
1304                         training_flag = PI_WRITE_LEVELING |
1305                                         PI_READ_GATE_TRAINING |
1306                                         PI_READ_LEVELING;
1307                 }
1308         }
1309
1310         /* ca training(LPDDR4,LPDDR3 support) */
1311         if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
1312                 ret = data_training_ca(chan, channel, params);
1313                 if (ret < 0) {
1314                         debug("%s: data training ca failed\n", __func__);
1315                         return ret;
1316                 }
1317         }
1318
1319         /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
1320         if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
1321                 ret = data_training_wl(chan, channel, params);
1322                 if (ret < 0) {
1323                         debug("%s: data training wl failed\n", __func__);
1324                         return ret;
1325                 }
1326         }
1327
1328         /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
1329         if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
1330                 ret = data_training_rg(chan, channel, params);
1331                 if (ret < 0) {
1332                         debug("%s: data training rg failed\n", __func__);
1333                         return ret;
1334                 }
1335         }
1336
1337         /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
1338         if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
1339                 ret = data_training_rl(chan, channel, params);
1340                 if (ret < 0) {
1341                         debug("%s: data training rl failed\n", __func__);
1342                         return ret;
1343                 }
1344         }
1345
1346         /* wdq leveling(LPDDR4 support) */
1347         if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
1348                 ret = data_training_wdql(chan, channel, params);
1349                 if (ret < 0) {
1350                         debug("%s: data training wdql failed\n", __func__);
1351                         return ret;
1352                 }
1353         }
1354
1355         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
1356         clrbits_le32(&denali_phy[927], (1 << 22));
1357
1358         return 0;
1359 }
1360
1361 static void set_ddrconfig(const struct chan_info *chan,
1362                           const struct rk3399_sdram_params *params,
1363                           unsigned char channel, u32 ddrconfig)
1364 {
1365         /* only need to set ddrconfig */
1366         struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
1367         unsigned int cs0_cap = 0;
1368         unsigned int cs1_cap = 0;
1369
1370         cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
1371                         + params->ch[channel].cap_info.col
1372                         + params->ch[channel].cap_info.bk
1373                         + params->ch[channel].cap_info.bw - 20));
1374         if (params->ch[channel].cap_info.rank > 1)
1375                 cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
1376                                 - params->ch[channel].cap_info.cs1_row);
1377         if (params->ch[channel].cap_info.row_3_4) {
1378                 cs0_cap = cs0_cap * 3 / 4;
1379                 cs1_cap = cs1_cap * 3 / 4;
1380         }
1381
1382         writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
1383         writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
1384                &ddr_msch_regs->ddrsize);
1385 }
1386
1387 static void dram_all_config(struct dram_info *dram,
1388                             const struct rk3399_sdram_params *params)
1389 {
1390         u32 sys_reg2 = 0;
1391         u32 sys_reg3 = 0;
1392         unsigned int channel, idx;
1393
1394         sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
1395         sys_reg2 |= SYS_REG_ENC_NUM_CH(params->base.num_channels);
1396
1397         for (channel = 0, idx = 0;
1398              (idx < params->base.num_channels) && (channel < 2);
1399              channel++) {
1400                 const struct rk3399_sdram_channel *info = &params->ch[channel];
1401                 struct rk3399_msch_regs *ddr_msch_regs;
1402                 const struct rk3399_msch_timings *noc_timing;
1403
1404                 if (params->ch[channel].cap_info.col == 0)
1405                         continue;
1406                 idx++;
1407                 sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
1408                 sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
1409                 sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
1410                 sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
1411                 sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
1412                 sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
1413                 sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
1414                 SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
1415                 if (info->cap_info.cs1_row)
1416                         SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
1417                                             sys_reg3, channel);
1418                 sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
1419                 sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
1420
1421                 ddr_msch_regs = dram->chan[channel].msch;
1422                 noc_timing = &params->ch[channel].noc_timings;
1423                 writel(noc_timing->ddrtiminga0,
1424                        &ddr_msch_regs->ddrtiminga0);
1425                 writel(noc_timing->ddrtimingb0,
1426                        &ddr_msch_regs->ddrtimingb0);
1427                 writel(noc_timing->ddrtimingc0.d32,
1428                        &ddr_msch_regs->ddrtimingc0);
1429                 writel(noc_timing->devtodev0,
1430                        &ddr_msch_regs->devtodev0);
1431                 writel(noc_timing->ddrmode.d32,
1432                        &ddr_msch_regs->ddrmode);
1433
1434                 /**
1435                  * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
1436                  *
1437                  * The hardware for LPDDR4 with
1438                  * - CLK0P/N connect to lower 16-bits
1439                  * - CLK1P/N connect to higher 16-bits
1440                  *
1441                  * dfi dram clk is configured via CLK1P/N, so disabling
1442                  * dfi dram clk will disable the CLK1P/N as well for lpddr4.
1443                  */
1444                 if (params->ch[channel].cap_info.rank == 1 &&
1445                     params->base.dramtype != LPDDR4)
1446                         setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1447                                      1 << 17);
1448         }
1449
1450         writel(sys_reg2, &dram->pmugrf->os_reg2);
1451         writel(sys_reg3, &dram->pmugrf->os_reg3);
1452         rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1453                      params->base.stride << 10);
1454
1455         /* reboot hold register set */
1456         writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1457                 PRESET_GPIO1_HOLD(1),
1458                 &dram->pmucru->pmucru_rstnhold_con[1]);
1459         clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1460 }
1461
1462 static int switch_to_phy_index1(struct dram_info *dram,
1463                                 const struct rk3399_sdram_params *params)
1464 {
1465         u32 channel;
1466         u32 *denali_phy;
1467         u32 ch_count = params->base.num_channels;
1468         int ret;
1469         int i = 0;
1470
1471         writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1472                              1 << 4 | 1 << 2 | 1),
1473                         &dram->cic->cic_ctrl0);
1474         while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1475                 mdelay(10);
1476                 i++;
1477                 if (i > 10) {
1478                         debug("index1 frequency change overtime\n");
1479                         return -ETIME;
1480                 }
1481         }
1482
1483         i = 0;
1484         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1485         while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1486                 mdelay(10);
1487                 i++;
1488                 if (i > 10) {
1489                         debug("index1 frequency done overtime\n");
1490                         return -ETIME;
1491                 }
1492         }
1493
1494         for (channel = 0; channel < ch_count; channel++) {
1495                 denali_phy = dram->chan[channel].publ->denali_phy;
1496                 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1497                 ret = data_training(&dram->chan[channel], channel,
1498                                     params, PI_FULL_TRAINING);
1499                 if (ret < 0) {
1500                         debug("index1 training failed\n");
1501                         return ret;
1502                 }
1503         }
1504
1505         return 0;
1506 }
1507
1508 static unsigned char calculate_stride(struct rk3399_sdram_params *params)
1509 {
1510         unsigned int stride = params->base.stride;
1511         unsigned int channel, chinfo = 0;
1512         unsigned int ch_cap[2] = {0, 0};
1513         u64 cap;
1514
1515         for (channel = 0; channel < 2; channel++) {
1516                 unsigned int cs0_cap = 0;
1517                 unsigned int cs1_cap = 0;
1518                 struct sdram_cap_info *cap_info = &params->ch[channel].cap_info;
1519
1520                 if (cap_info->col == 0)
1521                         continue;
1522
1523                 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
1524                                  cap_info->bk + cap_info->bw - 20));
1525                 if (cap_info->rank > 1)
1526                         cs1_cap = cs0_cap >> (cap_info->cs0_row
1527                                               - cap_info->cs1_row);
1528                 if (cap_info->row_3_4) {
1529                         cs0_cap = cs0_cap * 3 / 4;
1530                         cs1_cap = cs1_cap * 3 / 4;
1531                 }
1532                 ch_cap[channel] = cs0_cap + cs1_cap;
1533                 chinfo |= 1 << channel;
1534         }
1535
1536         /* stride calculation for 1 channel */
1537         if (params->base.num_channels == 1 && chinfo & 1)
1538                 return 0x17;    /* channel a */
1539
1540         /* stride calculation for 2 channels, default gstride type is 256B */
1541         if (ch_cap[0] == ch_cap[1]) {
1542                 cap = ch_cap[0] + ch_cap[1];
1543                 switch (cap) {
1544                 /* 512MB */
1545                 case 512:
1546                         stride = 0;
1547                         break;
1548                 /* 1GB */
1549                 case 1024:
1550                         stride = 0x5;
1551                         break;
1552                 /*
1553                  * 768MB + 768MB same as total 2GB memory
1554                  * useful space: 0-768MB 1GB-1792MB
1555                  */
1556                 case 1536:
1557                 /* 2GB */
1558                 case 2048:
1559                         stride = 0x9;
1560                         break;
1561                 /* 1536MB + 1536MB */
1562                 case 3072:
1563                         stride = 0x11;
1564                         break;
1565                 /* 4GB */
1566                 case 4096:
1567                         stride = 0xD;
1568                         break;
1569                 default:
1570                         printf("%s: Unable to calculate stride for ", __func__);
1571                         print_size((cap * (1 << 20)), " capacity\n");
1572                         break;
1573                 }
1574         }
1575
1576         sdram_print_stride(stride);
1577
1578         return stride;
1579 }
1580
1581 static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
1582 {
1583         params->ch[channel].cap_info.rank = 0;
1584         params->ch[channel].cap_info.col = 0;
1585         params->ch[channel].cap_info.bk = 0;
1586         params->ch[channel].cap_info.bw = 32;
1587         params->ch[channel].cap_info.dbw = 32;
1588         params->ch[channel].cap_info.row_3_4 = 0;
1589         params->ch[channel].cap_info.cs0_row = 0;
1590         params->ch[channel].cap_info.cs1_row = 0;
1591         params->ch[channel].cap_info.ddrconfig = 0;
1592 }
1593
1594 static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params)
1595 {
1596         int channel;
1597         int ret;
1598
1599         for (channel = 0; channel < 2; channel++) {
1600                 const struct chan_info *chan = &dram->chan[channel];
1601                 struct rk3399_cru *cru = dram->cru;
1602                 struct rk3399_ddr_publ_regs *publ = chan->publ;
1603
1604                 phy_pctrl_reset(cru, channel);
1605                 phy_dll_bypass_set(publ, params->base.ddr_freq);
1606
1607                 ret = pctl_cfg(dram, chan, channel, params);
1608                 if (ret < 0) {
1609                         printf("%s: pctl config failed\n", __func__);
1610                         return ret;
1611                 }
1612
1613                 /* start to trigger initialization */
1614                 pctl_start(dram, channel);
1615         }
1616
1617         return 0;
1618 }
1619
1620 static int sdram_init(struct dram_info *dram,
1621                       struct rk3399_sdram_params *params)
1622 {
1623         unsigned char dramtype = params->base.dramtype;
1624         unsigned int ddr_freq = params->base.ddr_freq;
1625         u32 training_flag = PI_READ_GATE_TRAINING;
1626         int channel, ch, rank;
1627         int ret;
1628
1629         debug("Starting SDRAM initialization...\n");
1630
1631         if ((dramtype == DDR3 && ddr_freq > 933) ||
1632             (dramtype == LPDDR3 && ddr_freq > 933) ||
1633             (dramtype == LPDDR4 && ddr_freq > 800)) {
1634                 debug("SDRAM frequency is to high!");
1635                 return -E2BIG;
1636         }
1637
1638         for (ch = 0; ch < 2; ch++) {
1639                 params->ch[ch].cap_info.rank = 2;
1640                 for (rank = 2; rank != 0; rank--) {
1641                         ret = pctl_init(dram, params);
1642                         if (ret < 0) {
1643                                 printf("%s: pctl init failed\n", __func__);
1644                                 return ret;
1645                         }
1646
1647                         /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1648                         if (dramtype == LPDDR3)
1649                                 udelay(10);
1650
1651                         params->ch[ch].cap_info.rank = rank;
1652
1653                         /*
1654                          * LPDDR3 CA training msut be trigger before
1655                          * other training.
1656                          * DDR3 is not have CA training.
1657                          */
1658                         if (params->base.dramtype == LPDDR3)
1659                                 training_flag |= PI_CA_TRAINING;
1660
1661                         if (!(data_training(&dram->chan[ch], ch,
1662                                             params, training_flag)))
1663                                 break;
1664                 }
1665                 /* Computed rank with associated channel number */
1666                 params->ch[ch].cap_info.rank = rank;
1667         }
1668
1669         params->base.num_channels = 0;
1670         for (channel = 0; channel < 2; channel++) {
1671                 const struct chan_info *chan = &dram->chan[channel];
1672                 struct sdram_cap_info *cap_info = &params->ch[channel].cap_info;
1673                 u8 training_flag = PI_FULL_TRAINING;
1674
1675                 if (cap_info->rank == 0) {
1676                         clear_channel_params(params, channel);
1677                         continue;
1678                 } else {
1679                         params->base.num_channels++;
1680                 }
1681
1682                 debug("Channel ");
1683                 debug(channel ? "1: " : "0: ");
1684
1685                 /* LPDDR3 should have write and read gate training */
1686                 if (params->base.dramtype == LPDDR3)
1687                         training_flag = PI_WRITE_LEVELING |
1688                                         PI_READ_GATE_TRAINING;
1689
1690                 if (params->base.dramtype != LPDDR4) {
1691                         ret = data_training(dram, channel, params,
1692                                             training_flag);
1693                         if (!ret) {
1694                                 debug("%s: data train failed for channel %d\n",
1695                                       __func__, ret);
1696                                 continue;
1697                         }
1698                 }
1699
1700                 sdram_print_ddr_info(cap_info, &params->base);
1701
1702                 set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
1703         }
1704
1705         if (params->base.num_channels == 0) {
1706                 printf("%s: ", __func__);
1707                 sdram_print_dram_type(params->base.dramtype);
1708                 printf(" - %dMHz failed!\n", params->base.ddr_freq);
1709                 return -EINVAL;
1710         }
1711
1712         params->base.stride = calculate_stride(params);
1713         dram_all_config(dram, params);
1714         switch_to_phy_index1(dram, params);
1715
1716         debug("Finish SDRAM initialization...\n");
1717         return 0;
1718 }
1719
1720 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1721 {
1722 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1723         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1724         int ret;
1725
1726         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1727                                  (u32 *)&plat->sdram_params,
1728                                  sizeof(plat->sdram_params) / sizeof(u32));
1729         if (ret) {
1730                 printf("%s: Cannot read rockchip,sdram-params %d\n",
1731                        __func__, ret);
1732                 return ret;
1733         }
1734         ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
1735         if (ret)
1736                 printf("%s: regmap failed %d\n", __func__, ret);
1737
1738 #endif
1739         return 0;
1740 }
1741
1742 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1743 static int conv_of_platdata(struct udevice *dev)
1744 {
1745         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1746         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1747         int ret;
1748
1749         ret = regmap_init_mem_platdata(dev, dtplat->reg,
1750                                        ARRAY_SIZE(dtplat->reg) / 2,
1751                                        &plat->map);
1752         if (ret)
1753                 return ret;
1754
1755         return 0;
1756 }
1757 #endif
1758
1759 static int rk3399_dmc_init(struct udevice *dev)
1760 {
1761         struct dram_info *priv = dev_get_priv(dev);
1762         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1763         int ret;
1764 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1765         struct rk3399_sdram_params *params = &plat->sdram_params;
1766 #else
1767         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1768         struct rk3399_sdram_params *params =
1769                                         (void *)dtplat->rockchip_sdram_params;
1770
1771         ret = conv_of_platdata(dev);
1772         if (ret)
1773                 return ret;
1774 #endif
1775
1776         priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1777         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1778         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1779         priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1780         priv->pmucru = rockchip_get_pmucru();
1781         priv->cru = rockchip_get_cru();
1782         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1783         priv->chan[0].pi = regmap_get_range(plat->map, 1);
1784         priv->chan[0].publ = regmap_get_range(plat->map, 2);
1785         priv->chan[0].msch = regmap_get_range(plat->map, 3);
1786         priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1787         priv->chan[1].pi = regmap_get_range(plat->map, 5);
1788         priv->chan[1].publ = regmap_get_range(plat->map, 6);
1789         priv->chan[1].msch = regmap_get_range(plat->map, 7);
1790
1791         debug("con reg %p %p %p %p %p %p %p %p\n",
1792               priv->chan[0].pctl, priv->chan[0].pi,
1793               priv->chan[0].publ, priv->chan[0].msch,
1794               priv->chan[1].pctl, priv->chan[1].pi,
1795               priv->chan[1].publ, priv->chan[1].msch);
1796         debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1797               priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1798
1799 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1800         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1801 #else
1802         ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1803 #endif
1804         if (ret) {
1805                 printf("%s clk get failed %d\n", __func__, ret);
1806                 return ret;
1807         }
1808
1809         ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1810         if (ret < 0) {
1811                 printf("%s clk set failed %d\n", __func__, ret);
1812                 return ret;
1813         }
1814
1815         ret = sdram_init(priv, params);
1816         if (ret < 0) {
1817                 printf("%s DRAM init failed %d\n", __func__, ret);
1818                 return ret;
1819         }
1820
1821         return 0;
1822 }
1823 #endif
1824
1825 static int rk3399_dmc_probe(struct udevice *dev)
1826 {
1827 #if defined(CONFIG_TPL_BUILD) || \
1828         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1829         if (rk3399_dmc_init(dev))
1830                 return 0;
1831 #else
1832         struct dram_info *priv = dev_get_priv(dev);
1833
1834         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1835         debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
1836         priv->info.base = CONFIG_SYS_SDRAM_BASE;
1837         priv->info.size =
1838                 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
1839 #endif
1840         return 0;
1841 }
1842
1843 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1844 {
1845         struct dram_info *priv = dev_get_priv(dev);
1846
1847         *info = priv->info;
1848
1849         return 0;
1850 }
1851
1852 static struct ram_ops rk3399_dmc_ops = {
1853         .get_info = rk3399_dmc_get_info,
1854 };
1855
1856 static const struct udevice_id rk3399_dmc_ids[] = {
1857         { .compatible = "rockchip,rk3399-dmc" },
1858         { }
1859 };
1860
1861 U_BOOT_DRIVER(dmc_rk3399) = {
1862         .name = "rockchip_rk3399_dmc",
1863         .id = UCLASS_RAM,
1864         .of_match = rk3399_dmc_ids,
1865         .ops = &rk3399_dmc_ops,
1866 #if defined(CONFIG_TPL_BUILD) || \
1867         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1868         .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1869 #endif
1870         .probe = rk3399_dmc_probe,
1871         .priv_auto_alloc_size = sizeof(struct dram_info),
1872 #if defined(CONFIG_TPL_BUILD) || \
1873         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1874         .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
1875 #endif
1876 };