drivers/ram/rockchip/sdram_rk3188.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  * Copyright 2014 Rockchip Inc.
   5  *
   6  * Adapted from the very similar rk3288 ddr init.
   7  */
   8
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <dm.h>
  12 #include <dt-structs.h>
  13 #include <errno.h>
  14 #include <ram.h>
  15 #include <regmap.h>
  16 #include <syscon.h>
  17 #include <asm/io.h>
  18 #include <asm/arch-rockchip/clock.h>
  19 #include <asm/arch-rockchip/cru_rk3188.h>
  20 #include <asm/arch-rockchip/ddr_rk3188.h>
  21 #include <asm/arch-rockchip/grf_rk3188.h>
  22 #include <asm/arch-rockchip/pmu_rk3188.h>
  23 #include <asm/arch-rockchip/sdram.h>
  24 #include <asm/arch-rockchip/sdram_common.h>
  25 #include <linux/err.h>
  26
  27 struct chan_info {
  28         struct rk3288_ddr_pctl *pctl;
  29         struct rk3288_ddr_publ *publ;
  30         struct rk3188_msch *msch;
  31 };
  32
  33 struct dram_info {
  34         struct chan_info chan[1];
  35         struct ram_info info;
  36         struct clk ddr_clk;
  37         struct rk3188_cru *cru;
  38         struct rk3188_grf *grf;
  39         struct rk3188_sgrf *sgrf;
  40         struct rk3188_pmu *pmu;
  41 };
  42
  43 struct rk3188_sdram_params {
  44 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  45         struct dtd_rockchip_rk3188_dmc of_plat;
  46 #endif
  47         struct rk3288_sdram_channel ch[2];
  48         struct rk3288_sdram_pctl_timing pctl_timing;
  49         struct rk3288_sdram_phy_timing phy_timing;
  50         struct rk3288_base_params base;
  51         int num_channels;
  52         struct regmap *map;
  53 };
  54
  55 const int ddrconf_table[] = {
  56         /*
  57          * [5:4] row(13+n)
  58          * [1:0] col(9+n), assume bw=2
  59          * row      col,bw
  60          */
  61         0,
  62         ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  63         ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  64         ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  65         ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  66         ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  67         ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  68         ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
  69         ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
  70         0,
  71         0,
  72         0,
  73         0,
  74         0,
  75         0,
  76         0,
  77 };
  78
  79 #define TEST_PATTEN     0x5aa5f00f
  80 #define DQS_GATE_TRAINING_ERROR_RANK0   (1 << 4)
  81 #define DQS_GATE_TRAINING_ERROR_RANK1   (2 << 4)
  82
  83 #ifdef CONFIG_SPL_BUILD
  84 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
  85 {
  86         int i;
  87
  88         for (i = 0; i < n / sizeof(u32); i++) {
  89                 writel(*src, dest);
  90                 src++;
  91                 dest++;
  92         }
  93 }
  94
  95 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy)
  96 {
  97         u32 phy_ctl_srstn_shift = 13;
  98         u32 ctl_psrstn_shift = 11;
  99         u32 ctl_srstn_shift = 10;
 100         u32 phy_psrstn_shift = 9;
 101         u32 phy_srstn_shift = 8;
 102
 103         rk_clrsetreg(&cru->cru_softrst_con[5],
 104                      1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
 105                      1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
 106                      1 << phy_srstn_shift,
 107                      phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
 108                      ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
 109                      phy << phy_srstn_shift);
 110 }
 111
 112 static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n)
 113 {
 114         u32 phy_ctl_srstn_shift = 13;
 115
 116         rk_clrsetreg(&cru->cru_softrst_con[5],
 117                      1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
 118 }
 119
 120 static void phy_pctrl_reset(struct rk3188_cru *cru,
 121                             struct rk3288_ddr_publ *publ,
 122                             int channel)
 123 {
 124         int i;
 125
 126         ddr_reset(cru, channel, 1, 1);
 127         udelay(1);
 128         clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
 129         for (i = 0; i < 4; i++)
 130                 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
 131
 132         udelay(10);
 133         setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
 134         for (i = 0; i < 4; i++)
 135                 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
 136
 137         udelay(10);
 138         ddr_reset(cru, channel, 1, 0);
 139         udelay(10);
 140         ddr_reset(cru, channel, 0, 0);
 141         udelay(10);
 142 }
 143
 144 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
 145         u32 freq)
 146 {
 147         int i;
 148
 149         if (freq <= 250000000) {
 150                 if (freq <= 150000000)
 151                         clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 152                 else
 153                         setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 154                 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
 155                 for (i = 0; i < 4; i++)
 156                         setbits_le32(&publ->datx8[i].dxdllcr,
 157                                      DXDLLCR_DLLDIS);
 158
 159                 setbits_le32(&publ->pir, PIR_DLLBYP);
 160         } else {
 161                 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 162                 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
 163                 for (i = 0; i < 4; i++) {
 164                         clrbits_le32(&publ->datx8[i].dxdllcr,
 165                                      DXDLLCR_DLLDIS);
 166                 }
 167
 168                 clrbits_le32(&publ->pir, PIR_DLLBYP);
 169         }
 170 }
 171
 172 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
 173 {
 174         writel(DFI_INIT_START, &pctl->dfistcfg0);
 175         writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
 176                &pctl->dfistcfg1);
 177         writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
 178         writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
 179                &pctl->dfilpcfg0);
 180
 181         writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
 182         writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
 183         writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
 184         writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
 185         writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
 186         writel(1, &pctl->dfitphyupdtype0);
 187
 188         /* cs0 and cs1 write odt enable */
 189         writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
 190                &pctl->dfiodtcfg);
 191         /* odt write length */
 192         writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
 193         /* phyupd and ctrlupd disabled */
 194         writel(0, &pctl->dfiupdcfg);
 195 }
 196
 197 static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable)
 198 {
 199         uint val = 0;
 200
 201         if (enable)
 202                 val = 1 << DDR_16BIT_EN_SHIFT;
 203
 204         rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val);
 205 }
 206
 207 static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel,
 208                               bool ddr3_mode)
 209 {
 210         uint mask, val;
 211
 212         mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT;
 213         val = ddr3_mode << MSCH4_MAINDDR3_SHIFT;
 214         rk_clrsetreg(&grf->soc_con2, mask, val);
 215 }
 216
 217 static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable)
 218 {
 219         uint mask, val;
 220
 221         mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT;
 222         val = enable << RANK_TO_ROW15_EN_SHIFT;
 223         rk_clrsetreg(&grf->soc_con2, mask, val);
 224 }
 225
 226 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
 227                      struct rk3188_sdram_params *sdram_params,
 228                      struct rk3188_grf *grf)
 229 {
 230         copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
 231                     sizeof(sdram_params->pctl_timing));
 232         switch (sdram_params->base.dramtype) {
 233         case DDR3:
 234                 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
 235                         writel(sdram_params->pctl_timing.tcl - 3,
 236                                &pctl->dfitrddataen);
 237                 } else {
 238                         writel(sdram_params->pctl_timing.tcl - 2,
 239                                &pctl->dfitrddataen);
 240                 }
 241                 writel(sdram_params->pctl_timing.tcwl - 1,
 242                        &pctl->dfitphywrlat);
 243                 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
 244                        DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
 245                        1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
 246                        &pctl->mcfg);
 247                 ddr_set_ddr3_mode(grf, channel, true);
 248                 ddr_set_enable(grf, channel, true);
 249                 break;
 250         }
 251
 252         setbits_le32(&pctl->scfg, 1);
 253 }
 254
 255 static void phy_cfg(const struct chan_info *chan, int channel,
 256                     struct rk3188_sdram_params *sdram_params)
 257 {
 258         struct rk3288_ddr_publ *publ = chan->publ;
 259         struct rk3188_msch *msch = chan->msch;
 260         uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
 261         u32 dinit2;
 262         int i;
 263
 264         dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
 265         /* DDR PHY Timing */
 266         copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
 267                     sizeof(sdram_params->phy_timing));
 268         writel(sdram_params->base.noc_timing, &msch->ddrtiming);
 269         writel(0x3f, &msch->readlatency);
 270         writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
 271                DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
 272                8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
 273         writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
 274                DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
 275                &publ->ptr[1]);
 276         writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
 277                DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
 278                &publ->ptr[2]);
 279
 280         switch (sdram_params->base.dramtype) {
 281         case DDR3:
 282                 clrbits_le32(&publ->pgcr, 0x1f);
 283                 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
 284                                 DDRMD_DDR3 << DDRMD_SHIFT);
 285                 break;
 286         }
 287         if (sdram_params->base.odt) {
 288                 /*dynamic RTT enable */
 289                 for (i = 0; i < 4; i++)
 290                         setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
 291         } else {
 292                 /*dynamic RTT disable */
 293                 for (i = 0; i < 4; i++)
 294                         clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
 295         }
 296 }
 297
 298 static void phy_init(struct rk3288_ddr_publ *publ)
 299 {
 300         setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
 301                 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
 302         udelay(1);
 303         while ((readl(&publ->pgsr) &
 304                 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
 305                 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
 306                 ;
 307 }
 308
 309 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
 310                          u32 cmd, u32 arg)
 311 {
 312         writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
 313         udelay(1);
 314         while (readl(&pctl->mcmd) & START_CMD)
 315                 ;
 316 }
 317
 318 static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
 319                                    u32 rank, u32 cmd, u32 ma, u32 op)
 320 {
 321         send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
 322                      (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
 323 }
 324
 325 static void memory_init(struct rk3288_ddr_publ *publ,
 326                         u32 dramtype)
 327 {
 328         setbits_le32(&publ->pir,
 329                      (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
 330                       | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
 331                       | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
 332         udelay(1);
 333         while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
 334                 != (PGSR_IDONE | PGSR_DLDONE))
 335                 ;
 336 }
 337
 338 static void move_to_config_state(struct rk3288_ddr_publ *publ,
 339                                  struct rk3288_ddr_pctl *pctl)
 340 {
 341         unsigned int state;
 342
 343         while (1) {
 344                 state = readl(&pctl->stat) & PCTL_STAT_MSK;
 345
 346                 switch (state) {
 347                 case LOW_POWER:
 348                         writel(WAKEUP_STATE, &pctl->sctl);
 349                         while ((readl(&pctl->stat) & PCTL_STAT_MSK)
 350                                 != ACCESS)
 351                                 ;
 352                         /* wait DLL lock */
 353                         while ((readl(&publ->pgsr) & PGSR_DLDONE)
 354                                 != PGSR_DLDONE)
 355                                 ;
 356                         /*
 357                          * if at low power state,need wakeup first,
 358                          * and then enter the config, so
 359                          * fallthrough
 360                          */
 361                 case ACCESS:
 362                         /* fallthrough */
 363                 case INIT_MEM:
 364                         writel(CFG_STATE, &pctl->sctl);
 365                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
 366                                 ;
 367                         break;
 368                 case CONFIG:
 369                         return;
 370                 default:
 371                         break;
 372                 }
 373         }
 374 }
 375
 376 static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
 377                                 u32 n, struct rk3188_grf *grf)
 378 {
 379         struct rk3288_ddr_pctl *pctl = chan->pctl;
 380         struct rk3288_ddr_publ *publ = chan->publ;
 381         struct rk3188_msch *msch = chan->msch;
 382
 383         if (n == 1) {
 384                 setbits_le32(&pctl->ppcfg, 1);
 385                 ddr_set_enable(grf, channel, 1);
 386                 setbits_le32(&msch->ddrtiming, 1 << 31);
 387                 /* Data Byte disable*/
 388                 clrbits_le32(&publ->datx8[2].dxgcr, 1);
 389                 clrbits_le32(&publ->datx8[3].dxgcr, 1);
 390                 /* disable DLL */
 391                 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
 392                 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
 393         } else {
 394                 clrbits_le32(&pctl->ppcfg, 1);
 395                 ddr_set_enable(grf, channel, 0);
 396                 clrbits_le32(&msch->ddrtiming, 1 << 31);
 397                 /* Data Byte enable*/
 398                 setbits_le32(&publ->datx8[2].dxgcr, 1);
 399                 setbits_le32(&publ->datx8[3].dxgcr, 1);
 400
 401                 /* enable DLL */
 402                 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
 403                 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
 404                 /* reset DLL */
 405                 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
 406                 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
 407                 udelay(10);
 408                 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
 409                 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
 410         }
 411         setbits_le32(&pctl->dfistcfg0, 1 << 2);
 412 }
 413
 414 static int data_training(const struct chan_info *chan, int channel,
 415                          struct rk3188_sdram_params *sdram_params)
 416 {
 417         unsigned int j;
 418         int ret = 0;
 419         u32 rank;
 420         int i;
 421         u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
 422         struct rk3288_ddr_publ *publ = chan->publ;
 423         struct rk3288_ddr_pctl *pctl = chan->pctl;
 424
 425         /* disable auto refresh */
 426         writel(0, &pctl->trefi);
 427
 428         if (sdram_params->base.dramtype != LPDDR3)
 429                 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
 430         rank = sdram_params->ch[channel].rank | 1;
 431         for (j = 0; j < ARRAY_SIZE(step); j++) {
 432                 /*
 433                  * trigger QSTRN and RVTRN
 434                  * clear DTDONE status
 435                  */
 436                 setbits_le32(&publ->pir, PIR_CLRSR);
 437
 438                 /* trigger DTT */
 439                 setbits_le32(&publ->pir,
 440                              PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
 441                              PIR_CLRSR);
 442                 udelay(1);
 443                 /* wait echo byte DTDONE */
 444                 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
 445                         != rank)
 446                         ;
 447                 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
 448                         != rank)
 449                         ;
 450                 if (!(readl(&pctl->ppcfg) & 1)) {
 451                         while ((readl(&publ->datx8[2].dxgsr[0])
 452                                 & rank) != rank)
 453                                 ;
 454                         while ((readl(&publ->datx8[3].dxgsr[0])
 455                                 & rank) != rank)
 456                                 ;
 457                 }
 458                 if (readl(&publ->pgsr) &
 459                     (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
 460                         ret = -1;
 461                         break;
 462                 }
 463         }
 464         /* send some auto refresh to complement the lost while DTT */
 465         for (i = 0; i < (rank > 1 ? 8 : 4); i++)
 466                 send_command(pctl, rank, REF_CMD, 0);
 467
 468         if (sdram_params->base.dramtype != LPDDR3)
 469                 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
 470
 471         /* resume auto refresh */
 472         writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
 473
 474         return ret;
 475 }
 476
 477 static void move_to_access_state(const struct chan_info *chan)
 478 {
 479         struct rk3288_ddr_publ *publ = chan->publ;
 480         struct rk3288_ddr_pctl *pctl = chan->pctl;
 481         unsigned int state;
 482
 483         while (1) {
 484                 state = readl(&pctl->stat) & PCTL_STAT_MSK;
 485
 486                 switch (state) {
 487                 case LOW_POWER:
 488                         if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
 489                                         LP_TRIG_MASK) == 1)
 490                                 return;
 491
 492                         writel(WAKEUP_STATE, &pctl->sctl);
 493                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
 494                                 ;
 495                         /* wait DLL lock */
 496                         while ((readl(&publ->pgsr) & PGSR_DLDONE)
 497                                 != PGSR_DLDONE)
 498                                 ;
 499                         break;
 500                 case INIT_MEM:
 501                         writel(CFG_STATE, &pctl->sctl);
 502                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
 503                                 ;
 504                         /* fallthrough */
 505                 case CONFIG:
 506                         writel(GO_STATE, &pctl->sctl);
 507                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
 508                                 ;
 509                         break;
 510                 case ACCESS:
 511                         return;
 512                 default:
 513                         break;
 514                 }
 515         }
 516 }
 517
 518 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
 519                          struct rk3188_sdram_params *sdram_params)
 520 {
 521         struct rk3288_ddr_publ *publ = chan->publ;
 522
 523         if (sdram_params->ch[chnum].bk == 3)
 524                 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
 525                                 1 << PDQ_SHIFT);
 526         else
 527                 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
 528
 529         writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
 530 }
 531
 532 static void dram_all_config(const struct dram_info *dram,
 533                             struct rk3188_sdram_params *sdram_params)
 534 {
 535         unsigned int chan;
 536         u32 sys_reg = 0;
 537
 538         sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
 539         sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
 540         for (chan = 0; chan < sdram_params->num_channels; chan++) {
 541                 const struct rk3288_sdram_channel *info =
 542                         &sdram_params->ch[chan];
 543
 544                 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
 545                 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
 546                 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
 547                 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
 548                 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
 549                 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
 550                 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
 551                 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
 552                 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
 553
 554                 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
 555         }
 556         if (sdram_params->ch[0].rank == 2)
 557                 ddr_rank_2_row15en(dram->grf, 0);
 558         else
 559                 ddr_rank_2_row15en(dram->grf, 1);
 560
 561         writel(sys_reg, &dram->pmu->sys_reg[2]);
 562 }
 563
 564 static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
 565                 struct rk3188_sdram_params *sdram_params)
 566 {
 567         int reg;
 568         int need_trainig = 0;
 569         const struct chan_info *chan = &dram->chan[channel];
 570         struct rk3288_ddr_publ *publ = chan->publ;
 571
 572         ddr_rank_2_row15en(dram->grf, 0);
 573
 574         if (data_training(chan, channel, sdram_params) < 0) {
 575                 printf("first data training fail!\n");
 576                 reg = readl(&publ->datx8[0].dxgsr[0]);
 577                 /* Check the result for rank 0 */
 578                 if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
 579                         printf("data training fail!\n");
 580                         return -EIO;
 581                 }
 582
 583                 /* Check the result for rank 1 */
 584                 if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
 585                         sdram_params->ch[channel].rank = 1;
 586                         clrsetbits_le32(&publ->pgcr, 0xF << 18,
 587                                         sdram_params->ch[channel].rank << 18);
 588                         need_trainig = 1;
 589                 }
 590                 reg = readl(&publ->datx8[2].dxgsr[0]);
 591                 if (reg & (1 << 4)) {
 592                         sdram_params->ch[channel].bw = 1;
 593                         set_bandwidth_ratio(chan, channel,
 594                                             sdram_params->ch[channel].bw,
 595                                             dram->grf);
 596                         need_trainig = 1;
 597                 }
 598         }
 599         /* Assume the Die bit width are the same with the chip bit width */
 600         sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
 601
 602         if (need_trainig &&
 603             (data_training(chan, channel, sdram_params) < 0)) {
 604                 if (sdram_params->base.dramtype == LPDDR3) {
 605                         ddr_phy_ctl_reset(dram->cru, channel, 1);
 606                         udelay(10);
 607                         ddr_phy_ctl_reset(dram->cru, channel, 0);
 608                         udelay(10);
 609                 }
 610                 printf("2nd data training failed!");
 611                 return -EIO;
 612         }
 613
 614         return 0;
 615 }
 616
 617 /*
 618  * Detect ram columns and rows.
 619  * @dram: dram info struct
 620  * @channel: channel number to handle
 621  * @sdram_params: sdram parameters, function will fill in col and row values
 622  *
 623  * Returns 0 or negative on error.
 624  */
 625 static int sdram_col_row_detect(struct dram_info *dram, int channel,
 626                 struct rk3188_sdram_params *sdram_params)
 627 {
 628         int row, col;
 629         unsigned int addr;
 630         const struct chan_info *chan = &dram->chan[channel];
 631         struct rk3288_ddr_pctl *pctl = chan->pctl;
 632         struct rk3288_ddr_publ *publ = chan->publ;
 633         int ret = 0;
 634
 635         /* Detect col */
 636         for (col = 11; col >= 9; col--) {
 637                 writel(0, CONFIG_SYS_SDRAM_BASE);
 638                 addr = CONFIG_SYS_SDRAM_BASE +
 639                         (1 << (col + sdram_params->ch[channel].bw - 1));
 640                 writel(TEST_PATTEN, addr);
 641                 if ((readl(addr) == TEST_PATTEN) &&
 642                     (readl(CONFIG_SYS_SDRAM_BASE) == 0))
 643                         break;
 644         }
 645         if (col == 8) {
 646                 printf("Col detect error\n");
 647                 ret = -EINVAL;
 648                 goto out;
 649         } else {
 650                 sdram_params->ch[channel].col = col;
 651         }
 652
 653         ddr_rank_2_row15en(dram->grf, 1);
 654         move_to_config_state(publ, pctl);
 655         writel(1, &chan->msch->ddrconf);
 656         move_to_access_state(chan);
 657         /* Detect row, max 15,min13 in rk3188*/
 658         for (row = 16; row >= 13; row--) {
 659                 writel(0, CONFIG_SYS_SDRAM_BASE);
 660                 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
 661                 writel(TEST_PATTEN, addr);
 662                 if ((readl(addr) == TEST_PATTEN) &&
 663                     (readl(CONFIG_SYS_SDRAM_BASE) == 0))
 664                         break;
 665         }
 666         if (row == 12) {
 667                 printf("Row detect error\n");
 668                 ret = -EINVAL;
 669         } else {
 670                 sdram_params->ch[channel].cs1_row = row;
 671                 sdram_params->ch[channel].row_3_4 = 0;
 672                 debug("chn %d col %d, row %d\n", channel, col, row);
 673                 sdram_params->ch[channel].cs0_row = row;
 674         }
 675
 676 out:
 677         return ret;
 678 }
 679
 680 static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params)
 681 {
 682         int i, tmp, size, row, ret = 0;
 683
 684         row = sdram_params->ch[0].cs0_row;
 685         /*
 686          * RK3188 share the rank and row bit15, we use same ddr config for 15bit
 687          * and 16bit row
 688          */
 689         if (row == 16)
 690                 row = 15;
 691         tmp = sdram_params->ch[0].col - 9;
 692         tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
 693         tmp |= ((row - 13) << 4);
 694         size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
 695         for (i = 0; i < size; i++)
 696                 if (tmp == ddrconf_table[i])
 697                         break;
 698         if (i >= size) {
 699                 printf("niu config not found\n");
 700                 ret = -EINVAL;
 701         } else {
 702                 debug("niu config %d\n", i);
 703                 sdram_params->base.ddrconfig = i;
 704         }
 705
 706         return ret;
 707 }
 708
 709 static int sdram_init(struct dram_info *dram,
 710                       struct rk3188_sdram_params *sdram_params)
 711 {
 712         int channel;
 713         int zqcr;
 714         int ret;
 715
 716         if ((sdram_params->base.dramtype == DDR3 &&
 717              sdram_params->base.ddr_freq > 800000000)) {
 718                 printf("SDRAM frequency is too high!");
 719                 return -E2BIG;
 720         }
 721
 722         ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
 723         if (ret) {
 724                 printf("Could not set DDR clock\n");
 725                 return ret;
 726         }
 727
 728         for (channel = 0; channel < 1; channel++) {
 729                 const struct chan_info *chan = &dram->chan[channel];
 730                 struct rk3288_ddr_pctl *pctl = chan->pctl;
 731                 struct rk3288_ddr_publ *publ = chan->publ;
 732
 733                 phy_pctrl_reset(dram->cru, publ, channel);
 734                 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
 735
 736                 dfi_cfg(pctl, sdram_params->base.dramtype);
 737
 738                 pctl_cfg(channel, pctl, sdram_params, dram->grf);
 739
 740                 phy_cfg(chan, channel, sdram_params);
 741
 742                 phy_init(publ);
 743
 744                 writel(POWER_UP_START, &pctl->powctl);
 745                 while (!(readl(&pctl->powstat) & POWER_UP_DONE))
 746                         ;
 747
 748                 memory_init(publ, sdram_params->base.dramtype);
 749                 move_to_config_state(publ, pctl);
 750
 751                 /* Using 32bit bus width for detect */
 752                 sdram_params->ch[channel].bw = 2;
 753                 set_bandwidth_ratio(chan, channel,
 754                                     sdram_params->ch[channel].bw, dram->grf);
 755                 /*
 756                  * set cs, using n=3 for detect
 757                  * CS0, n=1
 758                  * CS1, n=2
 759                  * CS0 & CS1, n = 3
 760                  */
 761                 sdram_params->ch[channel].rank = 2,
 762                 clrsetbits_le32(&publ->pgcr, 0xF << 18,
 763                                 (sdram_params->ch[channel].rank | 1) << 18);
 764
 765                 /* DS=40ohm,ODT=155ohm */
 766                 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
 767                         2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
 768                         0x19 << PD_OUTPUT_SHIFT;
 769                 writel(zqcr, &publ->zq1cr[0]);
 770                 writel(zqcr, &publ->zq0cr[0]);
 771
 772                 /* Detect the rank and bit-width with data-training */
 773                 writel(1, &chan->msch->ddrconf);
 774                 sdram_rank_bw_detect(dram, channel, sdram_params);
 775
 776                 if (sdram_params->base.dramtype == LPDDR3) {
 777                         u32 i;
 778                         writel(0, &pctl->mrrcfg0);
 779                         for (i = 0; i < 17; i++)
 780                                 send_command_op(pctl, 1, MRR_CMD, i, 0);
 781                 }
 782                 writel(4, &chan->msch->ddrconf);
 783                 move_to_access_state(chan);
 784                 /* DDR3 and LPDDR3 are always 8 bank, no need detect */
 785                 sdram_params->ch[channel].bk = 3;
 786                 /* Detect Col and Row number*/
 787                 ret = sdram_col_row_detect(dram, channel, sdram_params);
 788                 if (ret)
 789                         goto error;
 790         }
 791         /* Find NIU DDR configuration */
 792         ret = sdram_get_niu_config(sdram_params);
 793         if (ret)
 794                 goto error;
 795
 796         dram_all_config(dram, sdram_params);
 797         debug("%s done\n", __func__);
 798
 799         return 0;
 800 error:
 801         printf("DRAM init failed!\n");
 802         hang();
 803 }
 804
 805 static int setup_sdram(struct udevice *dev)
 806 {
 807         struct dram_info *priv = dev_get_priv(dev);
 808         struct rk3188_sdram_params *params = dev_get_platdata(dev);
 809
 810         return sdram_init(priv, params);
 811 }
 812
 813 static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev)
 814 {
 815 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 816         struct rk3188_sdram_params *params = dev_get_platdata(dev);
 817         int ret;
 818
 819         /* rk3188 supports only one-channel */
 820         params->num_channels = 1;
 821         ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
 822                                  (u32 *)&params->pctl_timing,
 823                                  sizeof(params->pctl_timing) / sizeof(u32));
 824         if (ret) {
 825                 printf("%s: Cannot read rockchip,pctl-timing\n", __func__);
 826                 return -EINVAL;
 827         }
 828         ret = dev_read_u32_array(dev, "rockchip,phy-timing",
 829                                  (u32 *)&params->phy_timing,
 830                                  sizeof(params->phy_timing) / sizeof(u32));
 831         if (ret) {
 832                 printf("%s: Cannot read rockchip,phy-timing\n", __func__);
 833                 return -EINVAL;
 834         }
 835         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
 836                                  (u32 *)&params->base,
 837                                  sizeof(params->base) / sizeof(u32));
 838         if (ret) {
 839                 printf("%s: Cannot read rockchip,sdram-params\n", __func__);
 840                 return -EINVAL;
 841         }
 842         ret = regmap_init_mem(dev_ofnode(dev), &params->map);
 843         if (ret)
 844                 return ret;
 845 #endif
 846
 847         return 0;
 848 }
 849 #endif /* CONFIG_SPL_BUILD */
 850
 851 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 852 static int conv_of_platdata(struct udevice *dev)
 853 {
 854         struct rk3188_sdram_params *plat = dev_get_platdata(dev);
 855         struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat;
 856         int ret;
 857
 858         memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
 859                sizeof(plat->pctl_timing));
 860         memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
 861                sizeof(plat->phy_timing));
 862         memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
 863         /* rk3188 supports dual-channel, set default channel num to 2 */
 864         plat->num_channels = 1;
 865         ret = regmap_init_mem_platdata(dev, of_plat->reg,
 866                                        ARRAY_SIZE(of_plat->reg) / 2,
 867                                        &plat->map);
 868         if (ret)
 869                 return ret;
 870
 871         return 0;
 872 }
 873 #endif
 874
 875 static int rk3188_dmc_probe(struct udevice *dev)
 876 {
 877 #ifdef CONFIG_SPL_BUILD
 878         struct rk3188_sdram_params *plat = dev_get_platdata(dev);
 879         struct regmap *map;
 880         struct udevice *dev_clk;
 881         int ret;
 882 #endif
 883         struct dram_info *priv = dev_get_priv(dev);
 884
 885         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 886
 887 #ifdef CONFIG_SPL_BUILD
 888 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 889         ret = conv_of_platdata(dev);
 890         if (ret)
 891                 return ret;
 892 #endif
 893         map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
 894         if (IS_ERR(map))
 895                 return PTR_ERR(map);
 896         priv->chan[0].msch = regmap_get_range(map, 0);
 897
 898         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 899
 900         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
 901         priv->chan[0].publ = regmap_get_range(plat->map, 1);
 902
 903         ret = rockchip_get_clk(&dev_clk);
 904         if (ret)
 905                 return ret;
 906         priv->ddr_clk.id = CLK_DDR;
 907         ret = clk_request(dev_clk, &priv->ddr_clk);
 908         if (ret)
 909                 return ret;
 910
 911         priv->cru = rockchip_get_cru();
 912         if (IS_ERR(priv->cru))
 913                 return PTR_ERR(priv->cru);
 914         ret = setup_sdram(dev);
 915         if (ret)
 916                 return ret;
 917 #else
 918         priv->info.base = CONFIG_SYS_SDRAM_BASE;
 919         priv->info.size = rockchip_sdram_size(
 920                                 (phys_addr_t)&priv->pmu->sys_reg[2]);
 921 #endif
 922
 923         return 0;
 924 }
 925
 926 static int rk3188_dmc_get_info(struct udevice *dev, struct ram_info *info)
 927 {
 928         struct dram_info *priv = dev_get_priv(dev);
 929
 930         *info = priv->info;
 931
 932         return 0;
 933 }
 934
 935 static struct ram_ops rk3188_dmc_ops = {
 936         .get_info = rk3188_dmc_get_info,
 937 };
 938
 939 static const struct udevice_id rk3188_dmc_ids[] = {
 940         { .compatible = "rockchip,rk3188-dmc" },
 941         { }
 942 };
 943
 944 U_BOOT_DRIVER(dmc_rk3188) = {
 945         .name = "rockchip_rk3188_dmc",
 946         .id = UCLASS_RAM,
 947         .of_match = rk3188_dmc_ids,
 948         .ops = &rk3188_dmc_ops,
 949 #ifdef CONFIG_SPL_BUILD
 950         .ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata,
 951 #endif
 952         .probe = rk3188_dmc_probe,
 953         .priv_auto_alloc_size = sizeof(struct dram_info),
 954 #ifdef CONFIG_SPL_BUILD
 955         .platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params),
 956 #endif
 957 };