drivers/ram/rockchip/sdram_rk3188.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  * Copyright 2014 Rockchip Inc.
   5  *
   6  * Adapted from the very similar rk3288 ddr init.
   7  */
   8
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <dm.h>
  12 #include <dt-structs.h>
  13 #include <errno.h>
  14 #include <hang.h>
  15 #include <init.h>
  16 #include <log.h>
  17 #include <ram.h>
  18 #include <regmap.h>
  19 #include <syscon.h>
  20 #include <asm/io.h>
  21 #include <asm/arch-rockchip/clock.h>
  22 #include <asm/arch-rockchip/cru_rk3188.h>
  23 #include <asm/arch-rockchip/ddr_rk3188.h>
  24 #include <asm/arch-rockchip/grf_rk3188.h>
  25 #include <asm/arch-rockchip/pmu_rk3188.h>
  26 #include <asm/arch-rockchip/sdram.h>
  27 #include <asm/arch-rockchip/sdram_rk3288.h>
  28 #include <linux/delay.h>
  29 #include <linux/err.h>
  30
  31 struct chan_info {
  32         struct rk3288_ddr_pctl *pctl;
  33         struct rk3288_ddr_publ *publ;
  34         struct rk3188_msch *msch;
  35 };
  36
  37 struct dram_info {
  38         struct chan_info chan[1];
  39         struct ram_info info;
  40         struct clk ddr_clk;
  41         struct rk3188_cru *cru;
  42         struct rk3188_grf *grf;
  43         struct rk3188_sgrf *sgrf;
  44         struct rk3188_pmu *pmu;
  45 };
  46
  47 struct rk3188_sdram_params {
  48 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  49         struct dtd_rockchip_rk3188_dmc of_plat;
  50 #endif
  51         struct rk3288_sdram_channel ch[2];
  52         struct rk3288_sdram_pctl_timing pctl_timing;
  53         struct rk3288_sdram_phy_timing phy_timing;
  54         struct rk3288_base_params base;
  55         int num_channels;
  56         struct regmap *map;
  57 };
  58
  59 const int ddrconf_table[] = {
  60         /*
  61          * [5:4] row(13+n)
  62          * [1:0] col(9+n), assume bw=2
  63          * row      col,bw
  64          */
  65         0,
  66         ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  67         ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  68         ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  69         ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  70         ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  71         ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  72         ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
  73         ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
  74         0,
  75         0,
  76         0,
  77         0,
  78         0,
  79         0,
  80         0,
  81 };
  82
  83 #define TEST_PATTEN     0x5aa5f00f
  84 #define DQS_GATE_TRAINING_ERROR_RANK0   (1 << 4)
  85 #define DQS_GATE_TRAINING_ERROR_RANK1   (2 << 4)
  86
  87 #ifdef CONFIG_SPL_BUILD
  88 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
  89 {
  90         int i;
  91
  92         for (i = 0; i < n / sizeof(u32); i++) {
  93                 writel(*src, dest);
  94                 src++;
  95                 dest++;
  96         }
  97 }
  98
  99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy)
 100 {
 101         u32 phy_ctl_srstn_shift = 13;
 102         u32 ctl_psrstn_shift = 11;
 103         u32 ctl_srstn_shift = 10;
 104         u32 phy_psrstn_shift = 9;
 105         u32 phy_srstn_shift = 8;
 106
 107         rk_clrsetreg(&cru->cru_softrst_con[5],
 108                      1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
 109                      1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
 110                      1 << phy_srstn_shift,
 111                      phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
 112                      ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
 113                      phy << phy_srstn_shift);
 114 }
 115
 116 static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n)
 117 {
 118         u32 phy_ctl_srstn_shift = 13;
 119
 120         rk_clrsetreg(&cru->cru_softrst_con[5],
 121                      1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
 122 }
 123
 124 static void phy_pctrl_reset(struct rk3188_cru *cru,
 125                             struct rk3288_ddr_publ *publ,
 126                             int channel)
 127 {
 128         int i;
 129
 130         ddr_reset(cru, channel, 1, 1);
 131         udelay(1);
 132         clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
 133         for (i = 0; i < 4; i++)
 134                 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
 135
 136         udelay(10);
 137         setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
 138         for (i = 0; i < 4; i++)
 139                 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
 140
 141         udelay(10);
 142         ddr_reset(cru, channel, 1, 0);
 143         udelay(10);
 144         ddr_reset(cru, channel, 0, 0);
 145         udelay(10);
 146 }
 147
 148 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
 149         u32 freq)
 150 {
 151         int i;
 152
 153         if (freq <= 250000000) {
 154                 if (freq <= 150000000)
 155                         clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 156                 else
 157                         setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 158                 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
 159                 for (i = 0; i < 4; i++)
 160                         setbits_le32(&publ->datx8[i].dxdllcr,
 161                                      DXDLLCR_DLLDIS);
 162
 163                 setbits_le32(&publ->pir, PIR_DLLBYP);
 164         } else {
 165                 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 166                 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
 167                 for (i = 0; i < 4; i++) {
 168                         clrbits_le32(&publ->datx8[i].dxdllcr,
 169                                      DXDLLCR_DLLDIS);
 170                 }
 171
 172                 clrbits_le32(&publ->pir, PIR_DLLBYP);
 173         }
 174 }
 175
 176 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
 177 {
 178         writel(DFI_INIT_START, &pctl->dfistcfg0);
 179         writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
 180                &pctl->dfistcfg1);
 181         writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
 182         writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
 183                &pctl->dfilpcfg0);
 184
 185         writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
 186         writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
 187         writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
 188         writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
 189         writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
 190         writel(1, &pctl->dfitphyupdtype0);
 191
 192         /* cs0 and cs1 write odt enable */
 193         writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
 194                &pctl->dfiodtcfg);
 195         /* odt write length */
 196         writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
 197         /* phyupd and ctrlupd disabled */
 198         writel(0, &pctl->dfiupdcfg);
 199 }
 200
 201 static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable)
 202 {
 203         uint val = 0;
 204
 205         if (enable)
 206                 val = 1 << DDR_16BIT_EN_SHIFT;
 207
 208         rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val);
 209 }
 210
 211 static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel,
 212                               bool ddr3_mode)
 213 {
 214         uint mask, val;
 215
 216         mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT;
 217         val = ddr3_mode << MSCH4_MAINDDR3_SHIFT;
 218         rk_clrsetreg(&grf->soc_con2, mask, val);
 219 }
 220
 221 static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable)
 222 {
 223         uint mask, val;
 224
 225         mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT;
 226         val = enable << RANK_TO_ROW15_EN_SHIFT;
 227         rk_clrsetreg(&grf->soc_con2, mask, val);
 228 }
 229
 230 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
 231                      struct rk3188_sdram_params *sdram_params,
 232                      struct rk3188_grf *grf)
 233 {
 234         copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
 235                     sizeof(sdram_params->pctl_timing));
 236         switch (sdram_params->base.dramtype) {
 237         case DDR3:
 238                 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
 239                         writel(sdram_params->pctl_timing.tcl - 3,
 240                                &pctl->dfitrddataen);
 241                 } else {
 242                         writel(sdram_params->pctl_timing.tcl - 2,
 243                                &pctl->dfitrddataen);
 244                 }
 245                 writel(sdram_params->pctl_timing.tcwl - 1,
 246                        &pctl->dfitphywrlat);
 247                 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
 248                        DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
 249                        1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
 250                        &pctl->mcfg);
 251                 ddr_set_ddr3_mode(grf, channel, true);
 252                 ddr_set_enable(grf, channel, true);
 253                 break;
 254         }
 255
 256         setbits_le32(&pctl->scfg, 1);
 257 }
 258
 259 static void phy_cfg(const struct chan_info *chan, int channel,
 260                     struct rk3188_sdram_params *sdram_params)
 261 {
 262         struct rk3288_ddr_publ *publ = chan->publ;
 263         struct rk3188_msch *msch = chan->msch;
 264         uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
 265         u32 dinit2;
 266         int i;
 267
 268         dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
 269         /* DDR PHY Timing */
 270         copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
 271                     sizeof(sdram_params->phy_timing));
 272         writel(sdram_params->base.noc_timing, &msch->ddrtiming);
 273         writel(0x3f, &msch->readlatency);
 274         writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
 275                DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
 276                8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
 277         writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
 278                DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
 279                &publ->ptr[1]);
 280         writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
 281                DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
 282                &publ->ptr[2]);
 283
 284         switch (sdram_params->base.dramtype) {
 285         case DDR3:
 286                 clrbits_le32(&publ->pgcr, 0x1f);
 287                 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
 288                                 DDRMD_DDR3 << DDRMD_SHIFT);
 289                 break;
 290         }
 291         if (sdram_params->base.odt) {
 292                 /*dynamic RTT enable */
 293                 for (i = 0; i < 4; i++)
 294                         setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
 295         } else {
 296                 /*dynamic RTT disable */
 297                 for (i = 0; i < 4; i++)
 298                         clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
 299         }
 300 }
 301
 302 static void phy_init(struct rk3288_ddr_publ *publ)
 303 {
 304         setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
 305                 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
 306         udelay(1);
 307         while ((readl(&publ->pgsr) &
 308                 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
 309                 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
 310                 ;
 311 }
 312
 313 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
 314                          u32 cmd, u32 arg)
 315 {
 316         writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
 317         udelay(1);
 318         while (readl(&pctl->mcmd) & START_CMD)
 319                 ;
 320 }
 321
 322 static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
 323                                    u32 rank, u32 cmd, u32 ma, u32 op)
 324 {
 325         send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
 326                      (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
 327 }
 328
 329 static void memory_init(struct rk3288_ddr_publ *publ,
 330                         u32 dramtype)
 331 {
 332         setbits_le32(&publ->pir,
 333                      (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
 334                       | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
 335                       | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
 336         udelay(1);
 337         while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
 338                 != (PGSR_IDONE | PGSR_DLDONE))
 339                 ;
 340 }
 341
 342 static void move_to_config_state(struct rk3288_ddr_publ *publ,
 343                                  struct rk3288_ddr_pctl *pctl)
 344 {
 345         unsigned int state;
 346
 347         while (1) {
 348                 state = readl(&pctl->stat) & PCTL_STAT_MSK;
 349
 350                 switch (state) {
 351                 case LOW_POWER:
 352                         writel(WAKEUP_STATE, &pctl->sctl);
 353                         while ((readl(&pctl->stat) & PCTL_STAT_MSK)
 354                                 != ACCESS)
 355                                 ;
 356                         /* wait DLL lock */
 357                         while ((readl(&publ->pgsr) & PGSR_DLDONE)
 358                                 != PGSR_DLDONE)
 359                                 ;
 360                         /*
 361                          * if at low power state,need wakeup first,
 362                          * and then enter the config, so
 363                          * fallthrough
 364                          */
 365                 case ACCESS:
 366                         /* fallthrough */
 367                 case INIT_MEM:
 368                         writel(CFG_STATE, &pctl->sctl);
 369                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
 370                                 ;
 371                         break;
 372                 case CONFIG:
 373                         return;
 374                 default:
 375                         break;
 376                 }
 377         }
 378 }
 379
 380 static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
 381                                 u32 n, struct rk3188_grf *grf)
 382 {
 383         struct rk3288_ddr_pctl *pctl = chan->pctl;
 384         struct rk3288_ddr_publ *publ = chan->publ;
 385         struct rk3188_msch *msch = chan->msch;
 386
 387         if (n == 1) {
 388                 setbits_le32(&pctl->ppcfg, 1);
 389                 ddr_set_enable(grf, channel, 1);
 390                 setbits_le32(&msch->ddrtiming, 1 << 31);
 391                 /* Data Byte disable*/
 392                 clrbits_le32(&publ->datx8[2].dxgcr, 1);
 393                 clrbits_le32(&publ->datx8[3].dxgcr, 1);
 394                 /* disable DLL */
 395                 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
 396                 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
 397         } else {
 398                 clrbits_le32(&pctl->ppcfg, 1);
 399                 ddr_set_enable(grf, channel, 0);
 400                 clrbits_le32(&msch->ddrtiming, 1 << 31);
 401                 /* Data Byte enable*/
 402                 setbits_le32(&publ->datx8[2].dxgcr, 1);
 403                 setbits_le32(&publ->datx8[3].dxgcr, 1);
 404
 405                 /* enable DLL */
 406                 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
 407                 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
 408                 /* reset DLL */
 409                 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
 410                 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
 411                 udelay(10);
 412                 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
 413                 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
 414         }
 415         setbits_le32(&pctl->dfistcfg0, 1 << 2);
 416 }
 417
 418 static int data_training(const struct chan_info *chan, int channel,
 419                          struct rk3188_sdram_params *sdram_params)
 420 {
 421         unsigned int j;
 422         int ret = 0;
 423         u32 rank;
 424         int i;
 425         u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
 426         struct rk3288_ddr_publ *publ = chan->publ;
 427         struct rk3288_ddr_pctl *pctl = chan->pctl;
 428
 429         /* disable auto refresh */
 430         writel(0, &pctl->trefi);
 431
 432         if (sdram_params->base.dramtype != LPDDR3)
 433                 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
 434         rank = sdram_params->ch[channel].rank | 1;
 435         for (j = 0; j < ARRAY_SIZE(step); j++) {
 436                 /*
 437                  * trigger QSTRN and RVTRN
 438                  * clear DTDONE status
 439                  */
 440                 setbits_le32(&publ->pir, PIR_CLRSR);
 441
 442                 /* trigger DTT */
 443                 setbits_le32(&publ->pir,
 444                              PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
 445                              PIR_CLRSR);
 446                 udelay(1);
 447                 /* wait echo byte DTDONE */
 448                 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
 449                         != rank)
 450                         ;
 451                 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
 452                         != rank)
 453                         ;
 454                 if (!(readl(&pctl->ppcfg) & 1)) {
 455                         while ((readl(&publ->datx8[2].dxgsr[0])
 456                                 & rank) != rank)
 457                                 ;
 458                         while ((readl(&publ->datx8[3].dxgsr[0])
 459                                 & rank) != rank)
 460                                 ;
 461                 }
 462                 if (readl(&publ->pgsr) &
 463                     (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
 464                         ret = -1;
 465                         break;
 466                 }
 467         }
 468         /* send some auto refresh to complement the lost while DTT */
 469         for (i = 0; i < (rank > 1 ? 8 : 4); i++)
 470                 send_command(pctl, rank, REF_CMD, 0);
 471
 472         if (sdram_params->base.dramtype != LPDDR3)
 473                 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
 474
 475         /* resume auto refresh */
 476         writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
 477
 478         return ret;
 479 }
 480
 481 static void move_to_access_state(const struct chan_info *chan)
 482 {
 483         struct rk3288_ddr_publ *publ = chan->publ;
 484         struct rk3288_ddr_pctl *pctl = chan->pctl;
 485         unsigned int state;
 486
 487         while (1) {
 488                 state = readl(&pctl->stat) & PCTL_STAT_MSK;
 489
 490                 switch (state) {
 491                 case LOW_POWER:
 492                         if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
 493                                         LP_TRIG_MASK) == 1)
 494                                 return;
 495
 496                         writel(WAKEUP_STATE, &pctl->sctl);
 497                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
 498                                 ;
 499                         /* wait DLL lock */
 500                         while ((readl(&publ->pgsr) & PGSR_DLDONE)
 501                                 != PGSR_DLDONE)
 502                                 ;
 503                         break;
 504                 case INIT_MEM:
 505                         writel(CFG_STATE, &pctl->sctl);
 506                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
 507                                 ;
 508                         /* fallthrough */
 509                 case CONFIG:
 510                         writel(GO_STATE, &pctl->sctl);
 511                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
 512                                 ;
 513                         break;
 514                 case ACCESS:
 515                         return;
 516                 default:
 517                         break;
 518                 }
 519         }
 520 }
 521
 522 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
 523                          struct rk3188_sdram_params *sdram_params)
 524 {
 525         struct rk3288_ddr_publ *publ = chan->publ;
 526
 527         if (sdram_params->ch[chnum].bk == 3)
 528                 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
 529                                 1 << PDQ_SHIFT);
 530         else
 531                 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
 532
 533         writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
 534 }
 535
 536 static void dram_all_config(const struct dram_info *dram,
 537                             struct rk3188_sdram_params *sdram_params)
 538 {
 539         unsigned int chan;
 540         u32 sys_reg = 0;
 541
 542         sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
 543         sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
 544         for (chan = 0; chan < sdram_params->num_channels; chan++) {
 545                 const struct rk3288_sdram_channel *info =
 546                         &sdram_params->ch[chan];
 547
 548                 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
 549                 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
 550                 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
 551                 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
 552                 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
 553                 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
 554                 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
 555                 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
 556                 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
 557
 558                 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
 559         }
 560         if (sdram_params->ch[0].rank == 2)
 561                 ddr_rank_2_row15en(dram->grf, 0);
 562         else
 563                 ddr_rank_2_row15en(dram->grf, 1);
 564
 565         writel(sys_reg, &dram->pmu->sys_reg[2]);
 566 }
 567
 568 static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
 569                 struct rk3188_sdram_params *sdram_params)
 570 {
 571         int reg;
 572         int need_trainig = 0;
 573         const struct chan_info *chan = &dram->chan[channel];
 574         struct rk3288_ddr_publ *publ = chan->publ;
 575
 576         ddr_rank_2_row15en(dram->grf, 0);
 577
 578         if (data_training(chan, channel, sdram_params) < 0) {
 579                 printf("first data training fail!\n");
 580                 reg = readl(&publ->datx8[0].dxgsr[0]);
 581                 /* Check the result for rank 0 */
 582                 if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
 583                         printf("data training fail!\n");
 584                         return -EIO;
 585                 }
 586
 587                 /* Check the result for rank 1 */
 588                 if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
 589                         sdram_params->ch[channel].rank = 1;
 590                         clrsetbits_le32(&publ->pgcr, 0xF << 18,
 591                                         sdram_params->ch[channel].rank << 18);
 592                         need_trainig = 1;
 593                 }
 594                 reg = readl(&publ->datx8[2].dxgsr[0]);
 595                 if (reg & (1 << 4)) {
 596                         sdram_params->ch[channel].bw = 1;
 597                         set_bandwidth_ratio(chan, channel,
 598                                             sdram_params->ch[channel].bw,
 599                                             dram->grf);
 600                         need_trainig = 1;
 601                 }
 602         }
 603         /* Assume the Die bit width are the same with the chip bit width */
 604         sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
 605
 606         if (need_trainig &&
 607             (data_training(chan, channel, sdram_params) < 0)) {
 608                 if (sdram_params->base.dramtype == LPDDR3) {
 609                         ddr_phy_ctl_reset(dram->cru, channel, 1);
 610                         udelay(10);
 611                         ddr_phy_ctl_reset(dram->cru, channel, 0);
 612                         udelay(10);
 613                 }
 614                 printf("2nd data training failed!");
 615                 return -EIO;
 616         }
 617
 618         return 0;
 619 }
 620
 621 /*
 622  * Detect ram columns and rows.
 623  * @dram: dram info struct
 624  * @channel: channel number to handle
 625  * @sdram_params: sdram parameters, function will fill in col and row values
 626  *
 627  * Returns 0 or negative on error.
 628  */
 629 static int sdram_col_row_detect(struct dram_info *dram, int channel,
 630                 struct rk3188_sdram_params *sdram_params)
 631 {
 632         int row, col;
 633         unsigned int addr;
 634         const struct chan_info *chan = &dram->chan[channel];
 635         struct rk3288_ddr_pctl *pctl = chan->pctl;
 636         struct rk3288_ddr_publ *publ = chan->publ;
 637         int ret = 0;
 638
 639         /* Detect col */
 640         for (col = 11; col >= 9; col--) {
 641                 writel(0, CONFIG_SYS_SDRAM_BASE);
 642                 addr = CONFIG_SYS_SDRAM_BASE +
 643                         (1 << (col + sdram_params->ch[channel].bw - 1));
 644                 writel(TEST_PATTEN, addr);
 645                 if ((readl(addr) == TEST_PATTEN) &&
 646                     (readl(CONFIG_SYS_SDRAM_BASE) == 0))
 647                         break;
 648         }
 649         if (col == 8) {
 650                 printf("Col detect error\n");
 651                 ret = -EINVAL;
 652                 goto out;
 653         } else {
 654                 sdram_params->ch[channel].col = col;
 655         }
 656
 657         ddr_rank_2_row15en(dram->grf, 1);
 658         move_to_config_state(publ, pctl);
 659         writel(1, &chan->msch->ddrconf);
 660         move_to_access_state(chan);
 661         /* Detect row, max 15,min13 in rk3188*/
 662         for (row = 16; row >= 13; row--) {
 663                 writel(0, CONFIG_SYS_SDRAM_BASE);
 664                 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
 665                 writel(TEST_PATTEN, addr);
 666                 if ((readl(addr) == TEST_PATTEN) &&
 667                     (readl(CONFIG_SYS_SDRAM_BASE) == 0))
 668                         break;
 669         }
 670         if (row == 12) {
 671                 printf("Row detect error\n");
 672                 ret = -EINVAL;
 673         } else {
 674                 sdram_params->ch[channel].cs1_row = row;
 675                 sdram_params->ch[channel].row_3_4 = 0;
 676                 debug("chn %d col %d, row %d\n", channel, col, row);
 677                 sdram_params->ch[channel].cs0_row = row;
 678         }
 679
 680 out:
 681         return ret;
 682 }
 683
 684 static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params)
 685 {
 686         int i, tmp, size, row, ret = 0;
 687
 688         row = sdram_params->ch[0].cs0_row;
 689         /*
 690          * RK3188 share the rank and row bit15, we use same ddr config for 15bit
 691          * and 16bit row
 692          */
 693         if (row == 16)
 694                 row = 15;
 695         tmp = sdram_params->ch[0].col - 9;
 696         tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
 697         tmp |= ((row - 13) << 4);
 698         size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
 699         for (i = 0; i < size; i++)
 700                 if (tmp == ddrconf_table[i])
 701                         break;
 702         if (i >= size) {
 703                 printf("niu config not found\n");
 704                 ret = -EINVAL;
 705         } else {
 706                 debug("niu config %d\n", i);
 707                 sdram_params->base.ddrconfig = i;
 708         }
 709
 710         return ret;
 711 }
 712
 713 static int sdram_init(struct dram_info *dram,
 714                       struct rk3188_sdram_params *sdram_params)
 715 {
 716         int channel;
 717         int zqcr;
 718         int ret;
 719
 720         if ((sdram_params->base.dramtype == DDR3 &&
 721              sdram_params->base.ddr_freq > 800000000)) {
 722                 printf("SDRAM frequency is too high!");
 723                 return -E2BIG;
 724         }
 725
 726         ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
 727         if (ret) {
 728                 printf("Could not set DDR clock\n");
 729                 return ret;
 730         }
 731
 732         for (channel = 0; channel < 1; channel++) {
 733                 const struct chan_info *chan = &dram->chan[channel];
 734                 struct rk3288_ddr_pctl *pctl = chan->pctl;
 735                 struct rk3288_ddr_publ *publ = chan->publ;
 736
 737                 phy_pctrl_reset(dram->cru, publ, channel);
 738                 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
 739
 740                 dfi_cfg(pctl, sdram_params->base.dramtype);
 741
 742                 pctl_cfg(channel, pctl, sdram_params, dram->grf);
 743
 744                 phy_cfg(chan, channel, sdram_params);
 745
 746                 phy_init(publ);
 747
 748                 writel(POWER_UP_START, &pctl->powctl);
 749                 while (!(readl(&pctl->powstat) & POWER_UP_DONE))
 750                         ;
 751
 752                 memory_init(publ, sdram_params->base.dramtype);
 753                 move_to_config_state(publ, pctl);
 754
 755                 /* Using 32bit bus width for detect */
 756                 sdram_params->ch[channel].bw = 2;
 757                 set_bandwidth_ratio(chan, channel,
 758                                     sdram_params->ch[channel].bw, dram->grf);
 759                 /*
 760                  * set cs, using n=3 for detect
 761                  * CS0, n=1
 762                  * CS1, n=2
 763                  * CS0 & CS1, n = 3
 764                  */
 765                 sdram_params->ch[channel].rank = 2,
 766                 clrsetbits_le32(&publ->pgcr, 0xF << 18,
 767                                 (sdram_params->ch[channel].rank | 1) << 18);
 768
 769                 /* DS=40ohm,ODT=155ohm */
 770                 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
 771                         2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
 772                         0x19 << PD_OUTPUT_SHIFT;
 773                 writel(zqcr, &publ->zq1cr[0]);
 774                 writel(zqcr, &publ->zq0cr[0]);
 775
 776                 /* Detect the rank and bit-width with data-training */
 777                 writel(1, &chan->msch->ddrconf);
 778                 sdram_rank_bw_detect(dram, channel, sdram_params);
 779
 780                 if (sdram_params->base.dramtype == LPDDR3) {
 781                         u32 i;
 782                         writel(0, &pctl->mrrcfg0);
 783                         for (i = 0; i < 17; i++)
 784                                 send_command_op(pctl, 1, MRR_CMD, i, 0);
 785                 }
 786                 writel(4, &chan->msch->ddrconf);
 787                 move_to_access_state(chan);
 788                 /* DDR3 and LPDDR3 are always 8 bank, no need detect */
 789                 sdram_params->ch[channel].bk = 3;
 790                 /* Detect Col and Row number*/
 791                 ret = sdram_col_row_detect(dram, channel, sdram_params);
 792                 if (ret)
 793                         goto error;
 794         }
 795         /* Find NIU DDR configuration */
 796         ret = sdram_get_niu_config(sdram_params);
 797         if (ret)
 798                 goto error;
 799
 800         dram_all_config(dram, sdram_params);
 801         debug("%s done\n", __func__);
 802
 803         return 0;
 804 error:
 805         printf("DRAM init failed!\n");
 806         hang();
 807 }
 808
 809 static int setup_sdram(struct udevice *dev)
 810 {
 811         struct dram_info *priv = dev_get_priv(dev);
 812         struct rk3188_sdram_params *params = dev_get_platdata(dev);
 813
 814         return sdram_init(priv, params);
 815 }
 816
 817 static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev)
 818 {
 819 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 820         struct rk3188_sdram_params *params = dev_get_platdata(dev);
 821         int ret;
 822
 823         /* rk3188 supports only one-channel */
 824         params->num_channels = 1;
 825         ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
 826                                  (u32 *)&params->pctl_timing,
 827                                  sizeof(params->pctl_timing) / sizeof(u32));
 828         if (ret) {
 829                 printf("%s: Cannot read rockchip,pctl-timing\n", __func__);
 830                 return -EINVAL;
 831         }
 832         ret = dev_read_u32_array(dev, "rockchip,phy-timing",
 833                                  (u32 *)&params->phy_timing,
 834                                  sizeof(params->phy_timing) / sizeof(u32));
 835         if (ret) {
 836                 printf("%s: Cannot read rockchip,phy-timing\n", __func__);
 837                 return -EINVAL;
 838         }
 839         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
 840                                  (u32 *)&params->base,
 841                                  sizeof(params->base) / sizeof(u32));
 842         if (ret) {
 843                 printf("%s: Cannot read rockchip,sdram-params\n", __func__);
 844                 return -EINVAL;
 845         }
 846         ret = regmap_init_mem(dev_ofnode(dev), &params->map);
 847         if (ret)
 848                 return ret;
 849 #endif
 850
 851         return 0;
 852 }
 853 #endif /* CONFIG_SPL_BUILD */
 854
 855 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 856 static int conv_of_platdata(struct udevice *dev)
 857 {
 858         struct rk3188_sdram_params *plat = dev_get_platdata(dev);
 859         struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat;
 860         int ret;
 861
 862         memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
 863                sizeof(plat->pctl_timing));
 864         memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
 865                sizeof(plat->phy_timing));
 866         memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
 867         /* rk3188 supports dual-channel, set default channel num to 2 */
 868         plat->num_channels = 1;
 869         ret = regmap_init_mem_platdata(dev, of_plat->reg,
 870                                        ARRAY_SIZE(of_plat->reg) / 2,
 871                                        &plat->map);
 872         if (ret)
 873                 return ret;
 874
 875         return 0;
 876 }
 877 #endif
 878
 879 static int rk3188_dmc_probe(struct udevice *dev)
 880 {
 881 #ifdef CONFIG_SPL_BUILD
 882         struct rk3188_sdram_params *plat = dev_get_platdata(dev);
 883         struct regmap *map;
 884         struct udevice *dev_clk;
 885         int ret;
 886 #endif
 887         struct dram_info *priv = dev_get_priv(dev);
 888
 889         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 890
 891 #ifdef CONFIG_SPL_BUILD
 892 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 893         ret = conv_of_platdata(dev);
 894         if (ret)
 895                 return ret;
 896 #endif
 897         map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
 898         if (IS_ERR(map))
 899                 return PTR_ERR(map);
 900         priv->chan[0].msch = regmap_get_range(map, 0);
 901
 902         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 903
 904         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
 905         priv->chan[0].publ = regmap_get_range(plat->map, 1);
 906
 907         ret = rockchip_get_clk(&dev_clk);
 908         if (ret)
 909                 return ret;
 910         priv->ddr_clk.id = CLK_DDR;
 911         ret = clk_request(dev_clk, &priv->ddr_clk);
 912         if (ret)
 913                 return ret;
 914
 915         priv->cru = rockchip_get_cru();
 916         if (IS_ERR(priv->cru))
 917                 return PTR_ERR(priv->cru);
 918         ret = setup_sdram(dev);
 919         if (ret)
 920                 return ret;
 921 #else
 922         priv->info.base = CONFIG_SYS_SDRAM_BASE;
 923         priv->info.size = rockchip_sdram_size(
 924                                 (phys_addr_t)&priv->pmu->sys_reg[2]);
 925 #endif
 926
 927         return 0;
 928 }
 929
 930 static int rk3188_dmc_get_info(struct udevice *dev, struct ram_info *info)
 931 {
 932         struct dram_info *priv = dev_get_priv(dev);
 933
 934         *info = priv->info;
 935
 936         return 0;
 937 }
 938
 939 static struct ram_ops rk3188_dmc_ops = {
 940         .get_info = rk3188_dmc_get_info,
 941 };
 942
 943 static const struct udevice_id rk3188_dmc_ids[] = {
 944         { .compatible = "rockchip,rk3188-dmc" },
 945         { }
 946 };
 947
 948 U_BOOT_DRIVER(dmc_rk3188) = {
 949         .name = "rockchip_rk3188_dmc",
 950         .id = UCLASS_RAM,
 951         .of_match = rk3188_dmc_ids,
 952         .ops = &rk3188_dmc_ops,
 953 #ifdef CONFIG_SPL_BUILD
 954         .ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata,
 955 #endif
 956         .probe = rk3188_dmc_probe,
 957         .priv_auto_alloc_size = sizeof(struct dram_info),
 958 #ifdef CONFIG_SPL_BUILD
 959         .platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params),
 960 #endif
 961 };