drivers/ram/rockchip/sdram_px30.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <debug_uart.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <ram.h>
  12 #include <syscon.h>
  13 #include <asm/io.h>
  14 #include <asm/arch-rockchip/clock.h>
  15 #include <asm/arch-rockchip/cru_px30.h>
  16 #include <asm/arch-rockchip/grf_px30.h>
  17 #include <asm/arch-rockchip/hardware.h>
  18 #include <asm/arch-rockchip/sdram.h>
  19 #include <asm/arch-rockchip/sdram_px30.h>
  20 #include <linux/delay.h>
  21
  22 struct dram_info {
  23 #ifdef CONFIG_TPL_BUILD
  24         struct ddr_pctl_regs *pctl;
  25         struct ddr_phy_regs *phy;
  26         struct px30_cru *cru;
  27         struct msch_regs *msch;
  28         struct px30_ddr_grf_regs *ddr_grf;
  29         struct px30_grf *grf;
  30 #endif
  31         struct ram_info info;
  32         struct px30_pmugrf *pmugrf;
  33 };
  34
  35 #ifdef CONFIG_TPL_BUILD
  36
  37 u8 ddr_cfg_2_rbc[] = {
  38         /*
  39          * [6:4] max row: 13+n
  40          * [3]  bank(0:4bank,1:8bank)
  41          * [2:0]    col(10+n)
  42          */
  43         ((5 << 4) | (1 << 3) | 0), /* 0 */
  44         ((5 << 4) | (1 << 3) | 1), /* 1 */
  45         ((4 << 4) | (1 << 3) | 2), /* 2 */
  46         ((3 << 4) | (1 << 3) | 3), /* 3 */
  47         ((2 << 4) | (1 << 3) | 4), /* 4 */
  48         ((5 << 4) | (0 << 3) | 2), /* 5 */
  49         ((4 << 4) | (1 << 3) | 2), /* 6 */
  50         /*((0<<3)|3),*/  /* 12 for ddr4 */
  51         /*((1<<3)|1),*/  /* 13 B,C exchange for rkvdec */
  52 };
  53
  54 /*
  55  * for ddr4 if ddrconfig=7, upctl should set 7 and noc should
  56  * set to 1 for more efficient.
  57  * noc ddrconf, upctl addrmap
  58  * 1  7
  59  * 2  8
  60  * 3  9
  61  * 12 10
  62  * 5  11
  63  */
  64 u8 d4_rbc_2_d3_rbc[] = {
  65         1, /* 7 */
  66         2, /* 8 */
  67         3, /* 9 */
  68         12, /* 10 */
  69         5, /* 11 */
  70 };
  71
  72 /*
  73  * row higher than cs should be disabled by set to 0xf
  74  * rank addrmap calculate by real cap.
  75  */
  76 u32 addrmap[][8] = {
  77         /* map0 map1,   map2,       map3,       map4,      map5
  78          * map6,        map7,       map8
  79          * -------------------------------------------------------
  80          * bk2-0       col 5-2     col 9-6    col 11-10   row 11-0
  81          * row 15-12   row 17-16   bg1,0
  82          * -------------------------------------------------------
  83          * 4,3,2       5-2         9-6                    6
  84          *                         3,2
  85          */
  86         {0x00060606, 0x00000000, 0x1f1f0000, 0x00001f1f, 0x05050505,
  87                 0x05050505, 0x00000505, 0x3f3f}, /* 0 */
  88         {0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606,
  89                 0x06060606, 0x06060606, 0x3f3f}, /* 1 */
  90         {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
  91                 0x07070707, 0x00000f07, 0x3f3f}, /* 2 */
  92         {0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
  93                 0x08080808, 0x00000f0f, 0x3f3f}, /* 3 */
  94         {0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909,
  95                 0x0f090909, 0x00000f0f, 0x3f3f}, /* 4 */
  96         {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606,
  97                 0x06060606, 0x00000606, 0x3f3f}, /* 5 */
  98         {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
  99                 0x07070707, 0x00000f0f, 0x3f3f}, /* 6 */
 100         {0x003f0808, 0x00000006, 0x1f1f0000, 0x00001f1f, 0x06060606,
 101                 0x06060606, 0x00000606, 0x0600}, /* 7 */
 102         {0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
 103                 0x07070707, 0x00000f07, 0x0700}, /* 8 */
 104         {0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
 105                 0x08080808, 0x00000f0f, 0x0801}, /* 9 */
 106         {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
 107                 0x07070707, 0x00000f07, 0x3f01}, /* 10 */
 108         {0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606,
 109                 0x06060606, 0x00000606, 0x3f00}, /* 11 */
 110         /* when ddr4 12 map to 10, when ddr3 12 unused */
 111         {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
 112                 0x07070707, 0x00000f07, 0x3f01}, /* 10 */
 113         {0x00070706, 0x00000000, 0x1f010000, 0x00001f1f, 0x06060606,
 114                 0x06060606, 0x00000606, 0x3f3f}, /* 13 */
 115 };
 116
 117 #define PMUGRF_BASE_ADDR                0xFF010000
 118 #define CRU_BASE_ADDR                   0xFF2B0000
 119 #define GRF_BASE_ADDR                   0xFF140000
 120 #define DDRC_BASE_ADDR                  0xFF600000
 121 #define DDR_PHY_BASE_ADDR               0xFF2A0000
 122 #define SERVER_MSCH0_BASE_ADDR          0xFF530000
 123 #define DDR_GRF_BASE_ADDR               0xff630000
 124
 125 struct dram_info dram_info;
 126
 127 struct px30_sdram_params sdram_configs[] = {
 128 #include        "sdram-px30-ddr3-detect-333.inc"
 129 };
 130
 131 struct ddr_phy_skew skew = {
 132 #include        "sdram-px30-ddr_skew.inc"
 133 };
 134
 135 static void rkclk_ddr_reset(struct dram_info *dram,
 136                             u32 ctl_srstn, u32 ctl_psrstn,
 137                             u32 phy_srstn, u32 phy_psrstn)
 138 {
 139         writel(upctl2_srstn_req(ctl_srstn) | upctl2_psrstn_req(ctl_psrstn) |
 140                upctl2_asrstn_req(ctl_srstn),
 141                &dram->cru->softrst_con[1]);
 142         writel(ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn),
 143                &dram->cru->softrst_con[2]);
 144 }
 145
 146 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz)
 147 {
 148         unsigned int refdiv, postdiv1, postdiv2, fbdiv;
 149         int delay = 1000;
 150         u32 mhz = hz / MHz;
 151
 152         refdiv = 1;
 153         if (mhz <= 300) {
 154                 postdiv1 = 4;
 155                 postdiv2 = 2;
 156         } else if (mhz <= 400) {
 157                 postdiv1 = 6;
 158                 postdiv2 = 1;
 159         } else if (mhz <= 600) {
 160                 postdiv1 = 4;
 161                 postdiv2 = 1;
 162         } else if (mhz <= 800) {
 163                 postdiv1 = 3;
 164                 postdiv2 = 1;
 165         } else if (mhz <= 1600) {
 166                 postdiv1 = 2;
 167                 postdiv2 = 1;
 168         } else {
 169                 postdiv1 = 1;
 170                 postdiv2 = 1;
 171         }
 172         fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24;
 173
 174         writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode);
 175
 176         writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0);
 177         writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv),
 178                &dram->cru->pll[1].con1);
 179
 180         while (delay > 0) {
 181                 udelay(1);
 182                 if (LOCK(readl(&dram->cru->pll[1].con1)))
 183                         break;
 184                 delay--;
 185         }
 186
 187         writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode);
 188 }
 189
 190 static void rkclk_configure_ddr(struct dram_info *dram,
 191                                 struct px30_sdram_params *sdram_params)
 192 {
 193         /* for inno ddr phy need 2*freq */
 194         rkclk_set_dpll(dram,  sdram_params->base.ddr_freq * MHz * 2);
 195 }
 196
 197 /* return ddrconfig value
 198  *       (-1), find ddrconfig fail
 199  *       other, the ddrconfig value
 200  * only support cs0_row >= cs1_row
 201  */
 202 static unsigned int calculate_ddrconfig(struct px30_sdram_params *sdram_params)
 203 {
 204         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 205         u32 bw, die_bw, col, bank;
 206         u32 i, tmp;
 207         u32 ddrconf = -1;
 208
 209         bw = cap_info->bw;
 210         die_bw = cap_info->dbw;
 211         col = cap_info->col;
 212         bank = cap_info->bk;
 213
 214         if (sdram_params->base.dramtype == DDR4) {
 215                 if (die_bw == 0)
 216                         ddrconf = 7 + bw;
 217                 else
 218                         ddrconf = 12 - bw;
 219                 ddrconf = d4_rbc_2_d3_rbc[ddrconf - 7];
 220         } else {
 221                 tmp = ((bank - 2) << 3) | (col + bw - 10);
 222                 for (i = 0; i < 7; i++)
 223                         if ((ddr_cfg_2_rbc[i] & 0xf) == tmp) {
 224                                 ddrconf = i;
 225                                 break;
 226                         }
 227                 if (i > 6)
 228                         printascii("calculate ddrconfig error\n");
 229         }
 230
 231         return ddrconf;
 232 }
 233
 234 /*
 235  * calculate controller dram address map, and setting to register.
 236  * argument sdram_params->ch.ddrconf must be right value before
 237  * call this function.
 238  */
 239 static void set_ctl_address_map(struct dram_info *dram,
 240                                 struct px30_sdram_params *sdram_params)
 241 {
 242         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 243         void __iomem *pctl_base = dram->pctl;
 244         u32 cs_pst, bg, max_row, ddrconf;
 245         u32 i;
 246
 247         if (sdram_params->base.dramtype == DDR4)
 248                 /*
 249                  * DDR4 8bit dram BG = 2(4bank groups),
 250                  * 16bit dram BG = 1 (2 bank groups)
 251                  */
 252                 bg = (cap_info->dbw == 0) ? 2 : 1;
 253         else
 254                 bg = 0;
 255
 256         cs_pst = cap_info->bw + cap_info->col +
 257                 bg + cap_info->bk + cap_info->cs0_row;
 258         if (cs_pst >= 32 || cap_info->rank == 1)
 259                 writel(0x1f, pctl_base + DDR_PCTL2_ADDRMAP0);
 260         else
 261                 writel(cs_pst - 8, pctl_base + DDR_PCTL2_ADDRMAP0);
 262
 263         ddrconf = cap_info->ddrconfig;
 264         if (sdram_params->base.dramtype == DDR4) {
 265                 for (i = 0; i < ARRAY_SIZE(d4_rbc_2_d3_rbc); i++) {
 266                         if (d4_rbc_2_d3_rbc[i] == ddrconf) {
 267                                 ddrconf = 7 + i;
 268                                 break;
 269                         }
 270                 }
 271         }
 272
 273         sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP1),
 274                           &addrmap[ddrconf][0], 8 * 4);
 275         max_row = cs_pst - 1 - 8 - (addrmap[ddrconf][5] & 0xf);
 276
 277         if (max_row < 12)
 278                 printascii("set addrmap fail\n");
 279         /* need to disable row ahead of rank by set to 0xf */
 280         for (i = 17; i > max_row; i--)
 281                 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 +
 282                         ((i - 12) * 8 / 32) * 4,
 283                         0xf << ((i - 12) * 8 % 32),
 284                         0xf << ((i - 12) * 8 % 32));
 285
 286         if ((sdram_params->base.dramtype == LPDDR3 ||
 287              sdram_params->base.dramtype == LPDDR2) &&
 288                  cap_info->row_3_4)
 289                 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);
 290         if (sdram_params->base.dramtype == DDR4 && cap_info->bw != 0x2)
 291                 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);
 292 }
 293
 294 /*
 295  * rank = 1: cs0
 296  * rank = 2: cs1
 297  */
 298 int read_mr(struct dram_info *dram, u32 rank, u32 mr_num)
 299 {
 300         void __iomem *ddr_grf_base = dram->ddr_grf;
 301
 302         pctl_read_mr(dram->pctl, rank, mr_num);
 303
 304         return (readl(ddr_grf_base + DDR_GRF_STATUS(0)) & 0xff);
 305 }
 306
 307 #define MIN(a, b)       (((a) > (b)) ? (b) : (a))
 308 #define MAX(a, b)       (((a) > (b)) ? (a) : (b))
 309 static u32 check_rd_gate(struct dram_info *dram)
 310 {
 311         void __iomem *phy_base = dram->phy;
 312
 313         u32 max_val = 0;
 314         u32 min_val = 0xff;
 315         u32 gate[4];
 316         u32 i, bw;
 317
 318         bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf;
 319         switch (bw) {
 320         case 0x1:
 321                 bw = 1;
 322                 break;
 323         case 0x3:
 324                 bw = 2;
 325                 break;
 326         case 0xf:
 327         default:
 328                 bw = 4;
 329                 break;
 330         }
 331
 332         for (i = 0; i < bw; i++) {
 333                 gate[i] = readl(PHY_REG(phy_base, 0xfb + i));
 334                 max_val = MAX(max_val, gate[i]);
 335                 min_val = MIN(min_val, gate[i]);
 336         }
 337
 338         if (max_val > 0x80 || min_val < 0x20)
 339                 return -1;
 340         else
 341                 return 0;
 342 }
 343
 344 static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
 345 {
 346         void __iomem *pctl_base = dram->pctl;
 347         u32 dis_auto_zq = 0;
 348         u32 pwrctl;
 349         u32 ret;
 350
 351         /* disable auto low-power */
 352         pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
 353         writel(0, pctl_base + DDR_PCTL2_PWRCTL);
 354
 355         dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl);
 356
 357         ret = phy_data_training(dram->phy, cs, dramtype);
 358
 359         pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq);
 360
 361         /* restore auto low-power */
 362         writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
 363
 364         return ret;
 365 }
 366
 367 static void dram_set_bw(struct dram_info *dram, u32 bw)
 368 {
 369         phy_dram_set_bw(dram->phy, bw);
 370 }
 371
 372 static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)
 373 {
 374         writel(ddrconfig | (ddrconfig << 8), &dram->msch->deviceconf);
 375         rk_clrsetreg(&dram->grf->soc_noc_con[1], 0x3 << 14, 0 << 14);
 376 }
 377
 378 static void sdram_msch_config(struct msch_regs *msch,
 379                               struct sdram_msch_timings *noc_timings,
 380                               struct sdram_cap_info *cap_info,
 381                               struct sdram_base_params *base)
 382 {
 383         u64 cs_cap[2];
 384
 385         cs_cap[0] = sdram_get_cs_cap(cap_info, 0, base->dramtype);
 386         cs_cap[1] = sdram_get_cs_cap(cap_info, 1, base->dramtype);
 387         writel(((((cs_cap[1] >> 20) / 64) & 0xff) << 8) |
 388                         (((cs_cap[0] >> 20) / 64) & 0xff),
 389                         &msch->devicesize);
 390
 391         writel(noc_timings->ddrtiminga0.d32,
 392                &msch->ddrtiminga0);
 393         writel(noc_timings->ddrtimingb0.d32,
 394                &msch->ddrtimingb0);
 395         writel(noc_timings->ddrtimingc0.d32,
 396                &msch->ddrtimingc0);
 397         writel(noc_timings->devtodev0.d32,
 398                &msch->devtodev0);
 399         writel(noc_timings->ddrmode.d32, &msch->ddrmode);
 400         writel(noc_timings->ddr4timing.d32,
 401                &msch->ddr4timing);
 402         writel(noc_timings->agingx0, &msch->agingx0);
 403         writel(noc_timings->agingx0, &msch->aging0);
 404         writel(noc_timings->agingx0, &msch->aging1);
 405         writel(noc_timings->agingx0, &msch->aging2);
 406         writel(noc_timings->agingx0, &msch->aging3);
 407 }
 408
 409 static void dram_all_config(struct dram_info *dram,
 410                             struct px30_sdram_params *sdram_params)
 411 {
 412         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 413         u32 sys_reg2 = 0;
 414         u32 sys_reg3 = 0;
 415
 416         set_ddrconfig(dram, cap_info->ddrconfig);
 417         sdram_org_config(cap_info, &sdram_params->base, &sys_reg2,
 418                          &sys_reg3, 0);
 419         writel(sys_reg2, &dram->pmugrf->os_reg[2]);
 420         writel(sys_reg3, &dram->pmugrf->os_reg[3]);
 421         sdram_msch_config(dram->msch, &sdram_params->ch.noc_timings, cap_info,
 422                           &sdram_params->base);
 423 }
 424
 425 static void enable_low_power(struct dram_info *dram,
 426                              struct px30_sdram_params *sdram_params)
 427 {
 428         void __iomem *pctl_base = dram->pctl;
 429         void __iomem *phy_base = dram->phy;
 430         void __iomem *ddr_grf_base = dram->ddr_grf;
 431         u32 grf_lp_con;
 432
 433         /*
 434          * bit0: grf_upctl_axi_cg_en = 1 enable upctl2 axi clk auto gating
 435          * bit1: grf_upctl_apb_cg_en = 1 ungated axi,core clk for apb access
 436          * bit2: grf_upctl_core_cg_en = 1 enable upctl2 core clk auto gating
 437          * bit3: grf_selfref_type2_en = 0 disable core clk gating when type2 sr
 438          * bit4: grf_upctl_syscreq_cg_en = 1
 439          *       ungating coreclk when c_sysreq assert
 440          * bit8-11: grf_auto_sr_dly = 6
 441          */
 442         writel(0x1f1f0617, &dram->ddr_grf->ddr_grf_con[1]);
 443
 444         if (sdram_params->base.dramtype == DDR4)
 445                 grf_lp_con = (0x7 << 16) | (1 << 1);
 446         else if (sdram_params->base.dramtype == DDR3)
 447                 grf_lp_con = (0x7 << 16) | (1 << 0);
 448         else
 449                 grf_lp_con = (0x7 << 16) | (1 << 2);
 450
 451         /* en lpckdis_en */
 452         grf_lp_con = grf_lp_con | (0x1 << (9 + 16)) | (0x1 << 9);
 453         writel(grf_lp_con, ddr_grf_base + DDR_GRF_LP_CON);
 454
 455         /* off digit module clock when enter power down */
 456         setbits_le32(PHY_REG(phy_base, 7), 1 << 7);
 457
 458         /* enable sr, pd */
 459         if (PD_IDLE == 0)
 460                 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
 461         else
 462                 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
 463         if (SR_IDLE == 0)
 464                 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
 465         else
 466                 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
 467         setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3));
 468 }
 469
 470 /*
 471  * pre_init: 0: pre init for dram cap detect
 472  * 1: detect correct cap(except cs1 row)info, than reinit
 473  * 2: after reinit, we detect cs1_row, if cs1_row not equal
 474  *    to cs0_row and cs is in middle on ddrconf map, we need
 475  *    to reinit dram, than set the correct ddrconf.
 476  */
 477 static int sdram_init_(struct dram_info *dram,
 478                        struct px30_sdram_params *sdram_params, u32 pre_init)
 479 {
 480         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 481         void __iomem *pctl_base = dram->pctl;
 482
 483         rkclk_ddr_reset(dram, 1, 1, 1, 1);
 484         udelay(10);
 485         /*
 486          * dereset ddr phy psrstn to config pll,
 487          * if using phy pll psrstn must be dereset
 488          * before config pll
 489          */
 490         rkclk_ddr_reset(dram, 1, 1, 1, 0);
 491         rkclk_configure_ddr(dram, sdram_params);
 492
 493         /* release phy srst to provide clk to ctrl */
 494         rkclk_ddr_reset(dram, 1, 1, 0, 0);
 495         udelay(10);
 496         phy_soft_reset(dram->phy);
 497         /* release ctrl presetn, and config ctl registers */
 498         rkclk_ddr_reset(dram, 1, 0, 0, 0);
 499         pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE);
 500         cap_info->ddrconfig = calculate_ddrconfig(sdram_params);
 501         set_ctl_address_map(dram, sdram_params);
 502         phy_cfg(dram->phy, &sdram_params->phy_regs, sdram_params->skew,
 503                 &sdram_params->base, cap_info->bw);
 504
 505         /* enable dfi_init_start to init phy after ctl srstn deassert */
 506         setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));
 507
 508         rkclk_ddr_reset(dram, 0, 0, 0, 0);
 509         /* wait for dfi_init_done and dram init complete */
 510         while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
 511                 continue;
 512
 513         if (sdram_params->base.dramtype == LPDDR3)
 514                 pctl_write_mr(dram->pctl, 3, 11, 3, LPDDR3);
 515
 516         /* do ddr gate training */
 517 redo_cs0_training:
 518         if (data_training(dram, 0, sdram_params->base.dramtype) != 0) {
 519                 if (pre_init != 0)
 520                         printascii("DTT cs0 error\n");
 521                 return -1;
 522         }
 523         if (check_rd_gate(dram)) {
 524                 printascii("re training cs0");
 525                 goto redo_cs0_training;
 526         }
 527
 528         if (sdram_params->base.dramtype == LPDDR3) {
 529                 if ((read_mr(dram, 1, 8) & 0x3) != 0x3)
 530                         return -1;
 531         } else if (sdram_params->base.dramtype == LPDDR2) {
 532                 if ((read_mr(dram, 1, 8) & 0x3) != 0x0)
 533                         return -1;
 534         }
 535         /* for px30: when 2cs, both 2 cs should be training */
 536         if (pre_init != 0 && cap_info->rank == 2) {
 537 redo_cs1_training:
 538                 if (data_training(dram, 1, sdram_params->base.dramtype) != 0) {
 539                         printascii("DTT cs1 error\n");
 540                         return -1;
 541                 }
 542                 if (check_rd_gate(dram)) {
 543                         printascii("re training cs1");
 544                         goto redo_cs1_training;
 545                 }
 546         }
 547
 548         if (sdram_params->base.dramtype == DDR4)
 549                 pctl_write_vrefdq(dram->pctl, 0x3, 5670,
 550                                   sdram_params->base.dramtype);
 551
 552         dram_all_config(dram, sdram_params);
 553         enable_low_power(dram, sdram_params);
 554
 555         return 0;
 556 }
 557
 558 static int dram_detect_cap(struct dram_info *dram,
 559                            struct px30_sdram_params *sdram_params,
 560                            unsigned char channel)
 561 {
 562         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 563
 564         /*
 565          * for ddr3: ddrconf = 3
 566          * for ddr4: ddrconf = 12
 567          * for lpddr3: ddrconf = 3
 568          * default bw = 1
 569          */
 570         u32 bk, bktmp;
 571         u32 col, coltmp;
 572         u32 rowtmp;
 573         u32 cs;
 574         u32 bw = 1;
 575         u32 dram_type = sdram_params->base.dramtype;
 576
 577         if (dram_type != DDR4) {
 578                 /* detect col and bk for ddr3/lpddr3 */
 579                 coltmp = 12;
 580                 bktmp = 3;
 581                 if (dram_type == LPDDR2)
 582                         rowtmp = 15;
 583                 else
 584                         rowtmp = 16;
 585
 586                 if (sdram_detect_col(cap_info, coltmp) != 0)
 587                         goto cap_err;
 588                 sdram_detect_bank(cap_info, coltmp, bktmp);
 589                 sdram_detect_dbw(cap_info, dram_type);
 590         } else {
 591                 /* detect bg for ddr4 */
 592                 coltmp = 10;
 593                 bktmp = 4;
 594                 rowtmp = 17;
 595
 596                 col = 10;
 597                 bk = 2;
 598                 cap_info->col = col;
 599                 cap_info->bk = bk;
 600                 sdram_detect_bg(cap_info, coltmp);
 601         }
 602
 603         /* detect row */
 604         if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0)
 605                 goto cap_err;
 606
 607         /* detect row_3_4 */
 608         sdram_detect_row_3_4(cap_info, coltmp, bktmp);
 609
 610         /* bw and cs detect using data training */
 611         if (data_training(dram, 1, dram_type) == 0)
 612                 cs = 1;
 613         else
 614                 cs = 0;
 615         cap_info->rank = cs + 1;
 616
 617         dram_set_bw(dram, 2);
 618         if (data_training(dram, 0, dram_type) == 0)
 619                 bw = 2;
 620         else
 621                 bw = 1;
 622         cap_info->bw = bw;
 623
 624         cap_info->cs0_high16bit_row = cap_info->cs0_row;
 625         if (cs) {
 626                 cap_info->cs1_row = cap_info->cs0_row;
 627                 cap_info->cs1_high16bit_row = cap_info->cs0_row;
 628         } else {
 629                 cap_info->cs1_row = 0;
 630                 cap_info->cs1_high16bit_row = 0;
 631         }
 632
 633         return 0;
 634 cap_err:
 635         return -1;
 636 }
 637
 638 /* return: 0 = success, other = fail */
 639 static int sdram_init_detect(struct dram_info *dram,
 640                              struct px30_sdram_params *sdram_params)
 641 {
 642         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 643         u32 ret;
 644         u32 sys_reg = 0;
 645         u32 sys_reg3 = 0;
 646
 647         if (sdram_init_(dram, sdram_params, 0) != 0)
 648                 return -1;
 649
 650         if (dram_detect_cap(dram, sdram_params, 0) != 0)
 651                 return -1;
 652
 653         /* modify bw, cs related timing */
 654         pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info,
 655                                    sdram_params->base.dramtype);
 656         /* reinit sdram by real dram cap */
 657         ret = sdram_init_(dram, sdram_params, 1);
 658         if (ret != 0)
 659                 goto out;
 660
 661         /* redetect cs1 row */
 662         sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype);
 663         if (cap_info->cs1_row) {
 664                 sys_reg = readl(&dram->pmugrf->os_reg[2]);
 665                 sys_reg3 = readl(&dram->pmugrf->os_reg[3]);
 666                 SYS_REG_ENC_CS1_ROW(cap_info->cs1_row,
 667                                     sys_reg, sys_reg3, 0);
 668                 writel(sys_reg, &dram->pmugrf->os_reg[2]);
 669                 writel(sys_reg3, &dram->pmugrf->os_reg[3]);
 670         }
 671
 672         ret = sdram_detect_high_row(cap_info);
 673
 674 out:
 675         return ret;
 676 }
 677
 678 struct px30_sdram_params
 679                 *get_default_sdram_config(void)
 680 {
 681         sdram_configs[0].skew = &skew;
 682
 683         return &sdram_configs[0];
 684 }
 685
 686 /* return: 0 = success, other = fail */
 687 int sdram_init(void)
 688 {
 689         struct px30_sdram_params *sdram_params;
 690         int ret = 0;
 691
 692         dram_info.phy = (void *)DDR_PHY_BASE_ADDR;
 693         dram_info.pctl = (void *)DDRC_BASE_ADDR;
 694         dram_info.grf = (void *)GRF_BASE_ADDR;
 695         dram_info.cru = (void *)CRU_BASE_ADDR;
 696         dram_info.msch = (void *)SERVER_MSCH0_BASE_ADDR;
 697         dram_info.ddr_grf = (void *)DDR_GRF_BASE_ADDR;
 698         dram_info.pmugrf = (void *)PMUGRF_BASE_ADDR;
 699
 700         sdram_params = get_default_sdram_config();
 701         ret = sdram_init_detect(&dram_info, sdram_params);
 702
 703         if (ret)
 704                 goto error;
 705
 706         sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base);
 707
 708         printascii("out\n");
 709         return ret;
 710 error:
 711         return (-1);
 712 }
 713 #else
 714
 715 static int px30_dmc_probe(struct udevice *dev)
 716 {
 717         struct dram_info *priv = dev_get_priv(dev);
 718
 719         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 720         debug("%s: grf=%p\n", __func__, priv->pmugrf);
 721         priv->info.base = CONFIG_SYS_SDRAM_BASE;
 722         priv->info.size =
 723                 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
 724
 725         return 0;
 726 }
 727
 728 static int px30_dmc_get_info(struct udevice *dev, struct ram_info *info)
 729 {
 730         struct dram_info *priv = dev_get_priv(dev);
 731
 732         *info = priv->info;
 733
 734         return 0;
 735 }
 736
 737 static struct ram_ops px30_dmc_ops = {
 738         .get_info = px30_dmc_get_info,
 739 };
 740
 741 static const struct udevice_id px30_dmc_ids[] = {
 742         { .compatible = "rockchip,px30-dmc" },
 743         { }
 744 };
 745
 746 U_BOOT_DRIVER(dmc_px30) = {
 747         .name = "rockchip_px30_dmc",
 748         .id = UCLASS_RAM,
 749         .of_match = px30_dmc_ids,
 750         .ops = &px30_dmc_ops,
 751         .probe = px30_dmc_probe,
 752         .priv_auto_alloc_size = sizeof(struct dram_info),
 753 };
 754 #endif /* CONFIG_TPL_BUILD */