drivers/ram/rockchip/sdram_px30.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <debug_uart.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <ram.h>
  12 #include <syscon.h>
  13 #include <asm/io.h>
  14 #include <asm/arch-rockchip/clock.h>
  15 #include <asm/arch-rockchip/cru_px30.h>
  16 #include <asm/arch-rockchip/grf_px30.h>
  17 #include <asm/arch-rockchip/hardware.h>
  18 #include <asm/arch-rockchip/sdram.h>
  19 #include <asm/arch-rockchip/sdram_px30.h>
  20
  21 struct dram_info {
  22 #ifdef CONFIG_TPL_BUILD
  23         struct ddr_pctl_regs *pctl;
  24         struct ddr_phy_regs *phy;
  25         struct px30_cru *cru;
  26         struct msch_regs *msch;
  27         struct px30_ddr_grf_regs *ddr_grf;
  28         struct px30_grf *grf;
  29 #endif
  30         struct ram_info info;
  31         struct px30_pmugrf *pmugrf;
  32 };
  33
  34 #ifdef CONFIG_TPL_BUILD
  35
  36 u8 ddr_cfg_2_rbc[] = {
  37         /*
  38          * [6:4] max row: 13+n
  39          * [3]  bank(0:4bank,1:8bank)
  40          * [2:0]    col(10+n)
  41          */
  42         ((5 << 4) | (1 << 3) | 0), /* 0 */
  43         ((5 << 4) | (1 << 3) | 1), /* 1 */
  44         ((4 << 4) | (1 << 3) | 2), /* 2 */
  45         ((3 << 4) | (1 << 3) | 3), /* 3 */
  46         ((2 << 4) | (1 << 3) | 4), /* 4 */
  47         ((5 << 4) | (0 << 3) | 2), /* 5 */
  48         ((4 << 4) | (1 << 3) | 2), /* 6 */
  49         /*((0<<3)|3),*/  /* 12 for ddr4 */
  50         /*((1<<3)|1),*/  /* 13 B,C exchange for rkvdec */
  51 };
  52
  53 /*
  54  * for ddr4 if ddrconfig=7, upctl should set 7 and noc should
  55  * set to 1 for more efficient.
  56  * noc ddrconf, upctl addrmap
  57  * 1  7
  58  * 2  8
  59  * 3  9
  60  * 12 10
  61  * 5  11
  62  */
  63 u8 d4_rbc_2_d3_rbc[] = {
  64         1, /* 7 */
  65         2, /* 8 */
  66         3, /* 9 */
  67         12, /* 10 */
  68         5, /* 11 */
  69 };
  70
  71 /*
  72  * row higher than cs should be disabled by set to 0xf
  73  * rank addrmap calculate by real cap.
  74  */
  75 u32 addrmap[][8] = {
  76         /* map0 map1,   map2,       map3,       map4,      map5
  77          * map6,        map7,       map8
  78          * -------------------------------------------------------
  79          * bk2-0       col 5-2     col 9-6    col 11-10   row 11-0
  80          * row 15-12   row 17-16   bg1,0
  81          * -------------------------------------------------------
  82          * 4,3,2       5-2         9-6                    6
  83          *                         3,2
  84          */
  85         {0x00060606, 0x00000000, 0x1f1f0000, 0x00001f1f, 0x05050505,
  86                 0x05050505, 0x00000505, 0x3f3f}, /* 0 */
  87         {0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606,
  88                 0x06060606, 0x06060606, 0x3f3f}, /* 1 */
  89         {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
  90                 0x07070707, 0x00000f07, 0x3f3f}, /* 2 */
  91         {0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
  92                 0x08080808, 0x00000f0f, 0x3f3f}, /* 3 */
  93         {0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909,
  94                 0x0f090909, 0x00000f0f, 0x3f3f}, /* 4 */
  95         {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606,
  96                 0x06060606, 0x00000606, 0x3f3f}, /* 5 */
  97         {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
  98                 0x07070707, 0x00000f0f, 0x3f3f}, /* 6 */
  99         {0x003f0808, 0x00000006, 0x1f1f0000, 0x00001f1f, 0x06060606,
 100                 0x06060606, 0x00000606, 0x0600}, /* 7 */
 101         {0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
 102                 0x07070707, 0x00000f07, 0x0700}, /* 8 */
 103         {0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
 104                 0x08080808, 0x00000f0f, 0x0801}, /* 9 */
 105         {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
 106                 0x07070707, 0x00000f07, 0x3f01}, /* 10 */
 107         {0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606,
 108                 0x06060606, 0x00000606, 0x3f00}, /* 11 */
 109         /* when ddr4 12 map to 10, when ddr3 12 unused */
 110         {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
 111                 0x07070707, 0x00000f07, 0x3f01}, /* 10 */
 112         {0x00070706, 0x00000000, 0x1f010000, 0x00001f1f, 0x06060606,
 113                 0x06060606, 0x00000606, 0x3f3f}, /* 13 */
 114 };
 115
 116 #define PMUGRF_BASE_ADDR                0xFF010000
 117 #define CRU_BASE_ADDR                   0xFF2B0000
 118 #define GRF_BASE_ADDR                   0xFF140000
 119 #define DDRC_BASE_ADDR                  0xFF600000
 120 #define DDR_PHY_BASE_ADDR               0xFF2A0000
 121 #define SERVER_MSCH0_BASE_ADDR          0xFF530000
 122 #define DDR_GRF_BASE_ADDR               0xff630000
 123
 124 struct dram_info dram_info;
 125
 126 struct px30_sdram_params sdram_configs[] = {
 127 #include        "sdram-px30-ddr3-detect-333.inc"
 128 };
 129
 130 struct ddr_phy_skew skew = {
 131 #include        "sdram-px30-ddr_skew.inc"
 132 };
 133
 134 static void rkclk_ddr_reset(struct dram_info *dram,
 135                             u32 ctl_srstn, u32 ctl_psrstn,
 136                             u32 phy_srstn, u32 phy_psrstn)
 137 {
 138         writel(upctl2_srstn_req(ctl_srstn) | upctl2_psrstn_req(ctl_psrstn) |
 139                upctl2_asrstn_req(ctl_srstn),
 140                &dram->cru->softrst_con[1]);
 141         writel(ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn),
 142                &dram->cru->softrst_con[2]);
 143 }
 144
 145 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz)
 146 {
 147         unsigned int refdiv, postdiv1, postdiv2, fbdiv;
 148         int delay = 1000;
 149         u32 mhz = hz / MHz;
 150
 151         refdiv = 1;
 152         if (mhz <= 300) {
 153                 postdiv1 = 4;
 154                 postdiv2 = 2;
 155         } else if (mhz <= 400) {
 156                 postdiv1 = 6;
 157                 postdiv2 = 1;
 158         } else if (mhz <= 600) {
 159                 postdiv1 = 4;
 160                 postdiv2 = 1;
 161         } else if (mhz <= 800) {
 162                 postdiv1 = 3;
 163                 postdiv2 = 1;
 164         } else if (mhz <= 1600) {
 165                 postdiv1 = 2;
 166                 postdiv2 = 1;
 167         } else {
 168                 postdiv1 = 1;
 169                 postdiv2 = 1;
 170         }
 171         fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24;
 172
 173         writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode);
 174
 175         writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0);
 176         writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv),
 177                &dram->cru->pll[1].con1);
 178
 179         while (delay > 0) {
 180                 udelay(1);
 181                 if (LOCK(readl(&dram->cru->pll[1].con1)))
 182                         break;
 183                 delay--;
 184         }
 185
 186         writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode);
 187 }
 188
 189 static void rkclk_configure_ddr(struct dram_info *dram,
 190                                 struct px30_sdram_params *sdram_params)
 191 {
 192         /* for inno ddr phy need 2*freq */
 193         rkclk_set_dpll(dram,  sdram_params->base.ddr_freq * MHz * 2);
 194 }
 195
 196 /* return ddrconfig value
 197  *       (-1), find ddrconfig fail
 198  *       other, the ddrconfig value
 199  * only support cs0_row >= cs1_row
 200  */
 201 static unsigned int calculate_ddrconfig(struct px30_sdram_params *sdram_params)
 202 {
 203         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 204         u32 bw, die_bw, col, bank;
 205         u32 i, tmp;
 206         u32 ddrconf = -1;
 207
 208         bw = cap_info->bw;
 209         die_bw = cap_info->dbw;
 210         col = cap_info->col;
 211         bank = cap_info->bk;
 212
 213         if (sdram_params->base.dramtype == DDR4) {
 214                 if (die_bw == 0)
 215                         ddrconf = 7 + bw;
 216                 else
 217                         ddrconf = 12 - bw;
 218                 ddrconf = d4_rbc_2_d3_rbc[ddrconf - 7];
 219         } else {
 220                 tmp = ((bank - 2) << 3) | (col + bw - 10);
 221                 for (i = 0; i < 7; i++)
 222                         if ((ddr_cfg_2_rbc[i] & 0xf) == tmp) {
 223                                 ddrconf = i;
 224                                 break;
 225                         }
 226                 if (i > 6)
 227                         printascii("calculate ddrconfig error\n");
 228         }
 229
 230         return ddrconf;
 231 }
 232
 233 /*
 234  * calculate controller dram address map, and setting to register.
 235  * argument sdram_params->ch.ddrconf must be right value before
 236  * call this function.
 237  */
 238 static void set_ctl_address_map(struct dram_info *dram,
 239                                 struct px30_sdram_params *sdram_params)
 240 {
 241         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 242         void __iomem *pctl_base = dram->pctl;
 243         u32 cs_pst, bg, max_row, ddrconf;
 244         u32 i;
 245
 246         if (sdram_params->base.dramtype == DDR4)
 247                 /*
 248                  * DDR4 8bit dram BG = 2(4bank groups),
 249                  * 16bit dram BG = 1 (2 bank groups)
 250                  */
 251                 bg = (cap_info->dbw == 0) ? 2 : 1;
 252         else
 253                 bg = 0;
 254
 255         cs_pst = cap_info->bw + cap_info->col +
 256                 bg + cap_info->bk + cap_info->cs0_row;
 257         if (cs_pst >= 32 || cap_info->rank == 1)
 258                 writel(0x1f, pctl_base + DDR_PCTL2_ADDRMAP0);
 259         else
 260                 writel(cs_pst - 8, pctl_base + DDR_PCTL2_ADDRMAP0);
 261
 262         ddrconf = cap_info->ddrconfig;
 263         if (sdram_params->base.dramtype == DDR4) {
 264                 for (i = 0; i < ARRAY_SIZE(d4_rbc_2_d3_rbc); i++) {
 265                         if (d4_rbc_2_d3_rbc[i] == ddrconf) {
 266                                 ddrconf = 7 + i;
 267                                 break;
 268                         }
 269                 }
 270         }
 271
 272         sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP1),
 273                           &addrmap[ddrconf][0], 8 * 4);
 274         max_row = cs_pst - 1 - 8 - (addrmap[ddrconf][5] & 0xf);
 275
 276         if (max_row < 12)
 277                 printascii("set addrmap fail\n");
 278         /* need to disable row ahead of rank by set to 0xf */
 279         for (i = 17; i > max_row; i--)
 280                 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 +
 281                         ((i - 12) * 8 / 32) * 4,
 282                         0xf << ((i - 12) * 8 % 32),
 283                         0xf << ((i - 12) * 8 % 32));
 284
 285         if ((sdram_params->base.dramtype == LPDDR3 ||
 286              sdram_params->base.dramtype == LPDDR2) &&
 287                  cap_info->row_3_4)
 288                 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);
 289         if (sdram_params->base.dramtype == DDR4 && cap_info->bw != 0x2)
 290                 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);
 291 }
 292
 293 /*
 294  * rank = 1: cs0
 295  * rank = 2: cs1
 296  */
 297 int read_mr(struct dram_info *dram, u32 rank, u32 mr_num)
 298 {
 299         void __iomem *ddr_grf_base = dram->ddr_grf;
 300
 301         pctl_read_mr(dram->pctl, rank, mr_num);
 302
 303         return (readl(ddr_grf_base + DDR_GRF_STATUS(0)) & 0xff);
 304 }
 305
 306 #define MIN(a, b)       (((a) > (b)) ? (b) : (a))
 307 #define MAX(a, b)       (((a) > (b)) ? (a) : (b))
 308 static u32 check_rd_gate(struct dram_info *dram)
 309 {
 310         void __iomem *phy_base = dram->phy;
 311
 312         u32 max_val = 0;
 313         u32 min_val = 0xff;
 314         u32 gate[4];
 315         u32 i, bw;
 316
 317         bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf;
 318         switch (bw) {
 319         case 0x1:
 320                 bw = 1;
 321                 break;
 322         case 0x3:
 323                 bw = 2;
 324                 break;
 325         case 0xf:
 326         default:
 327                 bw = 4;
 328                 break;
 329         }
 330
 331         for (i = 0; i < bw; i++) {
 332                 gate[i] = readl(PHY_REG(phy_base, 0xfb + i));
 333                 max_val = MAX(max_val, gate[i]);
 334                 min_val = MIN(min_val, gate[i]);
 335         }
 336
 337         if (max_val > 0x80 || min_val < 0x20)
 338                 return -1;
 339         else
 340                 return 0;
 341 }
 342
 343 static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
 344 {
 345         void __iomem *pctl_base = dram->pctl;
 346         u32 dis_auto_zq = 0;
 347         u32 pwrctl;
 348         u32 ret;
 349
 350         /* disable auto low-power */
 351         pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
 352         writel(0, pctl_base + DDR_PCTL2_PWRCTL);
 353
 354         dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl);
 355
 356         ret = phy_data_training(dram->phy, cs, dramtype);
 357
 358         pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq);
 359
 360         /* restore auto low-power */
 361         writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
 362
 363         return ret;
 364 }
 365
 366 static void dram_set_bw(struct dram_info *dram, u32 bw)
 367 {
 368         phy_dram_set_bw(dram->phy, bw);
 369 }
 370
 371 static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)
 372 {
 373         writel(ddrconfig | (ddrconfig << 8), &dram->msch->deviceconf);
 374         rk_clrsetreg(&dram->grf->soc_noc_con[1], 0x3 << 14, 0 << 14);
 375 }
 376
 377 static void sdram_msch_config(struct msch_regs *msch,
 378                               struct sdram_msch_timings *noc_timings,
 379                               struct sdram_cap_info *cap_info,
 380                               struct sdram_base_params *base)
 381 {
 382         u64 cs_cap[2];
 383
 384         cs_cap[0] = sdram_get_cs_cap(cap_info, 0, base->dramtype);
 385         cs_cap[1] = sdram_get_cs_cap(cap_info, 1, base->dramtype);
 386         writel(((((cs_cap[1] >> 20) / 64) & 0xff) << 8) |
 387                         (((cs_cap[0] >> 20) / 64) & 0xff),
 388                         &msch->devicesize);
 389
 390         writel(noc_timings->ddrtiminga0.d32,
 391                &msch->ddrtiminga0);
 392         writel(noc_timings->ddrtimingb0.d32,
 393                &msch->ddrtimingb0);
 394         writel(noc_timings->ddrtimingc0.d32,
 395                &msch->ddrtimingc0);
 396         writel(noc_timings->devtodev0.d32,
 397                &msch->devtodev0);
 398         writel(noc_timings->ddrmode.d32, &msch->ddrmode);
 399         writel(noc_timings->ddr4timing.d32,
 400                &msch->ddr4timing);
 401         writel(noc_timings->agingx0, &msch->agingx0);
 402         writel(noc_timings->agingx0, &msch->aging0);
 403         writel(noc_timings->agingx0, &msch->aging1);
 404         writel(noc_timings->agingx0, &msch->aging2);
 405         writel(noc_timings->agingx0, &msch->aging3);
 406 }
 407
 408 static void dram_all_config(struct dram_info *dram,
 409                             struct px30_sdram_params *sdram_params)
 410 {
 411         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 412         u32 sys_reg2 = 0;
 413         u32 sys_reg3 = 0;
 414
 415         set_ddrconfig(dram, cap_info->ddrconfig);
 416         sdram_org_config(cap_info, &sdram_params->base, &sys_reg2,
 417                          &sys_reg3, 0);
 418         writel(sys_reg2, &dram->pmugrf->os_reg[2]);
 419         writel(sys_reg3, &dram->pmugrf->os_reg[3]);
 420         sdram_msch_config(dram->msch, &sdram_params->ch.noc_timings, cap_info,
 421                           &sdram_params->base);
 422 }
 423
 424 static void enable_low_power(struct dram_info *dram,
 425                              struct px30_sdram_params *sdram_params)
 426 {
 427         void __iomem *pctl_base = dram->pctl;
 428         void __iomem *phy_base = dram->phy;
 429         void __iomem *ddr_grf_base = dram->ddr_grf;
 430         u32 grf_lp_con;
 431
 432         /*
 433          * bit0: grf_upctl_axi_cg_en = 1 enable upctl2 axi clk auto gating
 434          * bit1: grf_upctl_apb_cg_en = 1 ungated axi,core clk for apb access
 435          * bit2: grf_upctl_core_cg_en = 1 enable upctl2 core clk auto gating
 436          * bit3: grf_selfref_type2_en = 0 disable core clk gating when type2 sr
 437          * bit4: grf_upctl_syscreq_cg_en = 1
 438          *       ungating coreclk when c_sysreq assert
 439          * bit8-11: grf_auto_sr_dly = 6
 440          */
 441         writel(0x1f1f0617, &dram->ddr_grf->ddr_grf_con[1]);
 442
 443         if (sdram_params->base.dramtype == DDR4)
 444                 grf_lp_con = (0x7 << 16) | (1 << 1);
 445         else if (sdram_params->base.dramtype == DDR3)
 446                 grf_lp_con = (0x7 << 16) | (1 << 0);
 447         else
 448                 grf_lp_con = (0x7 << 16) | (1 << 2);
 449
 450         /* en lpckdis_en */
 451         grf_lp_con = grf_lp_con | (0x1 << (9 + 16)) | (0x1 << 9);
 452         writel(grf_lp_con, ddr_grf_base + DDR_GRF_LP_CON);
 453
 454         /* off digit module clock when enter power down */
 455         setbits_le32(PHY_REG(phy_base, 7), 1 << 7);
 456
 457         /* enable sr, pd */
 458         if (PD_IDLE == 0)
 459                 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
 460         else
 461                 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
 462         if (SR_IDLE == 0)
 463                 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
 464         else
 465                 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
 466         setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3));
 467 }
 468
 469 /*
 470  * pre_init: 0: pre init for dram cap detect
 471  * 1: detect correct cap(except cs1 row)info, than reinit
 472  * 2: after reinit, we detect cs1_row, if cs1_row not equal
 473  *    to cs0_row and cs is in middle on ddrconf map, we need
 474  *    to reinit dram, than set the correct ddrconf.
 475  */
 476 static int sdram_init_(struct dram_info *dram,
 477                        struct px30_sdram_params *sdram_params, u32 pre_init)
 478 {
 479         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 480         void __iomem *pctl_base = dram->pctl;
 481
 482         rkclk_ddr_reset(dram, 1, 1, 1, 1);
 483         udelay(10);
 484         /*
 485          * dereset ddr phy psrstn to config pll,
 486          * if using phy pll psrstn must be dereset
 487          * before config pll
 488          */
 489         rkclk_ddr_reset(dram, 1, 1, 1, 0);
 490         rkclk_configure_ddr(dram, sdram_params);
 491
 492         /* release phy srst to provide clk to ctrl */
 493         rkclk_ddr_reset(dram, 1, 1, 0, 0);
 494         udelay(10);
 495         phy_soft_reset(dram->phy);
 496         /* release ctrl presetn, and config ctl registers */
 497         rkclk_ddr_reset(dram, 1, 0, 0, 0);
 498         pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE);
 499         cap_info->ddrconfig = calculate_ddrconfig(sdram_params);
 500         set_ctl_address_map(dram, sdram_params);
 501         phy_cfg(dram->phy, &sdram_params->phy_regs, sdram_params->skew,
 502                 &sdram_params->base, cap_info->bw);
 503
 504         /* enable dfi_init_start to init phy after ctl srstn deassert */
 505         setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));
 506
 507         rkclk_ddr_reset(dram, 0, 0, 0, 0);
 508         /* wait for dfi_init_done and dram init complete */
 509         while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
 510                 continue;
 511
 512         if (sdram_params->base.dramtype == LPDDR3)
 513                 pctl_write_mr(dram->pctl, 3, 11, 3, LPDDR3);
 514
 515         /* do ddr gate training */
 516 redo_cs0_training:
 517         if (data_training(dram, 0, sdram_params->base.dramtype) != 0) {
 518                 if (pre_init != 0)
 519                         printascii("DTT cs0 error\n");
 520                 return -1;
 521         }
 522         if (check_rd_gate(dram)) {
 523                 printascii("re training cs0");
 524                 goto redo_cs0_training;
 525         }
 526
 527         if (sdram_params->base.dramtype == LPDDR3) {
 528                 if ((read_mr(dram, 1, 8) & 0x3) != 0x3)
 529                         return -1;
 530         } else if (sdram_params->base.dramtype == LPDDR2) {
 531                 if ((read_mr(dram, 1, 8) & 0x3) != 0x0)
 532                         return -1;
 533         }
 534         /* for px30: when 2cs, both 2 cs should be training */
 535         if (pre_init != 0 && cap_info->rank == 2) {
 536 redo_cs1_training:
 537                 if (data_training(dram, 1, sdram_params->base.dramtype) != 0) {
 538                         printascii("DTT cs1 error\n");
 539                         return -1;
 540                 }
 541                 if (check_rd_gate(dram)) {
 542                         printascii("re training cs1");
 543                         goto redo_cs1_training;
 544                 }
 545         }
 546
 547         if (sdram_params->base.dramtype == DDR4)
 548                 pctl_write_vrefdq(dram->pctl, 0x3, 5670,
 549                                   sdram_params->base.dramtype);
 550
 551         dram_all_config(dram, sdram_params);
 552         enable_low_power(dram, sdram_params);
 553
 554         return 0;
 555 }
 556
 557 static int dram_detect_cap(struct dram_info *dram,
 558                            struct px30_sdram_params *sdram_params,
 559                            unsigned char channel)
 560 {
 561         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 562
 563         /*
 564          * for ddr3: ddrconf = 3
 565          * for ddr4: ddrconf = 12
 566          * for lpddr3: ddrconf = 3
 567          * default bw = 1
 568          */
 569         u32 bk, bktmp;
 570         u32 col, coltmp;
 571         u32 rowtmp;
 572         u32 cs;
 573         u32 bw = 1;
 574         u32 dram_type = sdram_params->base.dramtype;
 575
 576         if (dram_type != DDR4) {
 577                 /* detect col and bk for ddr3/lpddr3 */
 578                 coltmp = 12;
 579                 bktmp = 3;
 580                 if (dram_type == LPDDR2)
 581                         rowtmp = 15;
 582                 else
 583                         rowtmp = 16;
 584
 585                 if (sdram_detect_col(cap_info, coltmp) != 0)
 586                         goto cap_err;
 587                 sdram_detect_bank(cap_info, coltmp, bktmp);
 588                 sdram_detect_dbw(cap_info, dram_type);
 589         } else {
 590                 /* detect bg for ddr4 */
 591                 coltmp = 10;
 592                 bktmp = 4;
 593                 rowtmp = 17;
 594
 595                 col = 10;
 596                 bk = 2;
 597                 cap_info->col = col;
 598                 cap_info->bk = bk;
 599                 sdram_detect_bg(cap_info, coltmp);
 600         }
 601
 602         /* detect row */
 603         if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0)
 604                 goto cap_err;
 605
 606         /* detect row_3_4 */
 607         sdram_detect_row_3_4(cap_info, coltmp, bktmp);
 608
 609         /* bw and cs detect using data training */
 610         if (data_training(dram, 1, dram_type) == 0)
 611                 cs = 1;
 612         else
 613                 cs = 0;
 614         cap_info->rank = cs + 1;
 615
 616         dram_set_bw(dram, 2);
 617         if (data_training(dram, 0, dram_type) == 0)
 618                 bw = 2;
 619         else
 620                 bw = 1;
 621         cap_info->bw = bw;
 622
 623         cap_info->cs0_high16bit_row = cap_info->cs0_row;
 624         if (cs) {
 625                 cap_info->cs1_row = cap_info->cs0_row;
 626                 cap_info->cs1_high16bit_row = cap_info->cs0_row;
 627         } else {
 628                 cap_info->cs1_row = 0;
 629                 cap_info->cs1_high16bit_row = 0;
 630         }
 631
 632         return 0;
 633 cap_err:
 634         return -1;
 635 }
 636
 637 /* return: 0 = success, other = fail */
 638 static int sdram_init_detect(struct dram_info *dram,
 639                              struct px30_sdram_params *sdram_params)
 640 {
 641         struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
 642         u32 ret;
 643         u32 sys_reg = 0;
 644         u32 sys_reg3 = 0;
 645
 646         if (sdram_init_(dram, sdram_params, 0) != 0)
 647                 return -1;
 648
 649         if (dram_detect_cap(dram, sdram_params, 0) != 0)
 650                 return -1;
 651
 652         /* modify bw, cs related timing */
 653         pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info,
 654                                    sdram_params->base.dramtype);
 655         /* reinit sdram by real dram cap */
 656         ret = sdram_init_(dram, sdram_params, 1);
 657         if (ret != 0)
 658                 goto out;
 659
 660         /* redetect cs1 row */
 661         sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype);
 662         if (cap_info->cs1_row) {
 663                 sys_reg = readl(&dram->pmugrf->os_reg[2]);
 664                 sys_reg3 = readl(&dram->pmugrf->os_reg[3]);
 665                 SYS_REG_ENC_CS1_ROW(cap_info->cs1_row,
 666                                     sys_reg, sys_reg3, 0);
 667                 writel(sys_reg, &dram->pmugrf->os_reg[2]);
 668                 writel(sys_reg3, &dram->pmugrf->os_reg[3]);
 669         }
 670
 671         ret = sdram_detect_high_row(cap_info);
 672
 673 out:
 674         return ret;
 675 }
 676
 677 struct px30_sdram_params
 678                 *get_default_sdram_config(void)
 679 {
 680         sdram_configs[0].skew = &skew;
 681
 682         return &sdram_configs[0];
 683 }
 684
 685 /* return: 0 = success, other = fail */
 686 int sdram_init(void)
 687 {
 688         struct px30_sdram_params *sdram_params;
 689         int ret = 0;
 690
 691         dram_info.phy = (void *)DDR_PHY_BASE_ADDR;
 692         dram_info.pctl = (void *)DDRC_BASE_ADDR;
 693         dram_info.grf = (void *)GRF_BASE_ADDR;
 694         dram_info.cru = (void *)CRU_BASE_ADDR;
 695         dram_info.msch = (void *)SERVER_MSCH0_BASE_ADDR;
 696         dram_info.ddr_grf = (void *)DDR_GRF_BASE_ADDR;
 697         dram_info.pmugrf = (void *)PMUGRF_BASE_ADDR;
 698
 699         sdram_params = get_default_sdram_config();
 700         ret = sdram_init_detect(&dram_info, sdram_params);
 701
 702         if (ret)
 703                 goto error;
 704
 705         sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base);
 706
 707         printascii("out\n");
 708         return ret;
 709 error:
 710         return (-1);
 711 }
 712 #else
 713
 714 static int px30_dmc_probe(struct udevice *dev)
 715 {
 716         struct dram_info *priv = dev_get_priv(dev);
 717
 718         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 719         debug("%s: grf=%p\n", __func__, priv->pmugrf);
 720         priv->info.base = CONFIG_SYS_SDRAM_BASE;
 721         priv->info.size =
 722                 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
 723
 724         return 0;
 725 }
 726
 727 static int px30_dmc_get_info(struct udevice *dev, struct ram_info *info)
 728 {
 729         struct dram_info *priv = dev_get_priv(dev);
 730
 731         *info = priv->info;
 732
 733         return 0;
 734 }
 735
 736 static struct ram_ops px30_dmc_ops = {
 737         .get_info = px30_dmc_get_info,
 738 };
 739
 740 static const struct udevice_id px30_dmc_ids[] = {
 741         { .compatible = "rockchip,px30-dmc" },
 742         { }
 743 };
 744
 745 U_BOOT_DRIVER(dmc_px30) = {
 746         .name = "rockchip_px30_dmc",
 747         .id = UCLASS_RAM,
 748         .of_match = px30_dmc_ids,
 749         .ops = &px30_dmc_ops,
 750         .probe = px30_dmc_probe,
 751         .priv_auto_alloc_size = sizeof(struct dram_info),
 752 };
 753 #endif /* CONFIG_TPL_BUILD */