drivers/ram/mediatek/ddr3-mt7629.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek DDR3 driver for MT7629 SoC
   4  *
   5  * Copyright (C) 2018 MediaTek Inc.
   6  * Author: Wu Zou <wu.zou@mediatek.com>
   7  *         Ryder Lee <ryder.lee@mediatek.com>
   8  */
   9
  10 #include <clk.h>
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <ram.h>
  14 #include <asm/io.h>
  15 #include <linux/delay.h>
  16
  17 /* EMI */
  18 #define EMI_CONA                        0x000
  19 #define EMI_CONF                        0x028
  20 #define EMI_CONM                        0x060
  21
  22 /* DDR PHY */
  23 #define DDRPHY_PLL1                     0x0000
  24 #define DDRPHY_PLL2                     0x0004
  25 #define DDRPHY_PLL3                     0x0008
  26 #define DDRPHY_PLL4                     0x000c
  27 #define DDRPHY_PLL5                     0x0010
  28 #define DDRPHY_PLL7                     0x0018
  29 #define DDRPHY_B0_DLL_ARPI0             0x0080
  30 #define DDRPHY_B0_DLL_ARPI1             0x0084
  31 #define DDRPHY_B0_DLL_ARPI2             0x0088
  32 #define DDRPHY_B0_DLL_ARPI3             0x008c
  33 #define DDRPHY_B0_DLL_ARPI4             0x0090
  34 #define DDRPHY_B0_DLL_ARPI5             0x0094
  35 #define DDRPHY_B0_DQ2                   0x00a0
  36 #define DDRPHY_B0_DQ3                   0x00a4
  37 #define DDRPHY_B0_DQ4                   0x00a8
  38 #define DDRPHY_B0_DQ5                   0x00ac
  39 #define DDRPHY_B0_DQ6                   0x00b0
  40 #define DDRPHY_B0_DQ7                   0x00b4
  41 #define DDRPHY_B0_DQ8                   0x00b8
  42 #define DDRPHY_B1_DLL_ARPI0             0x0100
  43 #define DDRPHY_B1_DLL_ARPI1             0x0104
  44 #define DDRPHY_B1_DLL_ARPI2             0x0108
  45 #define DDRPHY_B1_DLL_ARPI3             0x010c
  46 #define DDRPHY_B1_DLL_ARPI4             0x0110
  47 #define DDRPHY_B1_DLL_ARPI5             0x0114
  48 #define DDRPHY_B1_DQ2                   0x0120
  49 #define DDRPHY_B1_DQ3                   0x0124
  50 #define DDRPHY_B1_DQ4                   0x0128
  51 #define DDRPHY_B1_DQ5                   0x012c
  52 #define DDRPHY_B1_DQ6                   0x0130
  53 #define DDRPHY_B1_DQ7                   0x0134
  54 #define DDRPHY_B1_DQ8                   0x0138
  55 #define DDRPHY_CA_DLL_ARPI0             0x0180
  56 #define DDRPHY_CA_DLL_ARPI1             0x0184
  57 #define DDRPHY_CA_DLL_ARPI2             0x0188
  58 #define DDRPHY_CA_DLL_ARPI3             0x018c
  59 #define DDRPHY_CA_DLL_ARPI4             0x0190
  60 #define DDRPHY_CA_DLL_ARPI5             0x0194
  61 #define DDRPHY_CA_CMD2                  0x01a0
  62 #define DDRPHY_CA_CMD3                  0x01a4
  63 #define DDRPHY_CA_CMD5                  0x01ac
  64 #define DDRPHY_CA_CMD6                  0x01b0
  65 #define DDRPHY_CA_CMD7                  0x01b4
  66 #define DDRPHY_CA_CMD8                  0x01b8
  67 #define DDRPHY_MISC_VREF_CTRL           0x0264
  68 #define DDRPHY_MISC_IMP_CTRL0           0x0268
  69 #define DDRPHY_MISC_IMP_CTRL1           0x026c
  70 #define DDRPHY_MISC_SHU_OPT             0x0270
  71 #define DDRPHY_MISC_SPM_CTRL0           0x0274
  72 #define DDRPHY_MISC_SPM_CTRL1           0x0278
  73 #define DDRPHY_MISC_SPM_CTRL2           0x027c
  74 #define DDRPHY_MISC_CG_CTRL0            0x0284
  75 #define DDRPHY_MISC_CG_CTRL1            0x0288
  76 #define DDRPHY_MISC_CG_CTRL2            0x028c
  77 #define DDRPHY_MISC_CG_CTRL4            0x0294
  78 #define DDRPHY_MISC_CTRL0               0x029c
  79 #define DDRPHY_MISC_CTRL1               0x02a0
  80 #define DDRPHY_MISC_CTRL3               0x02a8
  81 #define DDRPHY_MISC_RXDVS1              0x05e4
  82 #define DDRPHY_SHU1_B0_DQ4              0x0c10
  83 #define DDRPHY_SHU1_B0_DQ5              0x0c14
  84 #define DDRPHY_SHU1_B0_DQ6              0x0c18
  85 #define DDRPHY_SHU1_B0_DQ7              0x0c1c
  86 #define DDRPHY_SHU1_B1_DQ4              0x0c90
  87 #define DDRPHY_SHU1_B1_DQ5              0x0c94
  88 #define DDRPHY_SHU1_B1_DQ6              0x0c98
  89 #define DDRPHY_SHU1_B1_DQ7              0x0c9c
  90 #define DDRPHY_SHU1_CA_CMD2             0x0d08
  91 #define DDRPHY_SHU1_CA_CMD4             0x0d10
  92 #define DDRPHY_SHU1_CA_CMD5             0x0d14
  93 #define DDRPHY_SHU1_CA_CMD6             0x0d18
  94 #define DDRPHY_SHU1_CA_CMD7             0x0d1c
  95 #define DDRPHY_SHU1_PLL0                0x0d80
  96 #define DDRPHY_SHU1_PLL1                0x0d84
  97 #define DDRPHY_SHU1_PLL4                0x0d90
  98 #define DDRPHY_SHU1_PLL5                0x0d94
  99 #define DDRPHY_SHU1_PLL6                0x0d98
 100 #define DDRPHY_SHU1_PLL7                0x0d9C
 101 #define DDRPHY_SHU1_PLL8                0x0da0
 102 #define DDRPHY_SHU1_PLL9                0x0da4
 103 #define DDRPHY_SHU1_PLL10               0x0da8
 104 #define DDRPHY_SHU1_PLL11               0x0dac
 105 #define DDRPHY_SHU1_R0_B0_DQ2           0x0e08
 106 #define DDRPHY_SHU1_R0_B0_DQ3           0x0e0c
 107 #define DDRPHY_SHU1_R0_B0_DQ4           0x0e10
 108 #define DDRPHY_SHU1_R0_B0_DQ5           0x0e14
 109 #define DDRPHY_SHU1_R0_B0_DQ6           0x0e18
 110 #define DDRPHY_SHU1_R0_B0_DQ7           0x0e1c
 111 #define DDRPHY_SHU1_R0_B1_DQ2           0x0e58
 112 #define DDRPHY_SHU1_R0_B1_DQ3           0x0e5c
 113 #define DDRPHY_SHU1_R0_B1_DQ4           0x0e60
 114 #define DDRPHY_SHU1_R0_B1_DQ5           0x0e64
 115 #define DDRPHY_SHU1_R0_B1_DQ6           0x0e68
 116 #define DDRPHY_SHU1_R0_B1_DQ7           0x0e6c
 117 #define DDRPHY_SHU1_R0_CA_CMD9          0x0ec4
 118 #define DDRPHY_SHU1_R1_B0_DQ2           0x0f08
 119 #define DDRPHY_SHU1_R1_B0_DQ3           0x0f0c
 120 #define DDRPHY_SHU1_R1_B0_DQ4           0x0f10
 121 #define DDRPHY_SHU1_R1_B0_DQ5           0x0f14
 122 #define DDRPHY_SHU1_R1_B0_DQ6           0x0f18
 123 #define DDRPHY_SHU1_R1_B0_DQ7           0x0f1c
 124 #define DDRPHY_SHU1_R1_B1_DQ2           0x0f58
 125 #define DDRPHY_SHU1_R1_B1_DQ3           0x0f5c
 126 #define DDRPHY_SHU1_R1_B1_DQ4           0x0f60
 127 #define DDRPHY_SHU1_R1_B1_DQ5           0x0f64
 128 #define DDRPHY_SHU1_R1_B1_DQ6           0x0f68
 129 #define DDRPHY_SHU1_R1_B1_DQ7           0x0f6c
 130 #define DDRPHY_SHU1_R1_CA_CMD9          0x0fc4
 131
 132 /* DRAMC */
 133 #define DRAMC_DDRCONF0                  0x0000
 134 #define DRAMC_DRAMCTRL                  0x0004
 135 #define DRAMC_MISCTL0                   0x0008
 136 #define DRAMC_PERFCTL0                  0x000c
 137 #define DRAMC_ARBCTL                    0x0010
 138 #define DRAMC_RSTMASK                   0x001c
 139 #define DRAMC_PADCTRL                   0x0020
 140 #define DRAMC_CKECTRL                   0x0024
 141 #define DRAMC_RKCFG                     0x0034
 142 #define DRAMC_DRAMC_PD_CTRL             0x0038
 143 #define DRAMC_CLKAR                     0x003c
 144 #define DRAMC_CLKCTRL                   0x0040
 145 #define DRAMC_SREFCTRL                  0x0048
 146 #define DRAMC_REFCTRL0                  0x004c
 147 #define DRAMC_REFCTRL1                  0x0050
 148 #define DRAMC_REFRATRE_FILTER           0x0054
 149 #define DRAMC_ZQCS                      0x0058
 150 #define DRAMC_MRS                       0x005c
 151 #define DRAMC_SPCMD                     0x0060
 152 #define DRAMC_SPCMDCTRL                 0x0064
 153 #define DRAMC_HW_MRR_FUN                0x0074
 154 #define DRAMC_TEST2_1                   0x0094
 155 #define DRAMC_TEST2_2                   0x0098
 156 #define DRAMC_TEST2_3                   0x009c
 157 #define DRAMC_TEST2_4                   0x00a0
 158 #define DRAMC_CATRAINING1               0x00b0
 159 #define DRAMC_DUMMY_RD                  0x00d0
 160 #define DRAMC_SHUCTRL                   0x00d4
 161 #define DRAMC_SHUCTRL2                  0x00dc
 162 #define DRAMC_STBCAL                    0x0200
 163 #define DRAMC_STBCAL1                   0x0204
 164 #define DRAMC_EYESCAN                   0x020c
 165 #define DRAMC_DVFSDLL                   0x0210
 166 #define DRAMC_SHU_ACTIM0                0x0800
 167 #define DRAMC_SHU_ACTIM1                0x0804
 168 #define DRAMC_SHU_ACTIM2                0x0808
 169 #define DRAMC_SHU_ACTIM3                0x080c
 170 #define DRAMC_SHU_ACTIM4                0x0810
 171 #define DRAMC_SHU_ACTIM5                0x0814
 172 #define DRAMC_SHU_ACTIM_XRT             0x081c
 173 #define DRAMC_SHU_AC_TIME_05T           0x0820
 174 #define DRAMC_SHU_CONF0                 0x0840
 175 #define DRAMC_SHU_CONF1                 0x0844
 176 #define DRAMC_SHU_CONF2                 0x0848
 177 #define DRAMC_SHU_CONF3                 0x084c
 178 #define DRAMC_SHU_RANKCTL               0x0858
 179 #define DRAMC_SHU_CKECTRL               0x085c
 180 #define DRAMC_SHU_ODTCTRL               0x0860
 181 #define DRAMC_SHU_PIPE                  0x0878
 182 #define DRAMC_SHU_SELPH_CA1             0x0880
 183 #define DRAMC_SHU_SELPH_CA2             0x0884
 184 #define DRAMC_SHU_SELPH_CA3             0x0888
 185 #define DRAMC_SHU_SELPH_CA4             0x088c
 186 #define DRAMC_SHU_SELPH_CA5             0x0890
 187 #define DRAMC_SHU_SELPH_CA6             0x0894
 188 #define DRAMC_SHU_SELPH_CA7             0x0898
 189 #define DRAMC_SHU_SELPH_CA8             0x089c
 190 #define DRAMC_SHU_SELPH_DQS0            0x08a0
 191 #define DRAMC_SHU_SELPH_DQS1            0x08a4
 192 #define DRAMC_SHU1_DRVING1              0x08a8
 193 #define DRAMC_SHU1_DRVING2              0x08ac
 194 #define DRAMC_SHU1_WODT                 0x08c0
 195 #define DRAMC_SHU_SCINTV                0x08c8
 196 #define DRAMC_SHURK0_DQSCTL             0x0a00
 197 #define DRAMC_SHURK0_DQSIEN             0x0a04
 198 #define DRAMC_SHURK0_SELPH_ODTEN0       0x0a1c
 199 #define DRAMC_SHURK0_SELPH_ODTEN1       0x0a20
 200 #define DRAMC_SHURK0_SELPH_DQSG0        0x0a24
 201 #define DRAMC_SHURK0_SELPH_DQSG1        0x0a28
 202 #define DRAMC_SHURK0_SELPH_DQ0          0x0a2c
 203 #define DRAMC_SHURK0_SELPH_DQ1          0x0a30
 204 #define DRAMC_SHURK0_SELPH_DQ2          0x0a34
 205 #define DRAMC_SHURK0_SELPH_DQ3          0x0a38
 206 #define DRAMC_SHURK1_DQSCTL             0x0b00
 207 #define DRAMC_SHURK1_SELPH_ODTEN0       0x0b1c
 208 #define DRAMC_SHURK1_SELPH_ODTEN1       0x0b20
 209 #define DRAMC_SHURK1_SELPH_DQSG0        0x0b24
 210 #define DRAMC_SHURK1_SELPH_DQSG1        0x0b28
 211 #define DRAMC_SHURK1_SELPH_DQ0          0x0b2c
 212 #define DRAMC_SHURK1_SELPH_DQ1          0x0b30
 213 #define DRAMC_SHURK1_SELPH_DQ2          0x0b34
 214 #define DRAMC_SHURK1_SELPH_DQ3          0x0b38
 215 #define DRAMC_SHURK2_SELPH_ODTEN0       0x0c1c
 216 #define DRAMC_SHURK2_SELPH_ODTEN1       0x0c20
 217 #define DRAMC_SHU_DQSG_RETRY            0x0c54
 218
 219 #define EMI_COL_ADDR_MASK               GENMASK(13, 12)
 220 #define EMI_COL_ADDR_SHIFT              12
 221 #define WALKING_PATTERN                 0x12345678
 222 #define WALKING_STEP                    0x4000000
 223
 224 struct mtk_ddr3_priv {
 225         fdt_addr_t emi;
 226         fdt_addr_t ddrphy;
 227         fdt_addr_t dramc_ao;
 228         struct clk phy;
 229         struct clk phy_mux;
 230         struct clk mem;
 231         struct clk mem_mux;
 232 };
 233
 234 #ifdef CONFIG_SPL_BUILD
 235 static int mtk_ddr3_rank_size_detect(struct udevice *dev)
 236 {
 237         struct mtk_ddr3_priv *priv = dev_get_priv(dev);
 238         int step;
 239         u32 start, test;
 240
 241         /* To detect size, we have to make sure it's single rank
 242          * and it has maximum addressing region
 243          */
 244
 245         writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE);
 246
 247         if (readl(CONFIG_SYS_SDRAM_BASE) != WALKING_PATTERN)
 248                 return -EINVAL;
 249
 250         for (step = 0; step < 5; step++) {
 251                 writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE +
 252                        (WALKING_STEP << step));
 253
 254                 start = readl(CONFIG_SYS_SDRAM_BASE);
 255                 test = readl(CONFIG_SYS_SDRAM_BASE + (WALKING_STEP << step));
 256                 if ((test != ~WALKING_PATTERN) || test == start)
 257                         break;
 258         }
 259
 260         step = step ? step - 1 : 3;
 261         clrsetbits_le32(priv->emi + EMI_CONA, EMI_COL_ADDR_MASK,
 262                         step << EMI_COL_ADDR_SHIFT);
 263
 264         return 0;
 265 }
 266
 267 static int mtk_ddr3_init(struct udevice *dev)
 268 {
 269         struct mtk_ddr3_priv *priv = dev_get_priv(dev);
 270         int ret;
 271
 272         ret = clk_set_parent(&priv->phy, &priv->phy_mux);
 273         if (ret)
 274                 return ret;
 275
 276         /* EMI Setting */
 277         writel(0x00003010, priv->emi + EMI_CONA);
 278         writel(0x00000000, priv->emi + EMI_CONF);
 279         writel(0x000006b8, priv->emi + EMI_CONM);
 280         /* DQS */
 281         writel(0x20c00, priv->dramc_ao + DRAMC_SHU1_DRVING1);
 282         /* Clock */
 283         writel(0x8320c83, priv->dramc_ao + DRAMC_SHU1_DRVING2);
 284
 285         /* DDRPHY setting */
 286         writel(0x2201, priv->dramc_ao + DRAMC_DRAMCTRL);
 287         writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL);
 288         writel(0xe08, priv->ddrphy + DDRPHY_CA_CMD5);
 289         writel(0x60e, priv->ddrphy + DDRPHY_SHU1_CA_CMD5);
 290         writel(0x0, priv->ddrphy + DDRPHY_MISC_SPM_CTRL1);
 291         writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL0);
 292         writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL2);
 293         writel(0x6003bf, priv->ddrphy + DDRPHY_MISC_CG_CTRL2);
 294         writel(0x13300000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4);
 295
 296         writel(0x1, priv->ddrphy + DDRPHY_SHU1_CA_CMD7);
 297         writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7);
 298         writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7);
 299         writel(0xfff0, priv->ddrphy + DDRPHY_CA_CMD2);
 300         writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2);
 301         writel(0x0, priv->ddrphy + DDRPHY_B1_DQ2);
 302         writel(0x7, priv->ddrphy + DDRPHY_MISC_RXDVS1);
 303         writel(0x10, priv->ddrphy + DDRPHY_PLL3);
 304         writel(0x8e8e0000, priv->ddrphy + DDRPHY_MISC_VREF_CTRL);
 305         writel(0x2e0040, priv->ddrphy + DDRPHY_MISC_IMP_CTRL0);
 306         writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5);
 307         writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5);
 308         udelay(1);
 309
 310         writel(0x10, priv->ddrphy + DDRPHY_B0_DQ3);
 311         writel(0x10, priv->ddrphy + DDRPHY_B1_DQ3);
 312         writel(0x3f600, priv->ddrphy + DDRPHY_MISC_CG_CTRL1);
 313         writel(0x1010, priv->ddrphy + DDRPHY_B0_DQ4);
 314         writel(0x1110e0e, priv->ddrphy + DDRPHY_B0_DQ5);
 315         writel(0x10c10d0, priv->ddrphy + DDRPHY_B0_DQ6);
 316         writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5);
 317         writel(0x1010, priv->ddrphy + DDRPHY_B1_DQ4);
 318         writel(0x1110e0e, priv->ddrphy + DDRPHY_B1_DQ5);
 319         writel(0x10c10d0, priv->ddrphy + DDRPHY_B1_DQ6);
 320         writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5);
 321         writel(0x7fffffc, priv->ddrphy + DDRPHY_CA_CMD3);
 322         writel(0xc0010, priv->ddrphy + DDRPHY_CA_CMD6);
 323         writel(0x101, priv->ddrphy + DDRPHY_SHU1_CA_CMD2);
 324         writel(0x41e, priv->ddrphy + DDRPHY_B0_DQ3);
 325         writel(0x41e, priv->ddrphy + DDRPHY_B1_DQ3);
 326         writel(0x180101, priv->ddrphy + DDRPHY_CA_CMD8);
 327         writel(0x0, priv->ddrphy + DDRPHY_MISC_IMP_CTRL1);
 328         writel(0x11400000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4);
 329         writel(0xfff0f0f0, priv->ddrphy + DDRPHY_MISC_SHU_OPT);
 330         writel(0x1f, priv->ddrphy + DDRPHY_MISC_CG_CTRL0);
 331
 332         writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD6);
 333         writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ6);
 334         writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ6);
 335         writel(0x40000, priv->ddrphy + DDRPHY_PLL4);
 336         writel(0x0, priv->ddrphy + DDRPHY_PLL1);
 337         writel(0x0, priv->ddrphy + DDRPHY_PLL2);
 338         writel(0x666008, priv->ddrphy + DDRPHY_CA_DLL_ARPI5);
 339         writel(0x80666008, priv->ddrphy + DDRPHY_B0_DLL_ARPI5);
 340         writel(0x80666008, priv->ddrphy + DDRPHY_B1_DLL_ARPI5);
 341         writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
 342         writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
 343         writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
 344         writel(0x400, priv->ddrphy + DDRPHY_CA_DLL_ARPI2);
 345         writel(0x20400, priv->ddrphy + DDRPHY_B0_DLL_ARPI2);
 346         writel(0x20400, priv->ddrphy + DDRPHY_B1_DLL_ARPI2);
 347         writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL9);
 348         writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL11);
 349         writel(0xf7f, priv->ddrphy + DDRPHY_SHU1_PLL0);
 350         writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL8);
 351         writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL10);
 352         writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL4);
 353         writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL6);
 354
 355         writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL5);
 356         writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL7);
 357
 358         writel(0x14d0002, priv->ddrphy + DDRPHY_PLL5);
 359         writel(0x14d0002, priv->ddrphy + DDRPHY_PLL7);
 360         writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL8);
 361         writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL10);
 362         writel(0xf, priv->ddrphy + DDRPHY_SHU1_PLL1);
 363         writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
 364         writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
 365         writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
 366         writel(0x698600, priv->ddrphy + DDRPHY_CA_DLL_ARPI5);
 367         writel(0xc0778600, priv->ddrphy + DDRPHY_B0_DLL_ARPI5);
 368         writel(0xc0778600, priv->ddrphy + DDRPHY_B1_DLL_ARPI5);
 369         writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI4);
 370         writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI4);
 371         writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI4);
 372         writel(0x2ba800, priv->ddrphy + DDRPHY_CA_DLL_ARPI1);
 373         writel(0x2ae806, priv->ddrphy + DDRPHY_B0_DLL_ARPI1);
 374         writel(0xae806, priv->ddrphy + DDRPHY_B1_DLL_ARPI1);
 375         writel(0xba000, priv->ddrphy + DDRPHY_CA_DLL_ARPI3);
 376         writel(0x2e800, priv->ddrphy + DDRPHY_B0_DLL_ARPI3);
 377         writel(0x2e800, priv->ddrphy + DDRPHY_B1_DLL_ARPI3);
 378         writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD4);
 379         writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ4);
 380         writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ4);
 381         writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
 382         writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
 383         writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
 384         writel(0x32cf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6);
 385         writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6);
 386         writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6);
 387         writel(0x80010000, priv->ddrphy + DDRPHY_PLL1);
 388         writel(0x80000000, priv->ddrphy + DDRPHY_PLL2);
 389         udelay(100);
 390
 391         writel(0xc, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
 392         writel(0x9, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
 393         writel(0x9, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
 394         writel(0xd0000, priv->ddrphy + DDRPHY_PLL4);
 395         udelay(1);
 396
 397         writel(0x82, priv->ddrphy + DDRPHY_MISC_CTRL1);
 398         writel(0x2, priv->dramc_ao + DRAMC_DDRCONF0);
 399         writel(0x3acf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6);
 400         writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6);
 401         writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6);
 402         udelay(1);
 403
 404         writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI2);
 405         writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI2);
 406         writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI2);
 407         writel(0x80, priv->ddrphy + DDRPHY_MISC_CTRL1);
 408         writel(0x0, priv->dramc_ao + DRAMC_DDRCONF0);
 409         writel(0x80000000, priv->ddrphy + DDRPHY_PLL1);
 410         udelay(1);
 411
 412         writel(0x698e00, priv->ddrphy + DDRPHY_CA_DLL_ARPI5);
 413         udelay(1);
 414
 415         writel(0xc0778e00, priv->ddrphy + DDRPHY_B0_DLL_ARPI5);
 416         udelay(1);
 417
 418         writel(0xc0778e00, priv->ddrphy + DDRPHY_B1_DLL_ARPI5);
 419         udelay(1);
 420
 421         ret = clk_set_parent(&priv->mem, &priv->mem_mux);
 422         if (ret)
 423                 return ret;
 424
 425         /* DDR PHY PLL setting */
 426         writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3);
 427         writel(0x51e, priv->ddrphy + DDRPHY_B1_DQ3);
 428         writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1);
 429         writel(0x80101, priv->ddrphy + DDRPHY_CA_CMD8);
 430         writel(0x100, priv->ddrphy + DDRPHY_CA_CMD7);
 431         writel(0x0, priv->ddrphy + DDRPHY_CA_CMD7);
 432         writel(0x0, priv->ddrphy + DDRPHY_B0_DQ7);
 433         writel(0x0, priv->ddrphy + DDRPHY_B1_DQ7);
 434         writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3);
 435         writel(0xff051e, priv->ddrphy + DDRPHY_B1_DQ3);
 436         writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2);
 437         writel(0x1ff, priv->ddrphy + DDRPHY_B1_DQ2);
 438
 439         /* Update initial setting */
 440         writel(0x5fc, priv->ddrphy + DDRPHY_B0_DQ3);
 441         writel(0xff05fc, priv->ddrphy + DDRPHY_B1_DQ3);
 442         writel(0x10c12d9, priv->ddrphy + DDRPHY_B0_DQ6);
 443         writel(0x10c12d9, priv->ddrphy + DDRPHY_B1_DQ6);
 444         writel(0xc0259, priv->ddrphy + DDRPHY_CA_CMD6);
 445         writel(0x4000, priv->ddrphy + DDRPHY_B0_DQ2);
 446         writel(0x41ff, priv->ddrphy + DDRPHY_B1_DQ2);
 447         writel(0x0, priv->ddrphy + DDRPHY_B0_DQ8);
 448         writel(0x100, priv->ddrphy + DDRPHY_B1_DQ8);
 449         writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5);
 450         writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5);
 451         writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5);
 452         writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5);
 453         writel(0x39eff6, priv->dramc_ao + DRAMC_SHU_SCINTV);
 454         writel(0x204ffff, priv->dramc_ao + DRAMC_CLKAR);
 455         writel(0x31b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
 456         writel(0x0, priv->dramc_ao + DRAMC_PERFCTL0);
 457         writel(0x80000, priv->dramc_ao + DRAMC_PERFCTL0);
 458
 459         /* Dramc setting PC3 */
 460         writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0);
 461
 462         writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3);
 463         writel(0x200600, priv->dramc_ao + DRAMC_SHU_DQSG_RETRY);
 464         writel(0x101d007, priv->dramc_ao + DRAMC_SHUCTRL2);
 465         writel(0xe090601, priv->dramc_ao + DRAMC_DVFSDLL);
 466         writel(0x20003000, priv->dramc_ao + DRAMC_DDRCONF0);
 467         writel(0x3900020f, priv->ddrphy + DDRPHY_MISC_CTRL0);
 468         writel(0xa20810bf, priv->dramc_ao + DRAMC_SHU_CONF0);
 469         writel(0x30050, priv->dramc_ao + DRAMC_SHU_ODTCTRL);
 470         writel(0x25712000, priv->dramc_ao + DRAMC_REFCTRL0);
 471         writel(0xb0100000, priv->dramc_ao + DRAMC_STBCAL);
 472         writel(0x8000000, priv->dramc_ao + DRAMC_SREFCTRL);
 473         writel(0xc0000000, priv->dramc_ao + DRAMC_SHU_PIPE);
 474         writel(0x731004, priv->dramc_ao + DRAMC_RKCFG);
 475         writel(0x8007320f, priv->dramc_ao + DRAMC_SHU_CONF2);
 476         writel(0x2a7c0, priv->dramc_ao + DRAMC_SHU_SCINTV);
 477         writel(0xc110, priv->dramc_ao + DRAMC_SHUCTRL);
 478         writel(0x30000700, priv->dramc_ao + DRAMC_REFCTRL1);
 479         writel(0x6543b321, priv->dramc_ao + DRAMC_REFRATRE_FILTER);
 480
 481         /* Update PCDDR3 default setting */
 482         writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA1);
 483         writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA2);
 484         writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA3);
 485         writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA4);
 486         writel(0x10000111, priv->dramc_ao + DRAMC_SHU_SELPH_CA5);
 487         writel(0x1000000, priv->dramc_ao + DRAMC_SHU_SELPH_CA6);
 488         writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA7);
 489         writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA8);
 490         writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_CA_CMD9);
 491         writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_CA_CMD9);
 492         writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0);
 493         writel(0x33331111, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1);
 494         writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0);
 495         writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1);
 496         writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2);
 497         writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3);
 498         writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ0);
 499         writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ1);
 500         writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ2);
 501         writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ3);
 502         writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7);
 503         writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ7);
 504         writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7);
 505         writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ7);
 506         writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN0);
 507         writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN1);
 508         writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN0);
 509         writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN1);
 510         writel(0x0, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN0);
 511         writel(0x66666666, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN1);
 512         writel(0x2c000b0f, priv->dramc_ao + DRAMC_SHU_CONF1);
 513         writel(0x11111111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0);
 514         writel(0x64646464, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1);
 515         writel(0x11111111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG0);
 516         writel(0x64646464, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG1);
 517         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2);
 518         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3);
 519         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4);
 520         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5);
 521         writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ6);
 522         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ2);
 523         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ3);
 524         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ4);
 525         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ5);
 526         writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ6);
 527         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2);
 528         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3);
 529         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4);
 530         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5);
 531         writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ6);
 532         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ2);
 533         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ3);
 534         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ4);
 535         writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ5);
 536         writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ6);
 537         writel(0x20000001, priv->dramc_ao + DRAMC_SHU_RANKCTL);
 538         writel(0x2, priv->dramc_ao + DRAMC_SHURK0_DQSCTL);
 539         writel(0x2, priv->dramc_ao + DRAMC_SHURK1_DQSCTL);
 540         writel(0x4020b07, priv->dramc_ao + DRAMC_SHU_ACTIM0);
 541         writel(0xb060400, priv->dramc_ao + DRAMC_SHU_ACTIM1);
 542         writel(0x8090200, priv->dramc_ao + DRAMC_SHU_ACTIM2);
 543         writel(0x810018, priv->dramc_ao + DRAMC_SHU_ACTIM3);
 544         writel(0x1e9700ff, priv->dramc_ao + DRAMC_SHU_ACTIM4);
 545         writel(0x1000908, priv->dramc_ao + DRAMC_SHU_ACTIM5);
 546         writel(0x801040b, priv->dramc_ao + DRAMC_SHU_ACTIM_XRT);
 547         writel(0x20000D1, priv->dramc_ao + DRAMC_SHU_AC_TIME_05T);
 548         writel(0x80010000, priv->ddrphy + DDRPHY_PLL2);
 549         udelay(500);
 550
 551         writel(0x81080000, priv->dramc_ao + DRAMC_MISCTL0);
 552         writel(0xacf13, priv->dramc_ao + DRAMC_PERFCTL0);
 553         writel(0xacf12, priv->dramc_ao + DRAMC_PERFCTL0);
 554         writel(0x80, priv->dramc_ao + DRAMC_ARBCTL);
 555         writel(0x9, priv->dramc_ao + DRAMC_PADCTRL);
 556         writel(0x80000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL);
 557         writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL);
 558         writel(0x25714001, priv->dramc_ao + DRAMC_REFCTRL0);
 559         writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
 560         writel(0x4300000, priv->dramc_ao + DRAMC_CATRAINING1);
 561         writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
 562         writel(0x731414, priv->dramc_ao + DRAMC_RKCFG);
 563         writel(0x733414, priv->dramc_ao + DRAMC_RKCFG);
 564         udelay(20);
 565
 566         writel(0x80002050, priv->dramc_ao + DRAMC_CKECTRL);
 567         udelay(100);
 568
 569         writel(0x400000, priv->dramc_ao + DRAMC_MRS);
 570         writel(0x401800, priv->dramc_ao + DRAMC_MRS);
 571         writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
 572         writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
 573         udelay(100);
 574
 575         writel(0x601800, priv->dramc_ao + DRAMC_MRS);
 576         writel(0x600000, priv->dramc_ao + DRAMC_MRS);
 577         writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
 578         writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
 579         udelay(100);
 580
 581         writel(0x200000, priv->dramc_ao + DRAMC_MRS);
 582         writel(0x200400, priv->dramc_ao + DRAMC_MRS);
 583         writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
 584         writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
 585         udelay(100);
 586
 587         writel(0x400, priv->dramc_ao + DRAMC_MRS);
 588         writel(0x1d7000, priv->dramc_ao + DRAMC_MRS);
 589         writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
 590         writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
 591         udelay(100);
 592
 593         writel(0x702201, priv->dramc_ao + DRAMC_DRAMCTRL);
 594         writel(0x10, priv->dramc_ao + DRAMC_SPCMD);
 595         writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
 596         writel(0x20, priv->dramc_ao + DRAMC_SPCMD);
 597         writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
 598         writel(0x1, priv->dramc_ao + DRAMC_HW_MRR_FUN);
 599         writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL);
 600         writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL);
 601         writel(0xa56, priv->dramc_ao + DRAMC_ZQCS);
 602         writel(0xff0000, priv->dramc_ao + DRAMC_SHU_CONF3);
 603         writel(0x15b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
 604         writel(0x2cb00b0f, priv->dramc_ao + DRAMC_SHU_CONF1);
 605         writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0);
 606         writel(0x48000000, priv->dramc_ao + DRAMC_SREFCTRL);
 607         writel(0xc0000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL);
 608         writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN);
 609         writel(0x15e00, priv->dramc_ao + DRAMC_STBCAL1);
 610         writel(0x100000, priv->dramc_ao + DRAMC_TEST2_1);
 611         writel(0x4000, priv->dramc_ao + DRAMC_TEST2_2);
 612         writel(0x12000480, priv->dramc_ao + DRAMC_TEST2_3);
 613         writel(0x301d007, priv->dramc_ao + DRAMC_SHUCTRL2);
 614         writel(0x4782321, priv->dramc_ao + DRAMC_DRAMCTRL);
 615         writel(0x30210000, priv->dramc_ao + DRAMC_SHU_CKECTRL);
 616         writel(0x20000, priv->dramc_ao + DRAMC_DUMMY_RD);
 617         writel(0x4080110d, priv->dramc_ao + DRAMC_TEST2_4);
 618         writel(0x30000721, priv->dramc_ao + DRAMC_REFCTRL1);
 619         writel(0x0, priv->dramc_ao + DRAMC_RSTMASK);
 620         writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL);
 621         writel(0x80002000, priv->dramc_ao + DRAMC_CKECTRL);
 622         writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0);
 623
 624         /* Apply config before calibration */
 625         writel(0x120, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL);
 626         writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3);
 627         writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_CG_CTRL0);
 628         writel(0x2a7fe, priv->dramc_ao + DRAMC_SHU_SCINTV);
 629         writel(0xff01ff, priv->dramc_ao + DRAMC_SHU_CONF3);
 630         writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL);
 631         writel(0xa56, priv->dramc_ao + DRAMC_ZQCS);
 632         writel(0x80000000, priv->dramc_ao + DRAMC_SHU1_WODT);
 633         writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7);
 634         writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7);
 635         writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
 636         writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
 637         writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
 638         writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
 639         writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
 640         writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN);
 641         writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1);
 642         writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0);
 643         writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
 644         writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
 645
 646         /* Write leveling */
 647         writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7);
 648         writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7);
 649         writel(0x33221100, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1);
 650         writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0);
 651
 652         /* RX dqs gating cal */
 653         writel(0x11111010, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0);
 654         writel(0x20201717, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1);
 655         writel(0x1d1f, priv->dramc_ao + DRAMC_SHURK0_DQSIEN);
 656
 657         /* RX window per-bit cal */
 658         writel(0x03030404, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2);
 659         writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3);
 660         writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4);
 661         writel(0x01010000, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5);
 662         writel(0x03030606, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2);
 663         writel(0x02020202, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3);
 664         writel(0x04040303, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4);
 665         writel(0x06060101, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5);
 666
 667         /* RX datlat cal */
 668         writel(0x28b00a0e, priv->dramc_ao + DRAMC_SHU_CONF1);
 669
 670         /* TX window per-byte with 2UI cal */
 671         writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0);
 672         writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2);
 673         writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1);
 674         writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3);
 675         writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7);
 676         writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7);
 677
 678         return mtk_ddr3_rank_size_detect(dev);
 679 }
 680 #endif
 681
 682 static int mtk_ddr3_probe(struct udevice *dev)
 683 {
 684         struct mtk_ddr3_priv *priv = dev_get_priv(dev);
 685
 686         priv->emi = dev_read_addr_index(dev, 0);
 687         if (priv->emi == FDT_ADDR_T_NONE)
 688                 return -EINVAL;
 689
 690         priv->ddrphy = dev_read_addr_index(dev, 1);
 691         if (priv->ddrphy == FDT_ADDR_T_NONE)
 692                 return -EINVAL;
 693
 694         priv->dramc_ao = dev_read_addr_index(dev, 2);
 695         if (priv->dramc_ao == FDT_ADDR_T_NONE)
 696                 return -EINVAL;
 697
 698 #ifdef CONFIG_SPL_BUILD
 699         int ret;
 700
 701         ret = clk_get_by_index(dev, 0, &priv->phy);
 702         if (ret)
 703                 return ret;
 704
 705         ret = clk_get_by_index(dev, 1, &priv->phy_mux);
 706         if (ret)
 707                 return ret;
 708
 709         ret = clk_get_by_index(dev, 2, &priv->mem);
 710         if (ret)
 711                 return ret;
 712
 713         ret = clk_get_by_index(dev, 3, &priv->mem_mux);
 714         if (ret)
 715                 return ret;
 716
 717         ret = mtk_ddr3_init(dev);
 718         if (ret)
 719                 return ret;
 720 #endif
 721         return 0;
 722 }
 723
 724 static int mtk_ddr3_get_info(struct udevice *dev, struct ram_info *info)
 725 {
 726         struct mtk_ddr3_priv *priv = dev_get_priv(dev);
 727         u32 val = readl(priv->emi + EMI_CONA);
 728
 729         info->base = CONFIG_SYS_SDRAM_BASE;
 730
 731         switch ((val & EMI_COL_ADDR_MASK) >> EMI_COL_ADDR_SHIFT) {
 732         case 0:
 733                 info->size = SZ_128M;
 734                 break;
 735         case 1:
 736                 info->size = SZ_256M;
 737                 break;
 738         case 2:
 739                 info->size = SZ_512M;
 740                 break;
 741         case 3:
 742                 info->size = SZ_1G;
 743                 break;
 744         default:
 745                 return -EINVAL;
 746         }
 747
 748         return 0;
 749 }
 750
 751 static struct ram_ops mtk_ddr3_ops = {
 752         .get_info = mtk_ddr3_get_info,
 753 };
 754
 755 static const struct udevice_id mtk_ddr3_ids[] = {
 756         { .compatible = "mediatek,mt7629-dramc" },
 757         { }
 758 };
 759
 760 U_BOOT_DRIVER(mediatek_ddr3) = {
 761         .name     = "mediatek_ddr3",
 762         .id       = UCLASS_RAM,
 763         .of_match = mtk_ddr3_ids,
 764         .ops      = &mtk_ddr3_ops,
 765         .probe    = mtk_ddr3_probe,
 766         .priv_auto_alloc_size = sizeof(struct mtk_ddr3_priv),
 767 };