drivers/ram/k3-j721e/k3-j721e-ddrss.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments' J721E DDRSS driver
   4  *
   5  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <hang.h>
  12 #include <ram.h>
  13 #include <asm/io.h>
  14 #include <power-domain.h>
  15 #include <wait_bit.h>
  16
  17 #include "lpddr4_obj_if.h"
  18 #include "lpddr4_if.h"
  19 #include "lpddr4_structs_if.h"
  20 #include "lpddr4_ctl_regs.h"
  21
  22 #define SRAM_MAX 512
  23
  24 #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS       0x80
  25 #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS       0xc0
  26
  27 struct j721e_ddrss_desc {
  28         struct udevice *dev;
  29         void __iomem *ddrss_ss_cfg;
  30         void __iomem *ddrss_ctrl_mmr;
  31         struct power_domain ddrcfg_pwrdmn;
  32         struct power_domain ddrdata_pwrdmn;
  33         struct clk ddr_clk;
  34         struct clk osc_clk;
  35         u32 ddr_freq1;
  36         u32 ddr_freq2;
  37         u32 ddr_fhs_cnt;
  38 };
  39
  40 static LPDDR4_OBJ *driverdt;
  41 static lpddr4_config config;
  42 static lpddr4_privatedata pd;
  43
  44 static struct j721e_ddrss_desc *ddrss;
  45
  46 #define TH_MACRO_EXP(fld, str) (fld##str)
  47
  48 #define TH_FLD_MASK(fld)  TH_MACRO_EXP(fld, _MASK)
  49 #define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
  50 #define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
  51 #define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
  52 #define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
  53
  54 #define str(s) #s
  55 #define xstr(s) str(s)
  56
  57 #define  CTL_SHIFT 11
  58 #define  PHY_SHIFT 11
  59 #define  PI_SHIFT 10
  60
  61 #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
  62         char *i, *pstr= xstr(REG); offset = 0;\
  63         for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
  64                 offset = offset * 10 + (*i - '0'); }\
  65         } while (0)
  66
  67 static void j721e_lpddr4_ack_freq_upd_req(void)
  68 {
  69         unsigned int req_type, counter;
  70
  71         debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
  72
  73         for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
  74                 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
  75                                       CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
  76                                       true, 10000, false)) {
  77                         printf("Timeout during frequency handshake\n");
  78                         hang();
  79                 }
  80
  81                 req_type = readl(ddrss->ddrss_ctrl_mmr +
  82                                  CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
  83
  84                 debug("%s: received freq change req: req type = %d, req no. = %d \n",
  85                       __func__, req_type, counter);
  86
  87                 if (req_type == 1)
  88                         clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
  89                 else if (req_type == 2)
  90                         clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
  91                 else if (req_type == 0)
  92                         /* Put DDR pll in bypass mode */
  93                         clk_set_rate(&ddrss->ddr_clk,
  94                                      clk_get_rate(&ddrss->osc_clk));
  95                 else
  96                         printf("%s: Invalid freq request type\n", __func__);
  97
  98                 writel(0x1, ddrss->ddrss_ctrl_mmr +
  99                        CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
 100                 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
 101                                       CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
 102                                       false, 10, false)) {
 103                         printf("Timeout during frequency handshake\n");
 104                         hang();
 105                 }
 106                 writel(0x0, ddrss->ddrss_ctrl_mmr +
 107                        CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
 108         }
 109 }
 110
 111 static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,
 112                                       lpddr4_infotype infotype)
 113 {
 114         if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) {
 115                 j721e_lpddr4_ack_freq_upd_req();
 116         }
 117 }
 118
 119 static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
 120 {
 121         int ret;
 122
 123         debug("%s(ddrss=%p)\n", __func__, ddrss);
 124
 125         ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
 126         if (ret) {
 127                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 128                 return ret;
 129         }
 130
 131         ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
 132         if (ret) {
 133                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 134                 return ret;
 135         }
 136
 137         return 0;
 138 }
 139
 140 static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
 141 {
 142         struct j721e_ddrss_desc *ddrss = dev_get_priv(dev);
 143         phys_addr_t reg;
 144         int ret;
 145
 146         debug("%s(dev=%p)\n", __func__, dev);
 147
 148         reg = dev_read_addr_name(dev, "cfg");
 149         if (reg == FDT_ADDR_T_NONE) {
 150                 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
 151                 return -EINVAL;
 152         }
 153         ddrss->ddrss_ss_cfg = (void *)reg;
 154
 155         reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
 156         if (reg == FDT_ADDR_T_NONE) {
 157                 dev_err(dev, "No reg property for CTRL MMR\n");
 158                 return -EINVAL;
 159         }
 160         ddrss->ddrss_ctrl_mmr = (void *)reg;
 161
 162         ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
 163         if (ret) {
 164                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 165                 return ret;
 166         }
 167
 168         ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
 169         if (ret) {
 170                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 171                 return ret;
 172         }
 173
 174         ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
 175         if (ret)
 176                 dev_err(dev, "clk get failed%d\n", ret);
 177
 178         ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
 179         if (ret)
 180                 dev_err(dev, "clk get failed for osc clk %d\n", ret);
 181
 182         ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
 183         if (ret)
 184                 dev_err(dev, "ddr freq1 not populated %d\n", ret);
 185
 186         ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
 187         if (ret)
 188                 dev_err(dev, "ddr freq2 not populated %d\n", ret);
 189
 190         ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
 191         if (ret)
 192                 dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
 193
 194         /* Put DDR pll in bypass mode */
 195         ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
 196         if (ret)
 197                 dev_err(dev, "ddr clk bypass failed\n");
 198
 199         return ret;
 200 }
 201
 202 void j721e_lpddr4_probe(void)
 203 {
 204         uint32_t status = 0U;
 205         uint16_t configsize = 0U;
 206
 207         status = driverdt->probe(&config, &configsize);
 208
 209         if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
 210             || (configsize > SRAM_MAX)) {
 211                 printf("LPDDR4_Probe: FAIL\n");
 212                 hang();
 213         } else {
 214                 debug("LPDDR4_Probe: PASS\n");
 215         }
 216 }
 217
 218 void j721e_lpddr4_init(void)
 219 {
 220         uint32_t status = 0U;
 221
 222         if ((sizeof(pd) != sizeof(lpddr4_privatedata))
 223             || (sizeof(pd) > SRAM_MAX)) {
 224                 printf("LPDDR4_Init: FAIL\n");
 225                 hang();
 226         }
 227
 228         config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
 229         config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler;
 230
 231         status = driverdt->init(&pd, &config);
 232
 233         if ((status > 0U) ||
 234             (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
 235             (pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
 236             (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
 237                 printf("LPDDR4_Init: FAIL\n");
 238                 hang();
 239         } else {
 240                 debug("LPDDR4_Init: PASS\n");
 241         }
 242 }
 243
 244 void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)
 245 {
 246         int ret, i;
 247
 248         ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
 249                                  (u32 *) reginit_data->denalictlreg,
 250                                  LPDDR4_CTL_REG_COUNT);
 251         if (ret)
 252                 printf("Error reading ctrl data\n");
 253
 254         for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++)
 255                 reginit_data->updatectlreg[i] = true;
 256
 257         ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
 258                                  (u32 *) reginit_data->denaliphyindepreg,
 259                                  LPDDR4_PHY_INDEP_REG_COUNT);
 260         if (ret)
 261                 printf("Error reading PI data\n");
 262
 263         for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++)
 264                 reginit_data->updatephyindepreg[i] = true;
 265
 266         ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
 267                                  (u32 *) reginit_data->denaliphyreg,
 268                                  LPDDR4_PHY_REG_COUNT);
 269         if (ret)
 270                 printf("Error reading PHY data\n");
 271
 272         for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++)
 273                 reginit_data->updatephyreg[i] = true;
 274 }
 275
 276 void j721e_lpddr4_hardware_reg_init(void)
 277 {
 278         uint32_t status = 0U;
 279         lpddr4_reginitdata reginitdata;
 280
 281         populate_data_array_from_dt(&reginitdata);
 282
 283         status = driverdt->writectlconfig(&pd, &reginitdata);
 284         if (!status) {
 285                 status = driverdt->writephyindepconfig(&pd, &reginitdata);
 286         }
 287         if (!status) {
 288                 status = driverdt->writephyconfig(&pd, &reginitdata);
 289         }
 290         if (status) {
 291                 printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n");
 292                 hang();
 293         }
 294
 295         return;
 296 }
 297
 298 void j721e_lpddr4_start(void)
 299 {
 300         uint32_t status = 0U;
 301         uint32_t regval = 0U;
 302         uint32_t offset = 0U;
 303
 304         TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
 305
 306         status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
 307         if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
 308                 printf("LPDDR4_StartTest: FAIL\n");
 309                 hang();
 310         }
 311
 312         status = driverdt->start(&pd);
 313         if (status > 0U) {
 314                 printf("LPDDR4_StartTest: FAIL\n");
 315                 hang();
 316         }
 317
 318         status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
 319         if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
 320                 printf("LPDDR4_Start: FAIL\n");
 321                 hang();
 322         } else {
 323                 debug("LPDDR4_Start: PASS\n");
 324         }
 325 }
 326
 327 static int j721e_ddrss_probe(struct udevice *dev)
 328 {
 329         int ret;
 330         ddrss = dev_get_priv(dev);
 331
 332         debug("%s(dev=%p)\n", __func__, dev);
 333
 334         ret = j721e_ddrss_ofdata_to_priv(dev);
 335         if (ret)
 336                 return ret;
 337
 338         ddrss->dev = dev;
 339         ret = j721e_ddrss_power_on(ddrss);
 340         if (ret)
 341                 return ret;
 342
 343         driverdt = lpddr4_getinstance();
 344         j721e_lpddr4_probe();
 345         j721e_lpddr4_init();
 346         j721e_lpddr4_hardware_reg_init();
 347         j721e_lpddr4_start();
 348
 349         return ret;
 350 }
 351
 352 static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info)
 353 {
 354         return 0;
 355 }
 356
 357 static struct ram_ops j721e_ddrss_ops = {
 358         .get_info = j721e_ddrss_get_info,
 359 };
 360
 361 static const struct udevice_id j721e_ddrss_ids[] = {
 362         {.compatible = "ti,j721e-ddrss"},
 363         {}
 364 };
 365
 366 U_BOOT_DRIVER(j721e_ddrss) = {
 367         .name = "j721e_ddrss",
 368         .id = UCLASS_RAM,
 369         .of_match = j721e_ddrss_ids,
 370         .ops = &j721e_ddrss_ops,
 371         .probe = j721e_ddrss_probe,
 372         .priv_auto_alloc_size = sizeof(struct j721e_ddrss_desc),
 373 };