drivers/ram/imxrt_sdram.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <ram.h>
  13 #include <asm/io.h>
  14 #include <linux/err.h>
  15
  16 /* SDRAM Command Code */
  17 #define SD_CC_ARD               0x0     /* Master Bus (AXI) command - Read */
  18 #define SD_CC_AWR               0x1     /* Master Bus (AXI) command - Write */
  19 #define SD_CC_IRD               0x8     /* IP command - Read */
  20 #define SD_CC_IWR               0x9     /* IP command - Write */
  21 #define SD_CC_IMS               0xA     /* IP command - Set Mode Register */
  22 #define SD_CC_IACT              0xB     /* IP command - ACTIVE */
  23 #define SD_CC_IAF               0xC     /* IP command - Auto Refresh */
  24 #define SD_CC_ISF               0xD     /* IP Command - Self Refresh */
  25 #define SD_CC_IPRE              0xE     /* IP command - Precharge */
  26 #define SD_CC_IPREA             0xF     /* IP command - Precharge ALL */
  27
  28 #define SEMC_MCR_MDIS           BIT(1)
  29 #define SEMC_MCR_DQSMD          BIT(2)
  30
  31 #define SEMC_INTR_IPCMDERR      BIT(1)
  32 #define SEMC_INTR_IPCMDDONE     BIT(0)
  33
  34 #define SEMC_IPCMD_KEY          0xA55A0000
  35
  36 struct imxrt_semc_regs {
  37         /* 0x0 */
  38         u32 mcr;
  39         u32 iocr;
  40         u32 bmcr0;
  41         u32 bmcr1;
  42         u32 br[9];
  43
  44         /* 0x34 */
  45         u32 res1;
  46         u32 inten;
  47         u32 intr;
  48         /* 0x40 */
  49         u32 sdramcr0;
  50         u32 sdramcr1;
  51         u32 sdramcr2;
  52         u32 sdramcr3;
  53         /* 0x50 */
  54         u32 nandcr0;
  55         u32 nandcr1;
  56         u32 nandcr2;
  57         u32 nandcr3;
  58         /* 0x60 */
  59         u32 norcr0;
  60         u32 norcr1;
  61         u32 norcr2;
  62         u32 norcr3;
  63         /* 0x70 */
  64         u32 sramcr0;
  65         u32 sramcr1;
  66         u32 sramcr2;
  67         u32 sramcr3;
  68         /* 0x80 */
  69         u32 dbicr0;
  70         u32 dbicr1;
  71         u32 res2[2];
  72         /* 0x90 */
  73         u32 ipcr0;
  74         u32 ipcr1;
  75         u32 ipcr2;
  76         u32 ipcmd;
  77         /* 0xA0 */
  78         u32 iptxdat;
  79         u32 res3[3];
  80         /* 0xB0 */
  81         u32 iprxdat;
  82         u32 res4[3];
  83         /* 0xC0 */
  84         u32 sts[16];
  85 };
  86
  87 #define SEMC_IOCR_MUX_A8_SHIFT          0
  88 #define SEMC_IOCR_MUX_CSX0_SHIFT        3
  89 #define SEMC_IOCR_MUX_CSX1_SHIFT        6
  90 #define SEMC_IOCR_MUX_CSX2_SHIFT        9
  91 #define SEMC_IOCR_MUX_CSX3_SHIFT        12
  92 #define SEMC_IOCR_MUX_RDY_SHIFT         15
  93
  94 struct imxrt_sdram_mux {
  95         u8 a8;
  96         u8 csx0;
  97         u8 csx1;
  98         u8 csx2;
  99         u8 csx3;
 100         u8 rdy;
 101 };
 102
 103 #define SEMC_SDRAMCR0_PS_SHIFT          0
 104 #define SEMC_SDRAMCR0_BL_SHIFT          4
 105 #define SEMC_SDRAMCR0_COL_SHIFT         8
 106 #define SEMC_SDRAMCR0_CL_SHIFT          10
 107
 108 struct imxrt_sdram_control {
 109         u8 memory_width;
 110         u8 burst_len;
 111         u8 no_columns;
 112         u8 cas_latency;
 113 };
 114
 115 #define SEMC_SDRAMCR1_PRE2ACT_SHIFT     0
 116 #define SEMC_SDRAMCR1_ACT2RW_SHIFT      4
 117 #define SEMC_SDRAMCR1_RFRC_SHIFT        8
 118 #define SEMC_SDRAMCR1_WRC_SHIFT         13
 119 #define SEMC_SDRAMCR1_CKEOFF_SHIFT      16
 120 #define SEMC_SDRAMCR1_ACT2PRE_SHIFT     20
 121
 122 #define SEMC_SDRAMCR2_SRRC_SHIFT        0
 123 #define SEMC_SDRAMCR2_REF2REF_SHIFT     8
 124 #define SEMC_SDRAMCR2_ACT2ACT_SHIFT     16
 125 #define SEMC_SDRAMCR2_ITO_SHIFT         24
 126
 127 #define SEMC_SDRAMCR3_REN               BIT(0)
 128 #define SEMC_SDRAMCR3_REBL_SHIFT        1
 129 #define SEMC_SDRAMCR3_PRESCALE_SHIFT    8
 130 #define SEMC_SDRAMCR3_RT_SHIFT          16
 131 #define SEMC_SDRAMCR3_UT_SHIFT          24
 132
 133 struct imxrt_sdram_timing {
 134         u8 pre2act;
 135         u8 act2rw;
 136         u8 rfrc;
 137         u8 wrc;
 138         u8 ckeoff;
 139         u8 act2pre;
 140
 141         u8 srrc;
 142         u8 ref2ref;
 143         u8 act2act;
 144         u8 ito;
 145
 146         u8 rebl;
 147         u8 prescale;
 148         u8 rt;
 149         u8 ut;
 150 };
 151
 152 enum imxrt_semc_bank {
 153         SDRAM_BANK1,
 154         SDRAM_BANK2,
 155         SDRAM_BANK3,
 156         SDRAM_BANK4,
 157         MAX_SDRAM_BANK,
 158 };
 159
 160 #define SEMC_BR_VLD_MASK                1
 161 #define SEMC_BR_MS_SHIFT                1
 162
 163 struct bank_params {
 164         enum imxrt_semc_bank target_bank;
 165         u32 base_address;
 166         u32 memory_size;
 167 };
 168
 169 struct imxrt_sdram_params {
 170         struct imxrt_semc_regs *base;
 171
 172         struct imxrt_sdram_mux *sdram_mux;
 173         struct imxrt_sdram_control *sdram_control;
 174         struct imxrt_sdram_timing *sdram_timing;
 175
 176         struct bank_params bank_params[MAX_SDRAM_BANK];
 177         u8 no_sdram_banks;
 178 };
 179
 180 static int imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs)
 181 {
 182         do {
 183                 readl(&regs->intr);
 184
 185                 if (regs->intr & SEMC_INTR_IPCMDDONE)
 186                         return 0;
 187                 if (regs->intr & SEMC_INTR_IPCMDERR)
 188                         return -EIO;
 189
 190                 mdelay(50);
 191         } while (1);
 192 }
 193
 194 static int imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr,
 195                              u32 ipcmd, u32 wd, u32 *rd)
 196 {
 197         int ret;
 198
 199         if (ipcmd == SD_CC_IWR || ipcmd == SD_CC_IMS)
 200                 writel(wd, &regs->iptxdat);
 201
 202         /* set slave address for every command as specified on RM */
 203         writel(mem_addr, &regs->ipcr0);
 204
 205         /* execute command */
 206         writel(SEMC_IPCMD_KEY | ipcmd, &regs->ipcmd);
 207
 208         ret = imxrt_sdram_wait_ipcmd_done(regs);
 209         if (ret < 0)
 210                 return ret;
 211
 212         if (ipcmd == SD_CC_IRD) {
 213                 if (!rd)
 214                         return -EINVAL;
 215
 216                 *rd = readl(&regs->iprxdat);
 217         }
 218
 219         return 0;
 220 }
 221
 222 int imxrt_sdram_init(struct udevice *dev)
 223 {
 224         struct imxrt_sdram_params *params = dev_get_platdata(dev);
 225         struct imxrt_sdram_mux *mux = params->sdram_mux;
 226         struct imxrt_sdram_control *ctrl = params->sdram_control;
 227         struct imxrt_sdram_timing *time = params->sdram_timing;
 228         struct imxrt_semc_regs *regs = params->base;
 229         struct bank_params *bank_params;
 230         u32 rd;
 231         int i;
 232
 233         /* enable the SEMC controller */
 234         clrbits_le32(&regs->mcr, SEMC_MCR_MDIS);
 235         /* set DQS mode from DQS pad */
 236         setbits_le32(&regs->mcr, SEMC_MCR_DQSMD);
 237
 238         for (i = 0, bank_params = params->bank_params;
 239                 i < params->no_sdram_banks; bank_params++,
 240                 i++)
 241                 writel((bank_params->base_address & 0xfffff000)
 242                        | bank_params->memory_size << SEMC_BR_MS_SHIFT
 243                        | SEMC_BR_VLD_MASK,
 244                        &regs->br[bank_params->target_bank]);
 245
 246         writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT
 247                 | mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT
 248                 | mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT
 249                 | mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT
 250                 | mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT
 251                 | mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT,
 252                 &regs->iocr);
 253
 254         writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT
 255                 | ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT
 256                 | ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT
 257                 | ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT,
 258                 &regs->sdramcr0);
 259
 260         writel(time->pre2act << SEMC_SDRAMCR1_PRE2ACT_SHIFT
 261                 | time->act2rw << SEMC_SDRAMCR1_ACT2RW_SHIFT
 262                 | time->rfrc << SEMC_SDRAMCR1_RFRC_SHIFT
 263                 | time->wrc << SEMC_SDRAMCR1_WRC_SHIFT
 264                 | time->ckeoff << SEMC_SDRAMCR1_CKEOFF_SHIFT
 265                 | time->act2pre << SEMC_SDRAMCR1_ACT2PRE_SHIFT,
 266                 &regs->sdramcr1);
 267
 268         writel(time->srrc << SEMC_SDRAMCR2_SRRC_SHIFT
 269                 | time->ref2ref << SEMC_SDRAMCR2_REF2REF_SHIFT
 270                 | time->act2act << SEMC_SDRAMCR2_ACT2ACT_SHIFT
 271                 | time->ito << SEMC_SDRAMCR2_ITO_SHIFT,
 272                 &regs->sdramcr2);
 273
 274         writel(time->rebl << SEMC_SDRAMCR3_REBL_SHIFT
 275                 | time->prescale << SEMC_SDRAMCR3_PRESCALE_SHIFT
 276                 | time->rt << SEMC_SDRAMCR3_RT_SHIFT
 277                 | time->ut << SEMC_SDRAMCR3_UT_SHIFT
 278                 | SEMC_SDRAMCR3_REN,
 279                 &regs->sdramcr3);
 280
 281         writel(2, &regs->ipcr1);
 282
 283         for (i = 0, bank_params = params->bank_params;
 284                 i < params->no_sdram_banks; bank_params++,
 285                 i++) {
 286                 mdelay(250);
 287                 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA,
 288                                   0, &rd);
 289                 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
 290                                   0, &rd);
 291                 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
 292                                   0, &rd);
 293                 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS,
 294                                   ctrl->burst_len | (ctrl->cas_latency << 4),
 295                                   &rd);
 296                 mdelay(250);
 297         }
 298
 299         return 0;
 300 }
 301
 302 static int imxrt_semc_ofdata_to_platdata(struct udevice *dev)
 303 {
 304         struct imxrt_sdram_params *params = dev_get_platdata(dev);
 305         ofnode bank_node;
 306         u8 bank = 0;
 307
 308         params->sdram_mux =
 309                 (struct imxrt_sdram_mux *)
 310                  dev_read_u8_array_ptr(dev,
 311                                        "fsl,sdram-mux",
 312                                        sizeof(struct imxrt_sdram_mux));
 313         if (!params->sdram_mux) {
 314                 pr_err("fsl,sdram-mux not found");
 315                 return -EINVAL;
 316         }
 317
 318         params->sdram_control =
 319                 (struct imxrt_sdram_control *)
 320                  dev_read_u8_array_ptr(dev,
 321                                        "fsl,sdram-control",
 322                                        sizeof(struct imxrt_sdram_control));
 323         if (!params->sdram_control) {
 324                 pr_err("fsl,sdram-control not found");
 325                 return -EINVAL;
 326         }
 327
 328         params->sdram_timing =
 329                 (struct imxrt_sdram_timing *)
 330                  dev_read_u8_array_ptr(dev,
 331                                        "fsl,sdram-timing",
 332                                        sizeof(struct imxrt_sdram_timing));
 333         if (!params->sdram_timing) {
 334                 pr_err("fsl,sdram-timing not found");
 335                 return -EINVAL;
 336         }
 337
 338         dev_for_each_subnode(bank_node, dev) {
 339                 struct bank_params *bank_params;
 340                 char *bank_name;
 341                 int ret;
 342
 343                 /* extract the bank index from DT */
 344                 bank_name = (char *)ofnode_get_name(bank_node);
 345                 strsep(&bank_name, "@");
 346                 if (!bank_name) {
 347                         pr_err("missing sdram bank index");
 348                         return -EINVAL;
 349                 }
 350
 351                 bank_params = &params->bank_params[bank];
 352                 strict_strtoul(bank_name, 10,
 353                                (unsigned long *)&bank_params->target_bank);
 354                 if (bank_params->target_bank >= MAX_SDRAM_BANK) {
 355                         pr_err("Found bank %d , but only bank 0,1,2,3 are supported",
 356                                bank_params->target_bank);
 357                         return -EINVAL;
 358                 }
 359
 360                 ret = ofnode_read_u32(bank_node,
 361                                       "fsl,memory-size",
 362                                       &bank_params->memory_size);
 363                 if (ret < 0) {
 364                         pr_err("fsl,memory-size not found");
 365                         return -EINVAL;
 366                 }
 367
 368                 ret = ofnode_read_u32(bank_node,
 369                                       "fsl,base-address",
 370                                       &bank_params->base_address);
 371                 if (ret < 0) {
 372                         pr_err("fsl,base-address not found");
 373                         return -EINVAL;
 374                 }
 375
 376                 debug("Found bank %s %u\n", bank_name,
 377                       bank_params->target_bank);
 378                 bank++;
 379         }
 380
 381         params->no_sdram_banks = bank;
 382         debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
 383
 384         return 0;
 385 }
 386
 387 static int imxrt_semc_probe(struct udevice *dev)
 388 {
 389         struct imxrt_sdram_params *params = dev_get_platdata(dev);
 390         int ret;
 391         fdt_addr_t addr;
 392
 393         addr = dev_read_addr(dev);
 394         if (addr == FDT_ADDR_T_NONE)
 395                 return -EINVAL;
 396
 397         params->base = (struct imxrt_semc_regs *)addr;
 398
 399 #ifdef CONFIG_CLK
 400         struct clk clk;
 401
 402         ret = clk_get_by_index(dev, 0, &clk);
 403         if (ret < 0)
 404                 return ret;
 405
 406         ret = clk_enable(&clk);
 407
 408         if (ret) {
 409                 dev_err(dev, "failed to enable clock\n");
 410                 return ret;
 411         }
 412 #endif
 413         ret = imxrt_sdram_init(dev);
 414         if (ret)
 415                 return ret;
 416
 417         return 0;
 418 }
 419
 420 static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info)
 421 {
 422         return 0;
 423 }
 424
 425 static struct ram_ops imxrt_semc_ops = {
 426         .get_info = imxrt_semc_get_info,
 427 };
 428
 429 static const struct udevice_id imxrt_semc_ids[] = {
 430         { .compatible = "fsl,imxrt-semc", .data = 0 },
 431         { }
 432 };
 433
 434 U_BOOT_DRIVER(imxrt_semc) = {
 435         .name = "imxrt_semc",
 436         .id = UCLASS_RAM,
 437         .of_match = imxrt_semc_ids,
 438         .ops = &imxrt_semc_ops,
 439         .ofdata_to_platdata = imxrt_semc_ofdata_to_platdata,
 440         .probe = imxrt_semc_probe,
 441         .platdata_auto_alloc_size = sizeof(struct imxrt_sdram_params),
 442 };