drivers/ram/imxrt_sdram.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <ram.h>
  13 #include <asm/io.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16
  17 /* SDRAM Command Code */
  18 #define SD_CC_ARD               0x0     /* Master Bus (AXI) command - Read */
  19 #define SD_CC_AWR               0x1     /* Master Bus (AXI) command - Write */
  20 #define SD_CC_IRD               0x8     /* IP command - Read */
  21 #define SD_CC_IWR               0x9     /* IP command - Write */
  22 #define SD_CC_IMS               0xA     /* IP command - Set Mode Register */
  23 #define SD_CC_IACT              0xB     /* IP command - ACTIVE */
  24 #define SD_CC_IAF               0xC     /* IP command - Auto Refresh */
  25 #define SD_CC_ISF               0xD     /* IP Command - Self Refresh */
  26 #define SD_CC_IPRE              0xE     /* IP command - Precharge */
  27 #define SD_CC_IPREA             0xF     /* IP command - Precharge ALL */
  28
  29 #define SEMC_MCR_MDIS           BIT(1)
  30 #define SEMC_MCR_DQSMD          BIT(2)
  31
  32 #define SEMC_INTR_IPCMDERR      BIT(1)
  33 #define SEMC_INTR_IPCMDDONE     BIT(0)
  34
  35 #define SEMC_IPCMD_KEY          0xA55A0000
  36
  37 struct imxrt_semc_regs {
  38         /* 0x0 */
  39         u32 mcr;
  40         u32 iocr;
  41         u32 bmcr0;
  42         u32 bmcr1;
  43         u32 br[9];
  44
  45         /* 0x34 */
  46         u32 res1;
  47         u32 inten;
  48         u32 intr;
  49         /* 0x40 */
  50         u32 sdramcr0;
  51         u32 sdramcr1;
  52         u32 sdramcr2;
  53         u32 sdramcr3;
  54         /* 0x50 */
  55         u32 nandcr0;
  56         u32 nandcr1;
  57         u32 nandcr2;
  58         u32 nandcr3;
  59         /* 0x60 */
  60         u32 norcr0;
  61         u32 norcr1;
  62         u32 norcr2;
  63         u32 norcr3;
  64         /* 0x70 */
  65         u32 sramcr0;
  66         u32 sramcr1;
  67         u32 sramcr2;
  68         u32 sramcr3;
  69         /* 0x80 */
  70         u32 dbicr0;
  71         u32 dbicr1;
  72         u32 res2[2];
  73         /* 0x90 */
  74         u32 ipcr0;
  75         u32 ipcr1;
  76         u32 ipcr2;
  77         u32 ipcmd;
  78         /* 0xA0 */
  79         u32 iptxdat;
  80         u32 res3[3];
  81         /* 0xB0 */
  82         u32 iprxdat;
  83         u32 res4[3];
  84         /* 0xC0 */
  85         u32 sts[16];
  86 };
  87
  88 #define SEMC_IOCR_MUX_A8_SHIFT          0
  89 #define SEMC_IOCR_MUX_CSX0_SHIFT        3
  90 #define SEMC_IOCR_MUX_CSX1_SHIFT        6
  91 #define SEMC_IOCR_MUX_CSX2_SHIFT        9
  92 #define SEMC_IOCR_MUX_CSX3_SHIFT        12
  93 #define SEMC_IOCR_MUX_RDY_SHIFT         15
  94
  95 struct imxrt_sdram_mux {
  96         u8 a8;
  97         u8 csx0;
  98         u8 csx1;
  99         u8 csx2;
 100         u8 csx3;
 101         u8 rdy;
 102 };
 103
 104 #define SEMC_SDRAMCR0_PS_SHIFT          0
 105 #define SEMC_SDRAMCR0_BL_SHIFT          4
 106 #define SEMC_SDRAMCR0_COL_SHIFT         8
 107 #define SEMC_SDRAMCR0_CL_SHIFT          10
 108
 109 struct imxrt_sdram_control {
 110         u8 memory_width;
 111         u8 burst_len;
 112         u8 no_columns;
 113         u8 cas_latency;
 114 };
 115
 116 #define SEMC_SDRAMCR1_PRE2ACT_SHIFT     0
 117 #define SEMC_SDRAMCR1_ACT2RW_SHIFT      4
 118 #define SEMC_SDRAMCR1_RFRC_SHIFT        8
 119 #define SEMC_SDRAMCR1_WRC_SHIFT         13
 120 #define SEMC_SDRAMCR1_CKEOFF_SHIFT      16
 121 #define SEMC_SDRAMCR1_ACT2PRE_SHIFT     20
 122
 123 #define SEMC_SDRAMCR2_SRRC_SHIFT        0
 124 #define SEMC_SDRAMCR2_REF2REF_SHIFT     8
 125 #define SEMC_SDRAMCR2_ACT2ACT_SHIFT     16
 126 #define SEMC_SDRAMCR2_ITO_SHIFT         24
 127
 128 #define SEMC_SDRAMCR3_REN               BIT(0)
 129 #define SEMC_SDRAMCR3_REBL_SHIFT        1
 130 #define SEMC_SDRAMCR3_PRESCALE_SHIFT    8
 131 #define SEMC_SDRAMCR3_RT_SHIFT          16
 132 #define SEMC_SDRAMCR3_UT_SHIFT          24
 133
 134 struct imxrt_sdram_timing {
 135         u8 pre2act;
 136         u8 act2rw;
 137         u8 rfrc;
 138         u8 wrc;
 139         u8 ckeoff;
 140         u8 act2pre;
 141
 142         u8 srrc;
 143         u8 ref2ref;
 144         u8 act2act;
 145         u8 ito;
 146
 147         u8 rebl;
 148         u8 prescale;
 149         u8 rt;
 150         u8 ut;
 151 };
 152
 153 enum imxrt_semc_bank {
 154         SDRAM_BANK1,
 155         SDRAM_BANK2,
 156         SDRAM_BANK3,
 157         SDRAM_BANK4,
 158         MAX_SDRAM_BANK,
 159 };
 160
 161 #define SEMC_BR_VLD_MASK                1
 162 #define SEMC_BR_MS_SHIFT                1
 163
 164 struct bank_params {
 165         enum imxrt_semc_bank target_bank;
 166         u32 base_address;
 167         u32 memory_size;
 168 };
 169
 170 struct imxrt_sdram_params {
 171         struct imxrt_semc_regs *base;
 172
 173         struct imxrt_sdram_mux *sdram_mux;
 174         struct imxrt_sdram_control *sdram_control;
 175         struct imxrt_sdram_timing *sdram_timing;
 176
 177         struct bank_params bank_params[MAX_SDRAM_BANK];
 178         u8 no_sdram_banks;
 179 };
 180
 181 static int imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs)
 182 {
 183         do {
 184                 readl(&regs->intr);
 185
 186                 if (regs->intr & SEMC_INTR_IPCMDDONE)
 187                         return 0;
 188                 if (regs->intr & SEMC_INTR_IPCMDERR)
 189                         return -EIO;
 190
 191                 mdelay(50);
 192         } while (1);
 193 }
 194
 195 static int imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr,
 196                              u32 ipcmd, u32 wd, u32 *rd)
 197 {
 198         int ret;
 199
 200         if (ipcmd == SD_CC_IWR || ipcmd == SD_CC_IMS)
 201                 writel(wd, &regs->iptxdat);
 202
 203         /* set slave address for every command as specified on RM */
 204         writel(mem_addr, &regs->ipcr0);
 205
 206         /* execute command */
 207         writel(SEMC_IPCMD_KEY | ipcmd, &regs->ipcmd);
 208
 209         ret = imxrt_sdram_wait_ipcmd_done(regs);
 210         if (ret < 0)
 211                 return ret;
 212
 213         if (ipcmd == SD_CC_IRD) {
 214                 if (!rd)
 215                         return -EINVAL;
 216
 217                 *rd = readl(&regs->iprxdat);
 218         }
 219
 220         return 0;
 221 }
 222
 223 int imxrt_sdram_init(struct udevice *dev)
 224 {
 225         struct imxrt_sdram_params *params = dev_get_platdata(dev);
 226         struct imxrt_sdram_mux *mux = params->sdram_mux;
 227         struct imxrt_sdram_control *ctrl = params->sdram_control;
 228         struct imxrt_sdram_timing *time = params->sdram_timing;
 229         struct imxrt_semc_regs *regs = params->base;
 230         struct bank_params *bank_params;
 231         u32 rd;
 232         int i;
 233
 234         /* enable the SEMC controller */
 235         clrbits_le32(&regs->mcr, SEMC_MCR_MDIS);
 236         /* set DQS mode from DQS pad */
 237         setbits_le32(&regs->mcr, SEMC_MCR_DQSMD);
 238
 239         for (i = 0, bank_params = params->bank_params;
 240                 i < params->no_sdram_banks; bank_params++,
 241                 i++)
 242                 writel((bank_params->base_address & 0xfffff000)
 243                        | bank_params->memory_size << SEMC_BR_MS_SHIFT
 244                        | SEMC_BR_VLD_MASK,
 245                        &regs->br[bank_params->target_bank]);
 246
 247         writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT
 248                 | mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT
 249                 | mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT
 250                 | mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT
 251                 | mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT
 252                 | mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT,
 253                 &regs->iocr);
 254
 255         writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT
 256                 | ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT
 257                 | ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT
 258                 | ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT,
 259                 &regs->sdramcr0);
 260
 261         writel(time->pre2act << SEMC_SDRAMCR1_PRE2ACT_SHIFT
 262                 | time->act2rw << SEMC_SDRAMCR1_ACT2RW_SHIFT
 263                 | time->rfrc << SEMC_SDRAMCR1_RFRC_SHIFT
 264                 | time->wrc << SEMC_SDRAMCR1_WRC_SHIFT
 265                 | time->ckeoff << SEMC_SDRAMCR1_CKEOFF_SHIFT
 266                 | time->act2pre << SEMC_SDRAMCR1_ACT2PRE_SHIFT,
 267                 &regs->sdramcr1);
 268
 269         writel(time->srrc << SEMC_SDRAMCR2_SRRC_SHIFT
 270                 | time->ref2ref << SEMC_SDRAMCR2_REF2REF_SHIFT
 271                 | time->act2act << SEMC_SDRAMCR2_ACT2ACT_SHIFT
 272                 | time->ito << SEMC_SDRAMCR2_ITO_SHIFT,
 273                 &regs->sdramcr2);
 274
 275         writel(time->rebl << SEMC_SDRAMCR3_REBL_SHIFT
 276                 | time->prescale << SEMC_SDRAMCR3_PRESCALE_SHIFT
 277                 | time->rt << SEMC_SDRAMCR3_RT_SHIFT
 278                 | time->ut << SEMC_SDRAMCR3_UT_SHIFT
 279                 | SEMC_SDRAMCR3_REN,
 280                 &regs->sdramcr3);
 281
 282         writel(2, &regs->ipcr1);
 283
 284         for (i = 0, bank_params = params->bank_params;
 285                 i < params->no_sdram_banks; bank_params++,
 286                 i++) {
 287                 mdelay(250);
 288                 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA,
 289                                   0, &rd);
 290                 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
 291                                   0, &rd);
 292                 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
 293                                   0, &rd);
 294                 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS,
 295                                   ctrl->burst_len | (ctrl->cas_latency << 4),
 296                                   &rd);
 297                 mdelay(250);
 298         }
 299
 300         return 0;
 301 }
 302
 303 static int imxrt_semc_ofdata_to_platdata(struct udevice *dev)
 304 {
 305         struct imxrt_sdram_params *params = dev_get_platdata(dev);
 306         ofnode bank_node;
 307         u8 bank = 0;
 308
 309         params->sdram_mux =
 310                 (struct imxrt_sdram_mux *)
 311                  dev_read_u8_array_ptr(dev,
 312                                        "fsl,sdram-mux",
 313                                        sizeof(struct imxrt_sdram_mux));
 314         if (!params->sdram_mux) {
 315                 pr_err("fsl,sdram-mux not found");
 316                 return -EINVAL;
 317         }
 318
 319         params->sdram_control =
 320                 (struct imxrt_sdram_control *)
 321                  dev_read_u8_array_ptr(dev,
 322                                        "fsl,sdram-control",
 323                                        sizeof(struct imxrt_sdram_control));
 324         if (!params->sdram_control) {
 325                 pr_err("fsl,sdram-control not found");
 326                 return -EINVAL;
 327         }
 328
 329         params->sdram_timing =
 330                 (struct imxrt_sdram_timing *)
 331                  dev_read_u8_array_ptr(dev,
 332                                        "fsl,sdram-timing",
 333                                        sizeof(struct imxrt_sdram_timing));
 334         if (!params->sdram_timing) {
 335                 pr_err("fsl,sdram-timing not found");
 336                 return -EINVAL;
 337         }
 338
 339         dev_for_each_subnode(bank_node, dev) {
 340                 struct bank_params *bank_params;
 341                 char *bank_name;
 342                 int ret;
 343
 344                 /* extract the bank index from DT */
 345                 bank_name = (char *)ofnode_get_name(bank_node);
 346                 strsep(&bank_name, "@");
 347                 if (!bank_name) {
 348                         pr_err("missing sdram bank index");
 349                         return -EINVAL;
 350                 }
 351
 352                 bank_params = &params->bank_params[bank];
 353                 strict_strtoul(bank_name, 10,
 354                                (unsigned long *)&bank_params->target_bank);
 355                 if (bank_params->target_bank >= MAX_SDRAM_BANK) {
 356                         pr_err("Found bank %d , but only bank 0,1,2,3 are supported",
 357                                bank_params->target_bank);
 358                         return -EINVAL;
 359                 }
 360
 361                 ret = ofnode_read_u32(bank_node,
 362                                       "fsl,memory-size",
 363                                       &bank_params->memory_size);
 364                 if (ret < 0) {
 365                         pr_err("fsl,memory-size not found");
 366                         return -EINVAL;
 367                 }
 368
 369                 ret = ofnode_read_u32(bank_node,
 370                                       "fsl,base-address",
 371                                       &bank_params->base_address);
 372                 if (ret < 0) {
 373                         pr_err("fsl,base-address not found");
 374                         return -EINVAL;
 375                 }
 376
 377                 debug("Found bank %s %u\n", bank_name,
 378                       bank_params->target_bank);
 379                 bank++;
 380         }
 381
 382         params->no_sdram_banks = bank;
 383         debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
 384
 385         return 0;
 386 }
 387
 388 static int imxrt_semc_probe(struct udevice *dev)
 389 {
 390         struct imxrt_sdram_params *params = dev_get_platdata(dev);
 391         int ret;
 392         fdt_addr_t addr;
 393
 394         addr = dev_read_addr(dev);
 395         if (addr == FDT_ADDR_T_NONE)
 396                 return -EINVAL;
 397
 398         params->base = (struct imxrt_semc_regs *)addr;
 399
 400 #ifdef CONFIG_CLK
 401         struct clk clk;
 402
 403         ret = clk_get_by_index(dev, 0, &clk);
 404         if (ret < 0)
 405                 return ret;
 406
 407         ret = clk_enable(&clk);
 408
 409         if (ret) {
 410                 dev_err(dev, "failed to enable clock\n");
 411                 return ret;
 412         }
 413 #endif
 414         ret = imxrt_sdram_init(dev);
 415         if (ret)
 416                 return ret;
 417
 418         return 0;
 419 }
 420
 421 static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info)
 422 {
 423         return 0;
 424 }
 425
 426 static struct ram_ops imxrt_semc_ops = {
 427         .get_info = imxrt_semc_get_info,
 428 };
 429
 430 static const struct udevice_id imxrt_semc_ids[] = {
 431         { .compatible = "fsl,imxrt-semc", .data = 0 },
 432         { }
 433 };
 434
 435 U_BOOT_DRIVER(imxrt_semc) = {
 436         .name = "imxrt_semc",
 437         .id = UCLASS_RAM,
 438         .of_match = imxrt_semc_ids,
 439         .ops = &imxrt_semc_ops,
 440         .ofdata_to_platdata = imxrt_semc_ofdata_to_platdata,
 441         .probe = imxrt_semc_probe,
 442         .platdata_auto_alloc_size = sizeof(struct imxrt_sdram_params),
 443 };