drivers/qe/uec.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
   4  *
   5  * Dave Liu <daveliu@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <net.h>
  10 #include <malloc.h>
  11 #include <linux/errno.h>
  12 #include <asm/io.h>
  13 #include <linux/immap_qe.h>
  14 #include "uccf.h"
  15 #include "uec.h"
  16 #include "uec_phy.h"
  17 #include "miiphy.h"
  18 #include <fsl_qe.h>
  19 #include <phy.h>
  20
  21 /* Default UTBIPAR SMI address */
  22 #ifndef CONFIG_UTBIPAR_INIT_TBIPA
  23 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
  24 #endif
  25
  26 static uec_info_t uec_info[] = {
  27 #ifdef CONFIG_UEC_ETH1
  28         STD_UEC_INFO(1),        /* UEC1 */
  29 #endif
  30 #ifdef CONFIG_UEC_ETH2
  31         STD_UEC_INFO(2),        /* UEC2 */
  32 #endif
  33 #ifdef CONFIG_UEC_ETH3
  34         STD_UEC_INFO(3),        /* UEC3 */
  35 #endif
  36 #ifdef CONFIG_UEC_ETH4
  37         STD_UEC_INFO(4),        /* UEC4 */
  38 #endif
  39 #ifdef CONFIG_UEC_ETH5
  40         STD_UEC_INFO(5),        /* UEC5 */
  41 #endif
  42 #ifdef CONFIG_UEC_ETH6
  43         STD_UEC_INFO(6),        /* UEC6 */
  44 #endif
  45 #ifdef CONFIG_UEC_ETH7
  46         STD_UEC_INFO(7),        /* UEC7 */
  47 #endif
  48 #ifdef CONFIG_UEC_ETH8
  49         STD_UEC_INFO(8),        /* UEC8 */
  50 #endif
  51 };
  52
  53 #define MAXCONTROLLERS  (8)
  54
  55 static struct eth_device *devlist[MAXCONTROLLERS];
  56
  57 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
  58 {
  59         uec_t           *uec_regs;
  60         u32             maccfg1;
  61
  62         if (!uec) {
  63                 printf("%s: uec not initial\n", __FUNCTION__);
  64                 return -EINVAL;
  65         }
  66         uec_regs = uec->uec_regs;
  67
  68         maccfg1 = in_be32(&uec_regs->maccfg1);
  69
  70         if (mode & COMM_DIR_TX) {
  71                 maccfg1 |= MACCFG1_ENABLE_TX;
  72                 out_be32(&uec_regs->maccfg1, maccfg1);
  73                 uec->mac_tx_enabled = 1;
  74         }
  75
  76         if (mode & COMM_DIR_RX) {
  77                 maccfg1 |= MACCFG1_ENABLE_RX;
  78                 out_be32(&uec_regs->maccfg1, maccfg1);
  79                 uec->mac_rx_enabled = 1;
  80         }
  81
  82         return 0;
  83 }
  84
  85 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
  86 {
  87         uec_t           *uec_regs;
  88         u32             maccfg1;
  89
  90         if (!uec) {
  91                 printf("%s: uec not initial\n", __FUNCTION__);
  92                 return -EINVAL;
  93         }
  94         uec_regs = uec->uec_regs;
  95
  96         maccfg1 = in_be32(&uec_regs->maccfg1);
  97
  98         if (mode & COMM_DIR_TX) {
  99                 maccfg1 &= ~MACCFG1_ENABLE_TX;
 100                 out_be32(&uec_regs->maccfg1, maccfg1);
 101                 uec->mac_tx_enabled = 0;
 102         }
 103
 104         if (mode & COMM_DIR_RX) {
 105                 maccfg1 &= ~MACCFG1_ENABLE_RX;
 106                 out_be32(&uec_regs->maccfg1, maccfg1);
 107                 uec->mac_rx_enabled = 0;
 108         }
 109
 110         return 0;
 111 }
 112
 113 static int uec_graceful_stop_tx(uec_private_t *uec)
 114 {
 115         ucc_fast_t              *uf_regs;
 116         u32                     cecr_subblock;
 117         u32                     ucce;
 118
 119         if (!uec || !uec->uccf) {
 120                 printf("%s: No handle passed.\n", __FUNCTION__);
 121                 return -EINVAL;
 122         }
 123
 124         uf_regs = uec->uccf->uf_regs;
 125
 126         /* Clear the grace stop event */
 127         out_be32(&uf_regs->ucce, UCCE_GRA);
 128
 129         /* Issue host command */
 130         cecr_subblock =
 131                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 132         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
 133                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 134
 135         /* Wait for command to complete */
 136         do {
 137                 ucce = in_be32(&uf_regs->ucce);
 138         } while (! (ucce & UCCE_GRA));
 139
 140         uec->grace_stopped_tx = 1;
 141
 142         return 0;
 143 }
 144
 145 static int uec_graceful_stop_rx(uec_private_t *uec)
 146 {
 147         u32             cecr_subblock;
 148         u8              ack;
 149
 150         if (!uec) {
 151                 printf("%s: No handle passed.\n", __FUNCTION__);
 152                 return -EINVAL;
 153         }
 154
 155         if (!uec->p_rx_glbl_pram) {
 156                 printf("%s: No init rx global parameter\n", __FUNCTION__);
 157                 return -EINVAL;
 158         }
 159
 160         /* Clear acknowledge bit */
 161         ack = uec->p_rx_glbl_pram->rxgstpack;
 162         ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
 163         uec->p_rx_glbl_pram->rxgstpack = ack;
 164
 165         /* Keep issuing cmd and checking ack bit until it is asserted */
 166         do {
 167                 /* Issue host command */
 168                 cecr_subblock =
 169                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 170                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
 171                                  (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 172                 ack = uec->p_rx_glbl_pram->rxgstpack;
 173         } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
 174
 175         uec->grace_stopped_rx = 1;
 176
 177         return 0;
 178 }
 179
 180 static int uec_restart_tx(uec_private_t *uec)
 181 {
 182         u32             cecr_subblock;
 183
 184         if (!uec || !uec->uec_info) {
 185                 printf("%s: No handle passed.\n", __FUNCTION__);
 186                 return -EINVAL;
 187         }
 188
 189         cecr_subblock =
 190          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 191         qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
 192                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 193
 194         uec->grace_stopped_tx = 0;
 195
 196         return 0;
 197 }
 198
 199 static int uec_restart_rx(uec_private_t *uec)
 200 {
 201         u32             cecr_subblock;
 202
 203         if (!uec || !uec->uec_info) {
 204                 printf("%s: No handle passed.\n", __FUNCTION__);
 205                 return -EINVAL;
 206         }
 207
 208         cecr_subblock =
 209          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 210         qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
 211                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 212
 213         uec->grace_stopped_rx = 0;
 214
 215         return 0;
 216 }
 217
 218 static int uec_open(uec_private_t *uec, comm_dir_e mode)
 219 {
 220         ucc_fast_private_t      *uccf;
 221
 222         if (!uec || !uec->uccf) {
 223                 printf("%s: No handle passed.\n", __FUNCTION__);
 224                 return -EINVAL;
 225         }
 226         uccf = uec->uccf;
 227
 228         /* check if the UCC number is in range. */
 229         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 230                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 231                 return -EINVAL;
 232         }
 233
 234         /* Enable MAC */
 235         uec_mac_enable(uec, mode);
 236
 237         /* Enable UCC fast */
 238         ucc_fast_enable(uccf, mode);
 239
 240         /* RISC microcode start */
 241         if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
 242                 uec_restart_tx(uec);
 243         }
 244         if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
 245                 uec_restart_rx(uec);
 246         }
 247
 248         return 0;
 249 }
 250
 251 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
 252 {
 253         if (!uec || !uec->uccf) {
 254                 printf("%s: No handle passed.\n", __FUNCTION__);
 255                 return -EINVAL;
 256         }
 257
 258         /* check if the UCC number is in range. */
 259         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 260                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 261                 return -EINVAL;
 262         }
 263         /* Stop any transmissions */
 264         if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
 265                 uec_graceful_stop_tx(uec);
 266         }
 267         /* Stop any receptions */
 268         if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
 269                 uec_graceful_stop_rx(uec);
 270         }
 271
 272         /* Disable the UCC fast */
 273         ucc_fast_disable(uec->uccf, mode);
 274
 275         /* Disable the MAC */
 276         uec_mac_disable(uec, mode);
 277
 278         return 0;
 279 }
 280
 281 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
 282 {
 283         uec_t           *uec_regs;
 284         u32             maccfg2;
 285
 286         if (!uec) {
 287                 printf("%s: uec not initial\n", __FUNCTION__);
 288                 return -EINVAL;
 289         }
 290         uec_regs = uec->uec_regs;
 291
 292         if (duplex == DUPLEX_HALF) {
 293                 maccfg2 = in_be32(&uec_regs->maccfg2);
 294                 maccfg2 &= ~MACCFG2_FDX;
 295                 out_be32(&uec_regs->maccfg2, maccfg2);
 296         }
 297
 298         if (duplex == DUPLEX_FULL) {
 299                 maccfg2 = in_be32(&uec_regs->maccfg2);
 300                 maccfg2 |= MACCFG2_FDX;
 301                 out_be32(&uec_regs->maccfg2, maccfg2);
 302         }
 303
 304         return 0;
 305 }
 306
 307 static int uec_set_mac_if_mode(uec_private_t *uec,
 308                 phy_interface_t if_mode, int speed)
 309 {
 310         phy_interface_t         enet_if_mode;
 311         uec_t                   *uec_regs;
 312         u32                     upsmr;
 313         u32                     maccfg2;
 314
 315         if (!uec) {
 316                 printf("%s: uec not initial\n", __FUNCTION__);
 317                 return -EINVAL;
 318         }
 319
 320         uec_regs = uec->uec_regs;
 321         enet_if_mode = if_mode;
 322
 323         maccfg2 = in_be32(&uec_regs->maccfg2);
 324         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
 325
 326         upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
 327         upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
 328
 329         switch (speed) {
 330                 case SPEED_10:
 331                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 332                         switch (enet_if_mode) {
 333                                 case PHY_INTERFACE_MODE_MII:
 334                                         break;
 335                                 case PHY_INTERFACE_MODE_RGMII:
 336                                         upsmr |= (UPSMR_RPM | UPSMR_R10M);
 337                                         break;
 338                                 case PHY_INTERFACE_MODE_RMII:
 339                                         upsmr |= (UPSMR_R10M | UPSMR_RMM);
 340                                         break;
 341                                 default:
 342                                         return -EINVAL;
 343                                         break;
 344                         }
 345                         break;
 346                 case SPEED_100:
 347                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 348                         switch (enet_if_mode) {
 349                                 case PHY_INTERFACE_MODE_MII:
 350                                         break;
 351                                 case PHY_INTERFACE_MODE_RGMII:
 352                                         upsmr |= UPSMR_RPM;
 353                                         break;
 354                                 case PHY_INTERFACE_MODE_RMII:
 355                                         upsmr |= UPSMR_RMM;
 356                                         break;
 357                                 default:
 358                                         return -EINVAL;
 359                                         break;
 360                         }
 361                         break;
 362                 case SPEED_1000:
 363                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 364                         switch (enet_if_mode) {
 365                                 case PHY_INTERFACE_MODE_GMII:
 366                                         break;
 367                                 case PHY_INTERFACE_MODE_TBI:
 368                                         upsmr |= UPSMR_TBIM;
 369                                         break;
 370                                 case PHY_INTERFACE_MODE_RTBI:
 371                                         upsmr |= (UPSMR_RPM | UPSMR_TBIM);
 372                                         break;
 373                                 case PHY_INTERFACE_MODE_RGMII_RXID:
 374                                 case PHY_INTERFACE_MODE_RGMII_TXID:
 375                                 case PHY_INTERFACE_MODE_RGMII_ID:
 376                                 case PHY_INTERFACE_MODE_RGMII:
 377                                         upsmr |= UPSMR_RPM;
 378                                         break;
 379                                 case PHY_INTERFACE_MODE_SGMII:
 380                                         upsmr |= UPSMR_SGMM;
 381                                         break;
 382                                 default:
 383                                         return -EINVAL;
 384                                         break;
 385                         }
 386                         break;
 387                 default:
 388                         return -EINVAL;
 389                         break;
 390         }
 391
 392         out_be32(&uec_regs->maccfg2, maccfg2);
 393         out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
 394
 395         return 0;
 396 }
 397
 398 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
 399 {
 400         uint            timeout = 0x1000;
 401         u32             miimcfg = 0;
 402
 403         miimcfg = in_be32(&uec_mii_regs->miimcfg);
 404         miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
 405         out_be32(&uec_mii_regs->miimcfg, miimcfg);
 406
 407         /* Wait until the bus is free */
 408         while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
 409         if (timeout <= 0) {
 410                 printf("%s: The MII Bus is stuck!", __FUNCTION__);
 411                 return -ETIMEDOUT;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static int init_phy(struct eth_device *dev)
 418 {
 419         uec_private_t           *uec;
 420         uec_mii_t               *umii_regs;
 421         struct uec_mii_info     *mii_info;
 422         struct phy_info         *curphy;
 423         int                     err;
 424
 425         uec = (uec_private_t *)dev->priv;
 426         umii_regs = uec->uec_mii_regs;
 427
 428         uec->oldlink = 0;
 429         uec->oldspeed = 0;
 430         uec->oldduplex = -1;
 431
 432         mii_info = malloc(sizeof(*mii_info));
 433         if (!mii_info) {
 434                 printf("%s: Could not allocate mii_info", dev->name);
 435                 return -ENOMEM;
 436         }
 437         memset(mii_info, 0, sizeof(*mii_info));
 438
 439         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 440                 mii_info->speed = SPEED_1000;
 441         } else {
 442                 mii_info->speed = SPEED_100;
 443         }
 444
 445         mii_info->duplex = DUPLEX_FULL;
 446         mii_info->pause = 0;
 447         mii_info->link = 1;
 448
 449         mii_info->advertising = (ADVERTISED_10baseT_Half |
 450                                 ADVERTISED_10baseT_Full |
 451                                 ADVERTISED_100baseT_Half |
 452                                 ADVERTISED_100baseT_Full |
 453                                 ADVERTISED_1000baseT_Full);
 454         mii_info->autoneg = 1;
 455         mii_info->mii_id = uec->uec_info->phy_address;
 456         mii_info->dev = dev;
 457
 458         mii_info->mdio_read = &uec_read_phy_reg;
 459         mii_info->mdio_write = &uec_write_phy_reg;
 460
 461         uec->mii_info = mii_info;
 462
 463         qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
 464
 465         if (init_mii_management_configuration(umii_regs)) {
 466                 printf("%s: The MII Bus is stuck!", dev->name);
 467                 err = -1;
 468                 goto bus_fail;
 469         }
 470
 471         /* get info for this PHY */
 472         curphy = uec_get_phy_info(uec->mii_info);
 473         if (!curphy) {
 474                 printf("%s: No PHY found", dev->name);
 475                 err = -1;
 476                 goto no_phy;
 477         }
 478
 479         mii_info->phyinfo = curphy;
 480
 481         /* Run the commands which initialize the PHY */
 482         if (curphy->init) {
 483                 err = curphy->init(uec->mii_info);
 484                 if (err)
 485                         goto phy_init_fail;
 486         }
 487
 488         return 0;
 489
 490 phy_init_fail:
 491 no_phy:
 492 bus_fail:
 493         free(mii_info);
 494         return err;
 495 }
 496
 497 static void adjust_link(struct eth_device *dev)
 498 {
 499         uec_private_t           *uec = (uec_private_t *)dev->priv;
 500         struct uec_mii_info     *mii_info = uec->mii_info;
 501
 502         extern void change_phy_interface_mode(struct eth_device *dev,
 503                                  phy_interface_t mode, int speed);
 504
 505         if (mii_info->link) {
 506                 /* Now we make sure that we can be in full duplex mode.
 507                 * If not, we operate in half-duplex mode. */
 508                 if (mii_info->duplex != uec->oldduplex) {
 509                         if (!(mii_info->duplex)) {
 510                                 uec_set_mac_duplex(uec, DUPLEX_HALF);
 511                                 printf("%s: Half Duplex\n", dev->name);
 512                         } else {
 513                                 uec_set_mac_duplex(uec, DUPLEX_FULL);
 514                                 printf("%s: Full Duplex\n", dev->name);
 515                         }
 516                         uec->oldduplex = mii_info->duplex;
 517                 }
 518
 519                 if (mii_info->speed != uec->oldspeed) {
 520                         phy_interface_t mode =
 521                                 uec->uec_info->enet_interface_type;
 522                         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 523                                 switch (mii_info->speed) {
 524                                 case SPEED_1000:
 525                                         break;
 526                                 case SPEED_100:
 527                                         printf ("switching to rgmii 100\n");
 528                                         mode = PHY_INTERFACE_MODE_RGMII;
 529                                         break;
 530                                 case SPEED_10:
 531                                         printf ("switching to rgmii 10\n");
 532                                         mode = PHY_INTERFACE_MODE_RGMII;
 533                                         break;
 534                                 default:
 535                                         printf("%s: Ack,Speed(%d)is illegal\n",
 536                                                 dev->name, mii_info->speed);
 537                                         break;
 538                                 }
 539                         }
 540
 541                         /* change phy */
 542                         change_phy_interface_mode(dev, mode, mii_info->speed);
 543                         /* change the MAC interface mode */
 544                         uec_set_mac_if_mode(uec, mode, mii_info->speed);
 545
 546                         printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
 547                         uec->oldspeed = mii_info->speed;
 548                 }
 549
 550                 if (!uec->oldlink) {
 551                         printf("%s: Link is up\n", dev->name);
 552                         uec->oldlink = 1;
 553                 }
 554
 555         } else { /* if (mii_info->link) */
 556                 if (uec->oldlink) {
 557                         printf("%s: Link is down\n", dev->name);
 558                         uec->oldlink = 0;
 559                         uec->oldspeed = 0;
 560                         uec->oldduplex = -1;
 561                 }
 562         }
 563 }
 564
 565 static void phy_change(struct eth_device *dev)
 566 {
 567         uec_private_t   *uec = (uec_private_t *)dev->priv;
 568
 569 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
 570         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 571
 572         /* QE9 and QE12 need to be set for enabling QE MII managment signals */
 573         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
 574         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
 575 #endif
 576
 577         /* Update the link, speed, duplex */
 578         uec->mii_info->phyinfo->read_status(uec->mii_info);
 579
 580 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
 581         /*
 582          * QE12 is muxed with LBCTL, it needs to be released for enabling
 583          * LBCTL signal for LBC usage.
 584          */
 585         clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
 586 #endif
 587
 588         /* Adjust the interface according to speed */
 589         adjust_link(dev);
 590 }
 591
 592 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 593
 594 /*
 595  * Find a device index from the devlist by name
 596  *
 597  * Returns:
 598  *  The index where the device is located, -1 on error
 599  */
 600 static int uec_miiphy_find_dev_by_name(const char *devname)
 601 {
 602         int i;
 603
 604         for (i = 0; i < MAXCONTROLLERS; i++) {
 605                 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
 606                         break;
 607                 }
 608         }
 609
 610         /* If device cannot be found, returns -1 */
 611         if (i == MAXCONTROLLERS) {
 612                 debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
 613                 i = -1;
 614         }
 615
 616         return i;
 617 }
 618
 619 /*
 620  * Read a MII PHY register.
 621  *
 622  * Returns:
 623  *  0 on success
 624  */
 625 static int uec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
 626 {
 627         unsigned short value = 0;
 628         int devindex = 0;
 629
 630         if (bus->name == NULL) {
 631                 debug("%s: NULL pointer given\n", __FUNCTION__);
 632         } else {
 633                 devindex = uec_miiphy_find_dev_by_name(bus->name);
 634                 if (devindex >= 0) {
 635                         value = uec_read_phy_reg(devlist[devindex], addr, reg);
 636                 }
 637         }
 638         return value;
 639 }
 640
 641 /*
 642  * Write a MII PHY register.
 643  *
 644  * Returns:
 645  *  0 on success
 646  */
 647 static int uec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
 648                             u16 value)
 649 {
 650         int devindex = 0;
 651
 652         if (bus->name == NULL) {
 653                 debug("%s: NULL pointer given\n", __FUNCTION__);
 654         } else {
 655                 devindex = uec_miiphy_find_dev_by_name(bus->name);
 656                 if (devindex >= 0) {
 657                         uec_write_phy_reg(devlist[devindex], addr, reg, value);
 658                 }
 659         }
 660         return 0;
 661 }
 662 #endif
 663
 664 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
 665 {
 666         uec_t           *uec_regs;
 667         u32             mac_addr1;
 668         u32             mac_addr2;
 669
 670         if (!uec) {
 671                 printf("%s: uec not initial\n", __FUNCTION__);
 672                 return -EINVAL;
 673         }
 674
 675         uec_regs = uec->uec_regs;
 676
 677         /* if a station address of 0x12345678ABCD, perform a write to
 678         MACSTNADDR1 of 0xCDAB7856,
 679         MACSTNADDR2 of 0x34120000 */
 680
 681         mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
 682                         (mac_addr[3] << 8)  | (mac_addr[2]);
 683         out_be32(&uec_regs->macstnaddr1, mac_addr1);
 684
 685         mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
 686         out_be32(&uec_regs->macstnaddr2, mac_addr2);
 687
 688         return 0;
 689 }
 690
 691 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
 692                                          int *threads_num_ret)
 693 {
 694         int     num_threads_numerica;
 695
 696         switch (threads_num) {
 697                 case UEC_NUM_OF_THREADS_1:
 698                         num_threads_numerica = 1;
 699                         break;
 700                 case UEC_NUM_OF_THREADS_2:
 701                         num_threads_numerica = 2;
 702                         break;
 703                 case UEC_NUM_OF_THREADS_4:
 704                         num_threads_numerica = 4;
 705                         break;
 706                 case UEC_NUM_OF_THREADS_6:
 707                         num_threads_numerica = 6;
 708                         break;
 709                 case UEC_NUM_OF_THREADS_8:
 710                         num_threads_numerica = 8;
 711                         break;
 712                 default:
 713                         printf("%s: Bad number of threads value.",
 714                                  __FUNCTION__);
 715                         return -EINVAL;
 716         }
 717
 718         *threads_num_ret = num_threads_numerica;
 719
 720         return 0;
 721 }
 722
 723 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
 724 {
 725         uec_info_t      *uec_info;
 726         u32             end_bd;
 727         u8              bmrx = 0;
 728         int             i;
 729
 730         uec_info = uec->uec_info;
 731
 732         /* Alloc global Tx parameter RAM page */
 733         uec->tx_glbl_pram_offset = qe_muram_alloc(
 734                                 sizeof(uec_tx_global_pram_t),
 735                                  UEC_TX_GLOBAL_PRAM_ALIGNMENT);
 736         uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
 737                                 qe_muram_addr(uec->tx_glbl_pram_offset);
 738
 739         /* Zero the global Tx prameter RAM */
 740         memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
 741
 742         /* Init global Tx parameter RAM */
 743
 744         /* TEMODER, RMON statistics disable, one Tx queue */
 745         out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
 746
 747         /* SQPTR */
 748         uec->send_q_mem_reg_offset = qe_muram_alloc(
 749                                 sizeof(uec_send_queue_qd_t),
 750                                  UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
 751         uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
 752                                 qe_muram_addr(uec->send_q_mem_reg_offset);
 753         out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
 754
 755         /* Setup the table with TxBDs ring */
 756         end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
 757                                          * SIZEOFBD;
 758         out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
 759                                  (u32)(uec->p_tx_bd_ring));
 760         out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
 761                                                  end_bd);
 762
 763         /* Scheduler Base Pointer, we have only one Tx queue, no need it */
 764         out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
 765
 766         /* TxRMON Base Pointer, TxRMON disable, we don't need it */
 767         out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
 768
 769         /* TSTATE, global snooping, big endian, the CSB bus selected */
 770         bmrx = BMR_INIT_VALUE;
 771         out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
 772
 773         /* IPH_Offset */
 774         for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
 775                 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
 776         }
 777
 778         /* VTAG table */
 779         for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
 780                 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
 781         }
 782
 783         /* TQPTR */
 784         uec->thread_dat_tx_offset = qe_muram_alloc(
 785                 num_threads_tx * sizeof(uec_thread_data_tx_t) +
 786                  32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
 787
 788         uec->p_thread_data_tx = (uec_thread_data_tx_t *)
 789                                 qe_muram_addr(uec->thread_dat_tx_offset);
 790         out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
 791 }
 792
 793 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
 794 {
 795         u8      bmrx = 0;
 796         int     i;
 797         uec_82xx_address_filtering_pram_t       *p_af_pram;
 798
 799         /* Allocate global Rx parameter RAM page */
 800         uec->rx_glbl_pram_offset = qe_muram_alloc(
 801                 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
 802         uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
 803                                 qe_muram_addr(uec->rx_glbl_pram_offset);
 804
 805         /* Zero Global Rx parameter RAM */
 806         memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
 807
 808         /* Init global Rx parameter RAM */
 809         /* REMODER, Extended feature mode disable, VLAN disable,
 810          LossLess flow control disable, Receive firmware statisic disable,
 811          Extended address parsing mode disable, One Rx queues,
 812          Dynamic maximum/minimum frame length disable, IP checksum check
 813          disable, IP address alignment disable
 814         */
 815         out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
 816
 817         /* RQPTR */
 818         uec->thread_dat_rx_offset = qe_muram_alloc(
 819                         num_threads_rx * sizeof(uec_thread_data_rx_t),
 820                          UEC_THREAD_DATA_ALIGNMENT);
 821         uec->p_thread_data_rx = (uec_thread_data_rx_t *)
 822                                 qe_muram_addr(uec->thread_dat_rx_offset);
 823         out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
 824
 825         /* Type_or_Len */
 826         out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
 827
 828         /* RxRMON base pointer, we don't need it */
 829         out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
 830
 831         /* IntCoalescingPTR, we don't need it, no interrupt */
 832         out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
 833
 834         /* RSTATE, global snooping, big endian, the CSB bus selected */
 835         bmrx = BMR_INIT_VALUE;
 836         out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
 837
 838         /* MRBLR */
 839         out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
 840
 841         /* RBDQPTR */
 842         uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
 843                                 sizeof(uec_rx_bd_queues_entry_t) + \
 844                                 sizeof(uec_rx_prefetched_bds_t),
 845                                  UEC_RX_BD_QUEUES_ALIGNMENT);
 846         uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
 847                                 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
 848
 849         /* Zero it */
 850         memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
 851                                         sizeof(uec_rx_prefetched_bds_t));
 852         out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
 853         out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
 854                  (u32)uec->p_rx_bd_ring);
 855
 856         /* MFLR */
 857         out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
 858         /* MINFLR */
 859         out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
 860         /* MAXD1 */
 861         out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
 862         /* MAXD2 */
 863         out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
 864         /* ECAM_PTR */
 865         out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
 866         /* L2QT */
 867         out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
 868         /* L3QT */
 869         for (i = 0; i < 8; i++) {
 870                 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
 871         }
 872
 873         /* VLAN_TYPE */
 874         out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
 875         /* TCI */
 876         out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
 877
 878         /* Clear PQ2 style address filtering hash table */
 879         p_af_pram = (uec_82xx_address_filtering_pram_t *) \
 880                         uec->p_rx_glbl_pram->addressfiltering;
 881
 882         p_af_pram->iaddr_h = 0;
 883         p_af_pram->iaddr_l = 0;
 884         p_af_pram->gaddr_h = 0;
 885         p_af_pram->gaddr_l = 0;
 886 }
 887
 888 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
 889                                          int thread_tx, int thread_rx)
 890 {
 891         uec_init_cmd_pram_t             *p_init_enet_param;
 892         u32                             init_enet_param_offset;
 893         uec_info_t                      *uec_info;
 894         int                             i;
 895         int                             snum;
 896         u32                             init_enet_offset;
 897         u32                             entry_val;
 898         u32                             command;
 899         u32                             cecr_subblock;
 900
 901         uec_info = uec->uec_info;
 902
 903         /* Allocate init enet command parameter */
 904         uec->init_enet_param_offset = qe_muram_alloc(
 905                                         sizeof(uec_init_cmd_pram_t), 4);
 906         init_enet_param_offset = uec->init_enet_param_offset;
 907         uec->p_init_enet_param = (uec_init_cmd_pram_t *)
 908                                 qe_muram_addr(uec->init_enet_param_offset);
 909
 910         /* Zero init enet command struct */
 911         memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
 912
 913         /* Init the command struct */
 914         p_init_enet_param = uec->p_init_enet_param;
 915         p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
 916         p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
 917         p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
 918         p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
 919         p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
 920         p_init_enet_param->largestexternallookupkeysize = 0;
 921
 922         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
 923                                          << ENET_INIT_PARAM_RGF_SHIFT;
 924         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
 925                                          << ENET_INIT_PARAM_TGF_SHIFT;
 926
 927         /* Init Rx global parameter pointer */
 928         p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
 929                                                  (u32)uec_info->risc_rx;
 930
 931         /* Init Rx threads */
 932         for (i = 0; i < (thread_rx + 1); i++) {
 933                 if ((snum = qe_get_snum()) < 0) {
 934                         printf("%s can not get snum\n", __FUNCTION__);
 935                         return -ENOMEM;
 936                 }
 937
 938                 if (i==0) {
 939                         init_enet_offset = 0;
 940                 } else {
 941                         init_enet_offset = qe_muram_alloc(
 942                                         sizeof(uec_thread_rx_pram_t),
 943                                          UEC_THREAD_RX_PRAM_ALIGNMENT);
 944                 }
 945
 946                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 947                                  init_enet_offset | (u32)uec_info->risc_rx;
 948                 p_init_enet_param->rxthread[i] = entry_val;
 949         }
 950
 951         /* Init Tx global parameter pointer */
 952         p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
 953                                          (u32)uec_info->risc_tx;
 954
 955         /* Init Tx threads */
 956         for (i = 0; i < thread_tx; i++) {
 957                 if ((snum = qe_get_snum()) < 0) {
 958                         printf("%s can not get snum\n", __FUNCTION__);
 959                         return -ENOMEM;
 960                 }
 961
 962                 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
 963                                                  UEC_THREAD_TX_PRAM_ALIGNMENT);
 964
 965                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 966                                  init_enet_offset | (u32)uec_info->risc_tx;
 967                 p_init_enet_param->txthread[i] = entry_val;
 968         }
 969
 970         __asm__ __volatile__("sync");
 971
 972         /* Issue QE command */
 973         command = QE_INIT_TX_RX;
 974         cecr_subblock = ucc_fast_get_qe_cr_subblock(
 975                                 uec->uec_info->uf_info.ucc_num);
 976         qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
 977                                                  init_enet_param_offset);
 978
 979         return 0;
 980 }
 981
 982 static int uec_startup(uec_private_t *uec)
 983 {
 984         uec_info_t                      *uec_info;
 985         ucc_fast_info_t                 *uf_info;
 986         ucc_fast_private_t              *uccf;
 987         ucc_fast_t                      *uf_regs;
 988         uec_t                           *uec_regs;
 989         int                             num_threads_tx;
 990         int                             num_threads_rx;
 991         u32                             utbipar;
 992         u32                             length;
 993         u32                             align;
 994         qe_bd_t                         *bd;
 995         u8                              *buf;
 996         int                             i;
 997
 998         if (!uec || !uec->uec_info) {
 999                 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1000                 return -EINVAL;
1001         }
1002
1003         uec_info = uec->uec_info;
1004         uf_info = &(uec_info->uf_info);
1005
1006         /* Check if Rx BD ring len is illegal */
1007         if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1008                 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1009                 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1010                          __FUNCTION__);
1011                 return -EINVAL;
1012         }
1013
1014         /* Check if Tx BD ring len is illegal */
1015         if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1016                 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1017                          __FUNCTION__);
1018                 return -EINVAL;
1019         }
1020
1021         /* Check if MRBLR is illegal */
1022         if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
1023                 printf("%s: max rx buffer length must be mutliple of 128.\n",
1024                          __FUNCTION__);
1025                 return -EINVAL;
1026         }
1027
1028         /* Both Rx and Tx are stopped */
1029         uec->grace_stopped_rx = 1;
1030         uec->grace_stopped_tx = 1;
1031
1032         /* Init UCC fast */
1033         if (ucc_fast_init(uf_info, &uccf)) {
1034                 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1035                 return -ENOMEM;
1036         }
1037
1038         /* Save uccf */
1039         uec->uccf = uccf;
1040
1041         /* Convert the Tx threads number */
1042         if (uec_convert_threads_num(uec_info->num_threads_tx,
1043                                          &num_threads_tx)) {
1044                 return -EINVAL;
1045         }
1046
1047         /* Convert the Rx threads number */
1048         if (uec_convert_threads_num(uec_info->num_threads_rx,
1049                                          &num_threads_rx)) {
1050                 return -EINVAL;
1051         }
1052
1053         uf_regs = uccf->uf_regs;
1054
1055         /* UEC register is following UCC fast registers */
1056         uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1057
1058         /* Save the UEC register pointer to UEC private struct */
1059         uec->uec_regs = uec_regs;
1060
1061         /* Init UPSMR, enable hardware statistics (UCC) */
1062         out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1063
1064         /* Init MACCFG1, flow control disable, disable Tx and Rx */
1065         out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1066
1067         /* Init MACCFG2, length check, MAC PAD and CRC enable */
1068         out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1069
1070         /* Setup MAC interface mode */
1071         uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed);
1072
1073         /* Setup MII management base */
1074 #ifndef CONFIG_eTSEC_MDIO_BUS
1075         uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1076 #else
1077         uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1078 #endif
1079
1080         /* Setup MII master clock source */
1081         qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1082
1083         /* Setup UTBIPAR */
1084         utbipar = in_be32(&uec_regs->utbipar);
1085         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1086
1087         /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
1088          * This frees up the remaining SMI addresses for use.
1089          */
1090         utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
1091         out_be32(&uec_regs->utbipar, utbipar);
1092
1093         /* Configure the TBI for SGMII operation */
1094         if ((uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII) &&
1095            (uec->uec_info->speed == SPEED_1000)) {
1096                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1097                         ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1098
1099                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1100                         ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1101
1102                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1103                         ENET_TBI_MII_CR, TBICR_SETTINGS);
1104         }
1105
1106         /* Allocate Tx BDs */
1107         length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1108                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1109                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1110         if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1111                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1112                 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1113         }
1114
1115         align = UEC_TX_BD_RING_ALIGNMENT;
1116         uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1117         if (uec->tx_bd_ring_offset != 0) {
1118                 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1119                                                  & ~(align - 1));
1120         }
1121
1122         /* Zero all of Tx BDs */
1123         memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1124
1125         /* Allocate Rx BDs */
1126         length = uec_info->rx_bd_ring_len * SIZEOFBD;
1127         align = UEC_RX_BD_RING_ALIGNMENT;
1128         uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1129         if (uec->rx_bd_ring_offset != 0) {
1130                 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1131                                                          & ~(align - 1));
1132         }
1133
1134         /* Zero all of Rx BDs */
1135         memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1136
1137         /* Allocate Rx buffer */
1138         length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1139         align = UEC_RX_DATA_BUF_ALIGNMENT;
1140         uec->rx_buf_offset = (u32)malloc(length + align);
1141         if (uec->rx_buf_offset != 0) {
1142                 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1143                                                  & ~(align - 1));
1144         }
1145
1146         /* Zero all of the Rx buffer */
1147         memset((void *)(uec->rx_buf_offset), 0, length + align);
1148
1149         /* Init TxBD ring */
1150         bd = (qe_bd_t *)uec->p_tx_bd_ring;
1151         uec->txBd = bd;
1152
1153         for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1154                 BD_DATA_CLEAR(bd);
1155                 BD_STATUS_SET(bd, 0);
1156                 BD_LENGTH_SET(bd, 0);
1157                 bd ++;
1158         }
1159         BD_STATUS_SET((--bd), TxBD_WRAP);
1160
1161         /* Init RxBD ring */
1162         bd = (qe_bd_t *)uec->p_rx_bd_ring;
1163         uec->rxBd = bd;
1164         buf = uec->p_rx_buf;
1165         for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1166                 BD_DATA_SET(bd, buf);
1167                 BD_LENGTH_SET(bd, 0);
1168                 BD_STATUS_SET(bd, RxBD_EMPTY);
1169                 buf += MAX_RXBUF_LEN;
1170                 bd ++;
1171         }
1172         BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1173
1174         /* Init global Tx parameter RAM */
1175         uec_init_tx_parameter(uec, num_threads_tx);
1176
1177         /* Init global Rx parameter RAM */
1178         uec_init_rx_parameter(uec, num_threads_rx);
1179
1180         /* Init ethernet Tx and Rx parameter command */
1181         if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1182                                          num_threads_rx)) {
1183                 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1184                 return -ENOMEM;
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int uec_init(struct eth_device* dev, bd_t *bd)
1191 {
1192         uec_private_t           *uec;
1193         int                     err, i;
1194         struct phy_info         *curphy;
1195 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
1196         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
1197 #endif
1198
1199         uec = (uec_private_t *)dev->priv;
1200
1201         if (uec->the_first_run == 0) {
1202 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
1203         /* QE9 and QE12 need to be set for enabling QE MII managment signals */
1204         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
1205         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1206 #endif
1207
1208                 err = init_phy(dev);
1209                 if (err) {
1210                         printf("%s: Cannot initialize PHY, aborting.\n",
1211                                dev->name);
1212                         return err;
1213                 }
1214
1215                 curphy = uec->mii_info->phyinfo;
1216
1217                 if (curphy->config_aneg) {
1218                         err = curphy->config_aneg(uec->mii_info);
1219                         if (err) {
1220                                 printf("%s: Can't negotiate PHY\n", dev->name);
1221                                 return err;
1222                         }
1223                 }
1224
1225                 /* Give PHYs up to 5 sec to report a link */
1226                 i = 50;
1227                 do {
1228                         err = curphy->read_status(uec->mii_info);
1229                         if (!(((i-- > 0) && !uec->mii_info->link) || err))
1230                                 break;
1231                         udelay(100000);
1232                 } while (1);
1233
1234 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
1235                 /* QE12 needs to be released for enabling LBCTL signal*/
1236                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1237 #endif
1238
1239                 if (err || i <= 0)
1240                         printf("warning: %s: timeout on PHY link\n", dev->name);
1241
1242                 adjust_link(dev);
1243                 uec->the_first_run = 1;
1244         }
1245
1246         /* Set up the MAC address */
1247         if (dev->enetaddr[0] & 0x01) {
1248                 printf("%s: MacAddress is multcast address\n",
1249                          __FUNCTION__);
1250                 return -1;
1251         }
1252         uec_set_mac_address(uec, dev->enetaddr);
1253
1254
1255         err = uec_open(uec, COMM_DIR_RX_AND_TX);
1256         if (err) {
1257                 printf("%s: cannot enable UEC device\n", dev->name);
1258                 return -1;
1259         }
1260
1261         phy_change(dev);
1262
1263         return (uec->mii_info->link ? 0 : -1);
1264 }
1265
1266 static void uec_halt(struct eth_device* dev)
1267 {
1268         uec_private_t   *uec = (uec_private_t *)dev->priv;
1269         uec_stop(uec, COMM_DIR_RX_AND_TX);
1270 }
1271
1272 static int uec_send(struct eth_device *dev, void *buf, int len)
1273 {
1274         uec_private_t           *uec;
1275         ucc_fast_private_t      *uccf;
1276         volatile qe_bd_t        *bd;
1277         u16                     status;
1278         int                     i;
1279         int                     result = 0;
1280
1281         uec = (uec_private_t *)dev->priv;
1282         uccf = uec->uccf;
1283         bd = uec->txBd;
1284
1285         /* Find an empty TxBD */
1286         for (i = 0; bd->status & TxBD_READY; i++) {
1287                 if (i > 0x100000) {
1288                         printf("%s: tx buffer not ready\n", dev->name);
1289                         return result;
1290                 }
1291         }
1292
1293         /* Init TxBD */
1294         BD_DATA_SET(bd, buf);
1295         BD_LENGTH_SET(bd, len);
1296         status = bd->status;
1297         status &= BD_WRAP;
1298         status |= (TxBD_READY | TxBD_LAST);
1299         BD_STATUS_SET(bd, status);
1300
1301         /* Tell UCC to transmit the buffer */
1302         ucc_fast_transmit_on_demand(uccf);
1303
1304         /* Wait for buffer to be transmitted */
1305         for (i = 0; bd->status & TxBD_READY; i++) {
1306                 if (i > 0x100000) {
1307                         printf("%s: tx error\n", dev->name);
1308                         return result;
1309                 }
1310         }
1311
1312         /* Ok, the buffer be transimitted */
1313         BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1314         uec->txBd = bd;
1315         result = 1;
1316
1317         return result;
1318 }
1319
1320 static int uec_recv(struct eth_device* dev)
1321 {
1322         uec_private_t           *uec = dev->priv;
1323         volatile qe_bd_t        *bd;
1324         u16                     status;
1325         u16                     len;
1326         u8                      *data;
1327
1328         bd = uec->rxBd;
1329         status = bd->status;
1330
1331         while (!(status & RxBD_EMPTY)) {
1332                 if (!(status & RxBD_ERROR)) {
1333                         data = BD_DATA(bd);
1334                         len = BD_LENGTH(bd);
1335                         net_process_received_packet(data, len);
1336                 } else {
1337                         printf("%s: Rx error\n", dev->name);
1338                 }
1339                 status &= BD_CLEAN;
1340                 BD_LENGTH_SET(bd, 0);
1341                 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1342                 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1343                 status = bd->status;
1344         }
1345         uec->rxBd = bd;
1346
1347         return 1;
1348 }
1349
1350 int uec_initialize(bd_t *bis, uec_info_t *uec_info)
1351 {
1352         struct eth_device       *dev;
1353         int                     i;
1354         uec_private_t           *uec;
1355         int                     err;
1356
1357         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1358         if (!dev)
1359                 return 0;
1360         memset(dev, 0, sizeof(struct eth_device));
1361
1362         /* Allocate the UEC private struct */
1363         uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1364         if (!uec) {
1365                 return -ENOMEM;
1366         }
1367         memset(uec, 0, sizeof(uec_private_t));
1368
1369         /* Adjust uec_info */
1370 #if (MAX_QE_RISC == 4)
1371         uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
1372         uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
1373 #endif
1374
1375         devlist[uec_info->uf_info.ucc_num] = dev;
1376
1377         uec->uec_info = uec_info;
1378         uec->dev = dev;
1379
1380         sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
1381         dev->iobase = 0;
1382         dev->priv = (void *)uec;
1383         dev->init = uec_init;
1384         dev->halt = uec_halt;
1385         dev->send = uec_send;
1386         dev->recv = uec_recv;
1387
1388         /* Clear the ethnet address */
1389         for (i = 0; i < 6; i++)
1390                 dev->enetaddr[i] = 0;
1391
1392         eth_register(dev);
1393
1394         err = uec_startup(uec);
1395         if (err) {
1396                 printf("%s: Cannot configure net device, aborting.",dev->name);
1397                 return err;
1398         }
1399
1400 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1401         int retval;
1402         struct mii_dev *mdiodev = mdio_alloc();
1403         if (!mdiodev)
1404                 return -ENOMEM;
1405         strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
1406         mdiodev->read = uec_miiphy_read;
1407         mdiodev->write = uec_miiphy_write;
1408
1409         retval = mdio_register(mdiodev);
1410         if (retval < 0)
1411                 return retval;
1412 #endif
1413
1414         return 1;
1415 }
1416
1417 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num)
1418 {
1419         int i;
1420
1421         for (i = 0; i < num; i++)
1422                 uec_initialize(bis, &uecs[i]);
1423
1424         return 0;
1425 }
1426
1427 int uec_standard_init(bd_t *bis)
1428 {
1429         return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
1430 }