drivers/power/regulator/pbias_regulator.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Texas Instruments Incorporated, <www.ti.com>
   4  * Jean-Jacques Hiblot <jjhiblot@ti.com>
   5  */
   6
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <power/pmic.h>
  14 #include <power/regulator.h>
  15 #include <regmap.h>
  16 #include <syscon.h>
  17 #include <linux/bitops.h>
  18 #include <linux/ioport.h>
  19 #include <dm/read.h>
  20 #ifdef CONFIG_MMC_OMAP36XX_PINS
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/mux.h>
  24 #endif
  25
  26 struct pbias_reg_info {
  27         u32 enable;
  28         u32 enable_mask;
  29         u32 disable_val;
  30         u32 vmode;
  31         unsigned int enable_time;
  32         char *name;
  33 };
  34
  35 struct pbias_priv {
  36         struct regmap *regmap;
  37         int offset;
  38 };
  39
  40 static const struct pmic_child_info pmic_children_info[] = {
  41         { .prefix = "pbias", .driver = "pbias_regulator"},
  42         { },
  43 };
  44
  45 static int pbias_write(struct udevice *dev, uint reg, const uint8_t *buff,
  46                        int len)
  47 {
  48         struct pbias_priv *priv = dev_get_priv(dev);
  49         u32 val = *(u32 *)buff;
  50
  51         if (len != 4)
  52                 return -EINVAL;
  53
  54         return regmap_write(priv->regmap, priv->offset, val);
  55 }
  56
  57 static int pbias_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
  58 {
  59         struct pbias_priv *priv = dev_get_priv(dev);
  60
  61         if (len != 4)
  62                 return -EINVAL;
  63
  64         return regmap_read(priv->regmap, priv->offset, (u32 *)buff);
  65 }
  66
  67 static int pbias_ofdata_to_platdata(struct udevice *dev)
  68 {
  69         struct pbias_priv *priv = dev_get_priv(dev);
  70         struct udevice *syscon;
  71         struct regmap *regmap;
  72         struct resource res;
  73         int err;
  74
  75         err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  76                                            "syscon", &syscon);
  77         if (err) {
  78                 pr_err("%s: unable to find syscon device (%d)\n", __func__,
  79                       err);
  80                 return err;
  81         }
  82
  83         regmap = syscon_get_regmap(syscon);
  84         if (IS_ERR(regmap)) {
  85                 pr_err("%s: unable to find regmap (%ld)\n", __func__,
  86                       PTR_ERR(regmap));
  87                 return PTR_ERR(regmap);
  88         }
  89         priv->regmap = regmap;
  90
  91         err = dev_read_resource(dev, 0, &res);
  92         if (err) {
  93                 pr_err("%s: unable to find offset (%d)\n", __func__, err);
  94                 return err;
  95         }
  96         priv->offset = res.start;
  97
  98         return 0;
  99 }
 100
 101 static int pbias_bind(struct udevice *dev)
 102 {
 103         int children;
 104
 105         children = pmic_bind_children(dev, dev->node, pmic_children_info);
 106         if (!children)
 107                 debug("%s: %s - no child found\n", __func__, dev->name);
 108
 109         return 0;
 110 }
 111
 112 static struct dm_pmic_ops pbias_ops = {
 113         .read = pbias_read,
 114         .write = pbias_write,
 115 };
 116
 117 static const struct udevice_id pbias_ids[] = {
 118         { .compatible = "ti,pbias-dra7" },
 119         { .compatible = "ti,pbias-omap2" },
 120         { .compatible = "ti,pbias-omap3" },
 121         { .compatible = "ti,pbias-omap4" },
 122         { .compatible = "ti,pbias-omap5" },
 123         { }
 124 };
 125
 126 U_BOOT_DRIVER(pbias_pmic) = {
 127         .name = "pbias_pmic",
 128         .id = UCLASS_PMIC,
 129         .of_match = pbias_ids,
 130         .bind = pbias_bind,
 131         .ops = &pbias_ops,
 132         .ofdata_to_platdata = pbias_ofdata_to_platdata,
 133         .priv_auto_alloc_size = sizeof(struct pbias_priv),
 134 };
 135
 136 static const struct pbias_reg_info pbias_mmc_omap2430 = {
 137         .enable = BIT(1),
 138         .enable_mask = BIT(1),
 139         .vmode = BIT(0),
 140         .disable_val = 0,
 141         .enable_time = 100,
 142         .name = "pbias_mmc_omap2430"
 143 };
 144
 145 static const struct pbias_reg_info pbias_sim_omap3 = {
 146         .enable = BIT(9),
 147         .enable_mask = BIT(9),
 148         .vmode = BIT(8),
 149         .enable_time = 100,
 150         .name = "pbias_sim_omap3"
 151 };
 152
 153 static const struct pbias_reg_info pbias_mmc_omap4 = {
 154         .enable = BIT(26) | BIT(22),
 155         .enable_mask = BIT(26) | BIT(25) | BIT(22),
 156         .disable_val = BIT(25),
 157         .vmode = BIT(21),
 158         .enable_time = 100,
 159         .name = "pbias_mmc_omap4"
 160 };
 161
 162 static const struct pbias_reg_info pbias_mmc_omap5 = {
 163         .enable = BIT(27) | BIT(26),
 164         .enable_mask = BIT(27) | BIT(25) | BIT(26),
 165         .disable_val = BIT(25),
 166         .vmode = BIT(21),
 167         .enable_time = 100,
 168         .name = "pbias_mmc_omap5"
 169 };
 170
 171 static const struct pbias_reg_info *pbias_reg_infos[] = {
 172         &pbias_mmc_omap5,
 173         &pbias_mmc_omap4,
 174         &pbias_sim_omap3,
 175         &pbias_mmc_omap2430,
 176         NULL
 177 };
 178
 179 static int pbias_regulator_probe(struct udevice *dev)
 180 {
 181         const struct pbias_reg_info **p = pbias_reg_infos;
 182         struct dm_regulator_uclass_platdata *uc_pdata;
 183
 184         uc_pdata = dev_get_uclass_platdata(dev);
 185
 186         while (*p) {
 187                 int rc;
 188
 189                 rc = dev_read_stringlist_search(dev, "regulator-name",
 190                                                 (*p)->name);
 191                 if (rc >= 0) {
 192                         debug("found regulator %s\n", (*p)->name);
 193                         break;
 194                 } else if (rc != -ENODATA) {
 195                         return rc;
 196                 }
 197                 p++;
 198         }
 199         if (!*p) {
 200                 int i = 0;
 201                 const char *s;
 202
 203                 debug("regulator ");
 204                 while (dev_read_string_index(dev, "regulator-name", i++, &s) >= 0)
 205                         debug("%s'%s' ", (i > 1) ? ", " : "", s);
 206                 debug("%s not supported\n", (i > 2) ? "are" : "is");
 207                 return -EINVAL;
 208         }
 209
 210         uc_pdata->type = REGULATOR_TYPE_OTHER;
 211         dev->priv = (void *)*p;
 212
 213         return 0;
 214 }
 215
 216 static int pbias_regulator_get_value(struct udevice *dev)
 217 {
 218         const struct pbias_reg_info *p = dev_get_priv(dev);
 219         int rc;
 220         u32 reg;
 221
 222         rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
 223         if (rc)
 224                 return rc;
 225
 226         debug("%s voltage id %s\n", p->name,
 227               (reg & p->vmode) ? "3.0v" : "1.8v");
 228         return (reg & p->vmode) ? 3000000 : 1800000;
 229 }
 230
 231 static int pbias_regulator_set_value(struct udevice *dev, int uV)
 232 {
 233         const struct pbias_reg_info *p = dev_get_priv(dev);
 234         int rc, ret;
 235         u32 reg;
 236 #ifdef CONFIG_MMC_OMAP36XX_PINS
 237         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 238 #endif
 239
 240         rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
 241         if (rc)
 242                 return rc;
 243
 244         if (uV == 3300000)
 245                 reg |= p->vmode;
 246         else if (uV == 1800000)
 247                 reg &= ~p->vmode;
 248         else
 249                 return -EINVAL;
 250
 251         debug("Setting %s voltage to %s\n", p->name,
 252               (reg & p->vmode) ? "3.0v" : "1.8v");
 253
 254 #ifdef CONFIG_MMC_OMAP36XX_PINS
 255         if (get_cpu_family() == CPU_OMAP36XX) {
 256                 /* Disable extended drain IO before changing PBIAS */
 257                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 258                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 259         }
 260 #endif
 261         ret = pmic_write(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
 262 #ifdef CONFIG_MMC_OMAP36XX_PINS
 263         if (get_cpu_family() == CPU_OMAP36XX) {
 264                 /* Enable extended drain IO after changing PBIAS */
 265                 writel(wkup_ctrl |
 266                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 267                                 OMAP34XX_CTRL_WKUP_CTRL);
 268         }
 269 #endif
 270         return ret;
 271 }
 272
 273 static int pbias_regulator_get_enable(struct udevice *dev)
 274 {
 275         const struct pbias_reg_info *p = dev_get_priv(dev);
 276         int rc;
 277         u32 reg;
 278
 279         rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
 280         if (rc)
 281                 return rc;
 282
 283         debug("%s id %s\n", p->name,
 284               (reg & p->enable_mask) == (p->disable_val) ? "on" : "off");
 285
 286         return (reg & p->enable_mask) == (p->disable_val);
 287 }
 288
 289 static int pbias_regulator_set_enable(struct udevice *dev, bool enable)
 290 {
 291         const struct pbias_reg_info *p = dev_get_priv(dev);
 292         int rc;
 293         u32 reg;
 294 #ifdef CONFIG_MMC_OMAP36XX_PINS
 295         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 296 #endif
 297
 298         debug("Turning %s %s\n", enable ? "on" : "off", p->name);
 299
 300 #ifdef CONFIG_MMC_OMAP36XX_PINS
 301         if (get_cpu_family() == CPU_OMAP36XX) {
 302                 /* Disable extended drain IO before changing PBIAS */
 303                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 304                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 305         }
 306 #endif
 307
 308         rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
 309         if (rc)
 310                 return rc;
 311
 312         reg &= ~p->enable_mask;
 313         if (enable)
 314                 reg |= p->enable;
 315         else
 316                 reg |= p->disable_val;
 317
 318         rc = pmic_write(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
 319
 320 #ifdef CONFIG_MMC_OMAP36XX_PINS
 321         if (get_cpu_family() == CPU_OMAP36XX) {
 322                 /* Enable extended drain IO after changing PBIAS */
 323                 writel(wkup_ctrl |
 324                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 325                                 OMAP34XX_CTRL_WKUP_CTRL);
 326         }
 327 #endif
 328
 329         if (rc)
 330                 return rc;
 331
 332         if (enable)
 333                 udelay(p->enable_time);
 334
 335         return 0;
 336 }
 337
 338 static const struct dm_regulator_ops pbias_regulator_ops = {
 339         .get_value  = pbias_regulator_get_value,
 340         .set_value  = pbias_regulator_set_value,
 341         .get_enable = pbias_regulator_get_enable,
 342         .set_enable = pbias_regulator_set_enable,
 343 };
 344
 345 U_BOOT_DRIVER(pbias_regulator) = {
 346         .name = "pbias_regulator",
 347         .id = UCLASS_REGULATOR,
 348         .ops = &pbias_regulator_ops,
 349         .probe = pbias_regulator_probe,
 350 };