drivers/power/domain/meson-ee-pwrc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2019 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <power-domain-uclass.h>
  12 #include <regmap.h>
  13 #include <syscon.h>
  14 #include <reset.h>
  15 #include <clk.h>
  16 #include <dt-bindings/power/meson-g12a-power.h>
  17 #include <dt-bindings/power/meson-sm1-power.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20
  21 /* AO Offsets */
  22
  23 #define AO_RTI_GEN_PWR_SLEEP0           (0x3a << 2)
  24 #define AO_RTI_GEN_PWR_ISO0             (0x3b << 2)
  25
  26 /* HHI Offsets */
  27
  28 #define HHI_MEM_PD_REG0                 (0x40 << 2)
  29 #define HHI_VPU_MEM_PD_REG0             (0x41 << 2)
  30 #define HHI_VPU_MEM_PD_REG1             (0x42 << 2)
  31 #define HHI_VPU_MEM_PD_REG3             (0x43 << 2)
  32 #define HHI_VPU_MEM_PD_REG4             (0x44 << 2)
  33 #define HHI_AUDIO_MEM_PD_REG0           (0x45 << 2)
  34 #define HHI_NANOQ_MEM_PD_REG0           (0x46 << 2)
  35 #define HHI_NANOQ_MEM_PD_REG1           (0x47 << 2)
  36 #define HHI_VPU_MEM_PD_REG2             (0x4d << 2)
  37
  38 struct meson_ee_pwrc;
  39 struct meson_ee_pwrc_domain;
  40
  41 struct meson_ee_pwrc_mem_domain {
  42         unsigned int reg;
  43         unsigned int mask;
  44 };
  45
  46 struct meson_ee_pwrc_top_domain {
  47         unsigned int sleep_reg;
  48         unsigned int sleep_mask;
  49         unsigned int iso_reg;
  50         unsigned int iso_mask;
  51 };
  52
  53 struct meson_ee_pwrc_domain_desc {
  54         char *name;
  55         unsigned int reset_names_count;
  56         unsigned int clk_names_count;
  57         struct meson_ee_pwrc_top_domain *top_pd;
  58         unsigned int mem_pd_count;
  59         struct meson_ee_pwrc_mem_domain *mem_pd;
  60         bool (*get_power)(struct power_domain *power_domain);
  61 };
  62
  63 struct meson_ee_pwrc_domain_data {
  64         unsigned int count;
  65         struct meson_ee_pwrc_domain_desc *domains;
  66 };
  67
  68 /* TOP Power Domains */
  69
  70 static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = {
  71         .sleep_reg = AO_RTI_GEN_PWR_SLEEP0,
  72         .sleep_mask = BIT(8),
  73         .iso_reg = AO_RTI_GEN_PWR_SLEEP0,
  74         .iso_mask = BIT(9),
  75 };
  76
  77 #define SM1_EE_PD(__bit)                                        \
  78         {                                                       \
  79                 .sleep_reg = AO_RTI_GEN_PWR_SLEEP0,             \
  80                 .sleep_mask = BIT(__bit),                       \
  81                 .iso_reg = AO_RTI_GEN_PWR_ISO0,                 \
  82                 .iso_mask = BIT(__bit),                         \
  83         }
  84
  85 static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
  86 static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
  87 static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
  88 static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
  89 static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
  90
  91 /* Memory PD Domains */
  92
  93 #define VPU_MEMPD(__reg)                                        \
  94         { __reg, GENMASK(1, 0) },                               \
  95         { __reg, GENMASK(3, 2) },                               \
  96         { __reg, GENMASK(5, 4) },                               \
  97         { __reg, GENMASK(7, 6) },                               \
  98         { __reg, GENMASK(9, 8) },                               \
  99         { __reg, GENMASK(11, 10) },                             \
 100         { __reg, GENMASK(13, 12) },                             \
 101         { __reg, GENMASK(15, 14) },                             \
 102         { __reg, GENMASK(17, 16) },                             \
 103         { __reg, GENMASK(19, 18) },                             \
 104         { __reg, GENMASK(21, 20) },                             \
 105         { __reg, GENMASK(23, 22) },                             \
 106         { __reg, GENMASK(25, 24) },                             \
 107         { __reg, GENMASK(27, 26) },                             \
 108         { __reg, GENMASK(29, 28) },                             \
 109         { __reg, GENMASK(31, 30) }
 110
 111 #define VPU_HHI_MEMPD(__reg)                                    \
 112         { __reg, BIT(8) },                                      \
 113         { __reg, BIT(9) },                                      \
 114         { __reg, BIT(10) },                                     \
 115         { __reg, BIT(11) },                                     \
 116         { __reg, BIT(12) },                                     \
 117         { __reg, BIT(13) },                                     \
 118         { __reg, BIT(14) },                                     \
 119         { __reg, BIT(15) }
 120
 121 static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
 122         VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
 123         VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
 124         VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
 125         VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
 126 };
 127
 128 static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = {
 129         { HHI_MEM_PD_REG0, GENMASK(3, 2) },
 130 };
 131
 132 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
 133         VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
 134         VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
 135         VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
 136         VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
 137         { HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
 138         { HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
 139         { HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
 140         { HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
 141         VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
 142 };
 143
 144 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
 145         { HHI_NANOQ_MEM_PD_REG0, 0xff },
 146         { HHI_NANOQ_MEM_PD_REG1, 0xff },
 147 };
 148
 149 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
 150         { HHI_MEM_PD_REG0, GENMASK(31, 30) },
 151 };
 152
 153 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
 154         { HHI_MEM_PD_REG0, GENMASK(29, 26) },
 155 };
 156
 157 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
 158         { HHI_MEM_PD_REG0, GENMASK(25, 18) },
 159 };
 160
 161 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
 162         { HHI_MEM_PD_REG0, GENMASK(5, 4) },
 163         { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
 164         { HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
 165         { HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
 166         { HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
 167         { HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
 168         { HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
 169         { HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
 170         { HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
 171         { HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
 172         { HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
 173         { HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
 174         { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
 175 };
 176
 177 #define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks)  \
 178         {                                                               \
 179                 .name = __name,                                         \
 180                 .reset_names_count = __resets,                          \
 181                 .clk_names_count = __clks,                              \
 182                 .top_pd = __top_pd,                                     \
 183                 .mem_pd_count = ARRAY_SIZE(__mem),                      \
 184                 .mem_pd = __mem,                                        \
 185                 .get_power = __get_power,                               \
 186         }
 187
 188 #define TOP_PD(__name, __top_pd, __mem, __get_power)                    \
 189         {                                                               \
 190                 .name = __name,                                         \
 191                 .top_pd = __top_pd,                                     \
 192                 .mem_pd_count = ARRAY_SIZE(__mem),                      \
 193                 .mem_pd = __mem,                                        \
 194                 .get_power = __get_power,                               \
 195         }
 196
 197 #define MEM_PD(__name, __mem)                                           \
 198         TOP_PD(__name, NULL, __mem, NULL)
 199
 200 static bool pwrc_ee_get_power(struct power_domain *power_domain);
 201
 202 static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
 203         [PWRC_G12A_VPU_ID]  = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu,
 204                                      pwrc_ee_get_power, 11, 2),
 205         [PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
 206 };
 207
 208 static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
 209         [PWRC_SM1_VPU_ID]  = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
 210                                     pwrc_ee_get_power, 11, 2),
 211         [PWRC_SM1_NNA_ID]  = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
 212                                     pwrc_ee_get_power),
 213         [PWRC_SM1_USB_ID]  = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
 214                                     pwrc_ee_get_power),
 215         [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
 216                                     pwrc_ee_get_power),
 217         [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
 218                                     pwrc_ee_get_power),
 219         [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
 220         [PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
 221 };
 222
 223 struct meson_ee_pwrc_priv {
 224         struct regmap *regmap_ao;
 225         struct regmap *regmap_hhi;
 226         struct reset_ctl_bulk resets;
 227         struct clk_bulk clks;
 228         const struct meson_ee_pwrc_domain_data *data;
 229 };
 230
 231 static bool pwrc_ee_get_power(struct power_domain *power_domain)
 232 {
 233         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 234         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 235         u32 reg;
 236
 237         pwrc_domain = &priv->data->domains[power_domain->id];
 238
 239         regmap_read(priv->regmap_ao,
 240                     pwrc_domain->top_pd->sleep_reg, &reg);
 241
 242         return (reg & pwrc_domain->top_pd->sleep_mask);
 243 }
 244
 245 static int meson_ee_pwrc_request(struct power_domain *power_domain)
 246 {
 247         return 0;
 248 }
 249
 250 static int meson_ee_pwrc_free(struct power_domain *power_domain)
 251 {
 252         return 0;
 253 }
 254
 255 static int meson_ee_pwrc_off(struct power_domain *power_domain)
 256 {
 257         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 258         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 259         int i;
 260
 261         pwrc_domain = &priv->data->domains[power_domain->id];
 262
 263         if (pwrc_domain->top_pd)
 264                 regmap_update_bits(priv->regmap_ao,
 265                                    pwrc_domain->top_pd->sleep_reg,
 266                                    pwrc_domain->top_pd->sleep_mask,
 267                                    pwrc_domain->top_pd->sleep_mask);
 268         udelay(20);
 269
 270         for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
 271                 regmap_update_bits(priv->regmap_hhi,
 272                                    pwrc_domain->mem_pd[i].reg,
 273                                    pwrc_domain->mem_pd[i].mask,
 274                                    pwrc_domain->mem_pd[i].mask);
 275
 276         udelay(20);
 277
 278         if (pwrc_domain->top_pd)
 279                 regmap_update_bits(priv->regmap_ao,
 280                                    pwrc_domain->top_pd->iso_reg,
 281                                    pwrc_domain->top_pd->iso_mask,
 282                                    pwrc_domain->top_pd->iso_mask);
 283
 284         if (pwrc_domain->clk_names_count) {
 285                 mdelay(20);
 286                 clk_disable_bulk(&priv->clks);
 287         }
 288
 289         return 0;
 290 }
 291
 292 static int meson_ee_pwrc_on(struct power_domain *power_domain)
 293 {
 294         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 295         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 296         int i, ret;
 297
 298         pwrc_domain = &priv->data->domains[power_domain->id];
 299
 300         if (pwrc_domain->top_pd)
 301                 regmap_update_bits(priv->regmap_ao,
 302                                    pwrc_domain->top_pd->sleep_reg,
 303                                    pwrc_domain->top_pd->sleep_mask, 0);
 304         udelay(20);
 305
 306         for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
 307                 regmap_update_bits(priv->regmap_hhi,
 308                                    pwrc_domain->mem_pd[i].reg,
 309                                    pwrc_domain->mem_pd[i].mask, 0);
 310
 311         udelay(20);
 312
 313         if (pwrc_domain->reset_names_count) {
 314                 ret = reset_assert_bulk(&priv->resets);
 315                 if (ret)
 316                         return ret;
 317         }
 318
 319         if (pwrc_domain->top_pd)
 320                 regmap_update_bits(priv->regmap_ao,
 321                                    pwrc_domain->top_pd->iso_reg,
 322                                    pwrc_domain->top_pd->iso_mask, 0);
 323
 324         if (pwrc_domain->reset_names_count) {
 325                 ret = reset_deassert_bulk(&priv->resets);
 326                 if (ret)
 327                         return ret;
 328         }
 329
 330         if (pwrc_domain->clk_names_count)
 331                 return clk_enable_bulk(&priv->clks);
 332
 333         return 0;
 334 }
 335
 336 static int meson_ee_pwrc_of_xlate(struct power_domain *power_domain,
 337                                   struct ofnode_phandle_args *args)
 338 {
 339         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 340
 341         /* #power-domain-cells is 1 */
 342
 343         if (args->args_count < 1) {
 344                 debug("Invalid args_count: %d\n", args->args_count);
 345                 return -EINVAL;
 346         }
 347
 348         power_domain->id = args->args[0];
 349
 350         if (power_domain->id >= priv->data->count) {
 351                 debug("Invalid domain ID: %lu\n", power_domain->id);
 352                 return -EINVAL;
 353         }
 354
 355         return 0;
 356 }
 357
 358 struct power_domain_ops meson_ee_pwrc_ops = {
 359         .rfree = meson_ee_pwrc_free,
 360         .off = meson_ee_pwrc_off,
 361         .on = meson_ee_pwrc_on,
 362         .request = meson_ee_pwrc_request,
 363         .of_xlate = meson_ee_pwrc_of_xlate,
 364 };
 365
 366 static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
 367         .count = ARRAY_SIZE(g12a_pwrc_domains),
 368         .domains = g12a_pwrc_domains,
 369 };
 370
 371 static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
 372         .count = ARRAY_SIZE(sm1_pwrc_domains),
 373         .domains = sm1_pwrc_domains,
 374 };
 375
 376 static const struct udevice_id meson_ee_pwrc_ids[] = {
 377         {
 378                 .compatible = "amlogic,meson-g12a-pwrc",
 379                 .data = (unsigned long)&meson_ee_g12a_pwrc_data,
 380         },
 381         {
 382                 .compatible = "amlogic,meson-sm1-pwrc",
 383                 .data = (unsigned long)&meson_ee_sm1_pwrc_data,
 384         },
 385         { }
 386 };
 387
 388 static int meson_ee_pwrc_probe(struct udevice *dev)
 389 {
 390         struct meson_ee_pwrc_priv *priv = dev_get_priv(dev);
 391         u32 ao_phandle;
 392         ofnode ao_node;
 393         int ret;
 394
 395         priv->data = (void *)dev_get_driver_data(dev);
 396         if (!priv->data)
 397                 return -EINVAL;
 398
 399         priv->regmap_hhi = syscon_node_to_regmap(dev_get_parent(dev)->node);
 400         if (IS_ERR(priv->regmap_hhi))
 401                 return PTR_ERR(priv->regmap_hhi);
 402
 403         ret = ofnode_read_u32(dev->node, "amlogic,ao-sysctrl",
 404                               &ao_phandle);
 405         if (ret)
 406                 return ret;
 407
 408         ao_node = ofnode_get_by_phandle(ao_phandle);
 409         if (!ofnode_valid(ao_node))
 410                 return -EINVAL;
 411
 412         priv->regmap_ao = syscon_node_to_regmap(ao_node);
 413         if (IS_ERR(priv->regmap_ao))
 414                 return PTR_ERR(priv->regmap_ao);
 415
 416         ret = reset_get_bulk(dev, &priv->resets);
 417         if (ret)
 418                 return ret;
 419
 420         ret = clk_get_bulk(dev, &priv->clks);
 421         if (ret)
 422                 return ret;
 423
 424         return 0;
 425 }
 426
 427 U_BOOT_DRIVER(meson_ee_pwrc) = {
 428         .name = "meson_ee_pwrc",
 429         .id = UCLASS_POWER_DOMAIN,
 430         .of_match = meson_ee_pwrc_ids,
 431         .probe = meson_ee_pwrc_probe,
 432         .ops = &meson_ee_pwrc_ops,
 433         .priv_auto_alloc_size = sizeof(struct meson_ee_pwrc_priv),
 434 };