drivers/power/domain/meson-ee-pwrc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2019 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <power-domain-uclass.h>
  12 #include <regmap.h>
  13 #include <syscon.h>
  14 #include <reset.h>
  15 #include <clk.h>
  16 #include <dt-bindings/power/meson-g12a-power.h>
  17 #include <dt-bindings/power/meson-sm1-power.h>
  18 #include <linux/err.h>
  19
  20 /* AO Offsets */
  21
  22 #define AO_RTI_GEN_PWR_SLEEP0           (0x3a << 2)
  23 #define AO_RTI_GEN_PWR_ISO0             (0x3b << 2)
  24
  25 /* HHI Offsets */
  26
  27 #define HHI_MEM_PD_REG0                 (0x40 << 2)
  28 #define HHI_VPU_MEM_PD_REG0             (0x41 << 2)
  29 #define HHI_VPU_MEM_PD_REG1             (0x42 << 2)
  30 #define HHI_VPU_MEM_PD_REG3             (0x43 << 2)
  31 #define HHI_VPU_MEM_PD_REG4             (0x44 << 2)
  32 #define HHI_AUDIO_MEM_PD_REG0           (0x45 << 2)
  33 #define HHI_NANOQ_MEM_PD_REG0           (0x46 << 2)
  34 #define HHI_NANOQ_MEM_PD_REG1           (0x47 << 2)
  35 #define HHI_VPU_MEM_PD_REG2             (0x4d << 2)
  36
  37 struct meson_ee_pwrc;
  38 struct meson_ee_pwrc_domain;
  39
  40 struct meson_ee_pwrc_mem_domain {
  41         unsigned int reg;
  42         unsigned int mask;
  43 };
  44
  45 struct meson_ee_pwrc_top_domain {
  46         unsigned int sleep_reg;
  47         unsigned int sleep_mask;
  48         unsigned int iso_reg;
  49         unsigned int iso_mask;
  50 };
  51
  52 struct meson_ee_pwrc_domain_desc {
  53         char *name;
  54         unsigned int reset_names_count;
  55         unsigned int clk_names_count;
  56         struct meson_ee_pwrc_top_domain *top_pd;
  57         unsigned int mem_pd_count;
  58         struct meson_ee_pwrc_mem_domain *mem_pd;
  59         bool (*get_power)(struct power_domain *power_domain);
  60 };
  61
  62 struct meson_ee_pwrc_domain_data {
  63         unsigned int count;
  64         struct meson_ee_pwrc_domain_desc *domains;
  65 };
  66
  67 /* TOP Power Domains */
  68
  69 static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = {
  70         .sleep_reg = AO_RTI_GEN_PWR_SLEEP0,
  71         .sleep_mask = BIT(8),
  72         .iso_reg = AO_RTI_GEN_PWR_SLEEP0,
  73         .iso_mask = BIT(9),
  74 };
  75
  76 #define SM1_EE_PD(__bit)                                        \
  77         {                                                       \
  78                 .sleep_reg = AO_RTI_GEN_PWR_SLEEP0,             \
  79                 .sleep_mask = BIT(__bit),                       \
  80                 .iso_reg = AO_RTI_GEN_PWR_ISO0,                 \
  81                 .iso_mask = BIT(__bit),                         \
  82         }
  83
  84 static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
  85 static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
  86 static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
  87 static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
  88 static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
  89
  90 /* Memory PD Domains */
  91
  92 #define VPU_MEMPD(__reg)                                        \
  93         { __reg, GENMASK(1, 0) },                               \
  94         { __reg, GENMASK(3, 2) },                               \
  95         { __reg, GENMASK(5, 4) },                               \
  96         { __reg, GENMASK(7, 6) },                               \
  97         { __reg, GENMASK(9, 8) },                               \
  98         { __reg, GENMASK(11, 10) },                             \
  99         { __reg, GENMASK(13, 12) },                             \
 100         { __reg, GENMASK(15, 14) },                             \
 101         { __reg, GENMASK(17, 16) },                             \
 102         { __reg, GENMASK(19, 18) },                             \
 103         { __reg, GENMASK(21, 20) },                             \
 104         { __reg, GENMASK(23, 22) },                             \
 105         { __reg, GENMASK(25, 24) },                             \
 106         { __reg, GENMASK(27, 26) },                             \
 107         { __reg, GENMASK(29, 28) },                             \
 108         { __reg, GENMASK(31, 30) }
 109
 110 #define VPU_HHI_MEMPD(__reg)                                    \
 111         { __reg, BIT(8) },                                      \
 112         { __reg, BIT(9) },                                      \
 113         { __reg, BIT(10) },                                     \
 114         { __reg, BIT(11) },                                     \
 115         { __reg, BIT(12) },                                     \
 116         { __reg, BIT(13) },                                     \
 117         { __reg, BIT(14) },                                     \
 118         { __reg, BIT(15) }
 119
 120 static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
 121         VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
 122         VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
 123         VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
 124         VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
 125 };
 126
 127 static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = {
 128         { HHI_MEM_PD_REG0, GENMASK(3, 2) },
 129 };
 130
 131 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
 132         VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
 133         VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
 134         VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
 135         VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
 136         { HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
 137         { HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
 138         { HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
 139         { HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
 140         VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
 141 };
 142
 143 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
 144         { HHI_NANOQ_MEM_PD_REG0, 0xff },
 145         { HHI_NANOQ_MEM_PD_REG1, 0xff },
 146 };
 147
 148 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
 149         { HHI_MEM_PD_REG0, GENMASK(31, 30) },
 150 };
 151
 152 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
 153         { HHI_MEM_PD_REG0, GENMASK(29, 26) },
 154 };
 155
 156 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
 157         { HHI_MEM_PD_REG0, GENMASK(25, 18) },
 158 };
 159
 160 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
 161         { HHI_MEM_PD_REG0, GENMASK(5, 4) },
 162         { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
 163         { HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
 164         { HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
 165         { HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
 166         { HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
 167         { HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
 168         { HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
 169         { HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
 170         { HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
 171         { HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
 172         { HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
 173         { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
 174 };
 175
 176 #define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks)  \
 177         {                                                               \
 178                 .name = __name,                                         \
 179                 .reset_names_count = __resets,                          \
 180                 .clk_names_count = __clks,                              \
 181                 .top_pd = __top_pd,                                     \
 182                 .mem_pd_count = ARRAY_SIZE(__mem),                      \
 183                 .mem_pd = __mem,                                        \
 184                 .get_power = __get_power,                               \
 185         }
 186
 187 #define TOP_PD(__name, __top_pd, __mem, __get_power)                    \
 188         {                                                               \
 189                 .name = __name,                                         \
 190                 .top_pd = __top_pd,                                     \
 191                 .mem_pd_count = ARRAY_SIZE(__mem),                      \
 192                 .mem_pd = __mem,                                        \
 193                 .get_power = __get_power,                               \
 194         }
 195
 196 #define MEM_PD(__name, __mem)                                           \
 197         TOP_PD(__name, NULL, __mem, NULL)
 198
 199 static bool pwrc_ee_get_power(struct power_domain *power_domain);
 200
 201 static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
 202         [PWRC_G12A_VPU_ID]  = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu,
 203                                      pwrc_ee_get_power, 11, 2),
 204         [PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
 205 };
 206
 207 static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
 208         [PWRC_SM1_VPU_ID]  = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
 209                                     pwrc_ee_get_power, 11, 2),
 210         [PWRC_SM1_NNA_ID]  = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
 211                                     pwrc_ee_get_power),
 212         [PWRC_SM1_USB_ID]  = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
 213                                     pwrc_ee_get_power),
 214         [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
 215                                     pwrc_ee_get_power),
 216         [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
 217                                     pwrc_ee_get_power),
 218         [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
 219         [PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
 220 };
 221
 222 struct meson_ee_pwrc_priv {
 223         struct regmap *regmap_ao;
 224         struct regmap *regmap_hhi;
 225         struct reset_ctl_bulk resets;
 226         struct clk_bulk clks;
 227         const struct meson_ee_pwrc_domain_data *data;
 228 };
 229
 230 static bool pwrc_ee_get_power(struct power_domain *power_domain)
 231 {
 232         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 233         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 234         u32 reg;
 235
 236         pwrc_domain = &priv->data->domains[power_domain->id];
 237
 238         regmap_read(priv->regmap_ao,
 239                     pwrc_domain->top_pd->sleep_reg, &reg);
 240
 241         return (reg & pwrc_domain->top_pd->sleep_mask);
 242 }
 243
 244 static int meson_ee_pwrc_request(struct power_domain *power_domain)
 245 {
 246         return 0;
 247 }
 248
 249 static int meson_ee_pwrc_free(struct power_domain *power_domain)
 250 {
 251         return 0;
 252 }
 253
 254 static int meson_ee_pwrc_off(struct power_domain *power_domain)
 255 {
 256         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 257         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 258         int i;
 259
 260         pwrc_domain = &priv->data->domains[power_domain->id];
 261
 262         if (pwrc_domain->top_pd)
 263                 regmap_update_bits(priv->regmap_ao,
 264                                    pwrc_domain->top_pd->sleep_reg,
 265                                    pwrc_domain->top_pd->sleep_mask,
 266                                    pwrc_domain->top_pd->sleep_mask);
 267         udelay(20);
 268
 269         for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
 270                 regmap_update_bits(priv->regmap_hhi,
 271                                    pwrc_domain->mem_pd[i].reg,
 272                                    pwrc_domain->mem_pd[i].mask,
 273                                    pwrc_domain->mem_pd[i].mask);
 274
 275         udelay(20);
 276
 277         if (pwrc_domain->top_pd)
 278                 regmap_update_bits(priv->regmap_ao,
 279                                    pwrc_domain->top_pd->iso_reg,
 280                                    pwrc_domain->top_pd->iso_mask,
 281                                    pwrc_domain->top_pd->iso_mask);
 282
 283         if (pwrc_domain->clk_names_count) {
 284                 mdelay(20);
 285                 clk_disable_bulk(&priv->clks);
 286         }
 287
 288         return 0;
 289 }
 290
 291 static int meson_ee_pwrc_on(struct power_domain *power_domain)
 292 {
 293         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 294         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 295         int i, ret;
 296
 297         pwrc_domain = &priv->data->domains[power_domain->id];
 298
 299         if (pwrc_domain->top_pd)
 300                 regmap_update_bits(priv->regmap_ao,
 301                                    pwrc_domain->top_pd->sleep_reg,
 302                                    pwrc_domain->top_pd->sleep_mask, 0);
 303         udelay(20);
 304
 305         for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
 306                 regmap_update_bits(priv->regmap_hhi,
 307                                    pwrc_domain->mem_pd[i].reg,
 308                                    pwrc_domain->mem_pd[i].mask, 0);
 309
 310         udelay(20);
 311
 312         if (pwrc_domain->reset_names_count) {
 313                 ret = reset_assert_bulk(&priv->resets);
 314                 if (ret)
 315                         return ret;
 316         }
 317
 318         if (pwrc_domain->top_pd)
 319                 regmap_update_bits(priv->regmap_ao,
 320                                    pwrc_domain->top_pd->iso_reg,
 321                                    pwrc_domain->top_pd->iso_mask, 0);
 322
 323         if (pwrc_domain->reset_names_count) {
 324                 ret = reset_deassert_bulk(&priv->resets);
 325                 if (ret)
 326                         return ret;
 327         }
 328
 329         if (pwrc_domain->clk_names_count)
 330                 return clk_enable_bulk(&priv->clks);
 331
 332         return 0;
 333 }
 334
 335 static int meson_ee_pwrc_of_xlate(struct power_domain *power_domain,
 336                                   struct ofnode_phandle_args *args)
 337 {
 338         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 339
 340         /* #power-domain-cells is 1 */
 341
 342         if (args->args_count < 1) {
 343                 debug("Invalid args_count: %d\n", args->args_count);
 344                 return -EINVAL;
 345         }
 346
 347         power_domain->id = args->args[0];
 348
 349         if (power_domain->id >= priv->data->count) {
 350                 debug("Invalid domain ID: %lu\n", power_domain->id);
 351                 return -EINVAL;
 352         }
 353
 354         return 0;
 355 }
 356
 357 struct power_domain_ops meson_ee_pwrc_ops = {
 358         .rfree = meson_ee_pwrc_free,
 359         .off = meson_ee_pwrc_off,
 360         .on = meson_ee_pwrc_on,
 361         .request = meson_ee_pwrc_request,
 362         .of_xlate = meson_ee_pwrc_of_xlate,
 363 };
 364
 365 static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
 366         .count = ARRAY_SIZE(g12a_pwrc_domains),
 367         .domains = g12a_pwrc_domains,
 368 };
 369
 370 static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
 371         .count = ARRAY_SIZE(sm1_pwrc_domains),
 372         .domains = sm1_pwrc_domains,
 373 };
 374
 375 static const struct udevice_id meson_ee_pwrc_ids[] = {
 376         {
 377                 .compatible = "amlogic,meson-g12a-pwrc",
 378                 .data = (unsigned long)&meson_ee_g12a_pwrc_data,
 379         },
 380         {
 381                 .compatible = "amlogic,meson-sm1-pwrc",
 382                 .data = (unsigned long)&meson_ee_sm1_pwrc_data,
 383         },
 384         { }
 385 };
 386
 387 static int meson_ee_pwrc_probe(struct udevice *dev)
 388 {
 389         struct meson_ee_pwrc_priv *priv = dev_get_priv(dev);
 390         u32 ao_phandle;
 391         ofnode ao_node;
 392         int ret;
 393
 394         priv->data = (void *)dev_get_driver_data(dev);
 395         if (!priv->data)
 396                 return -EINVAL;
 397
 398         priv->regmap_hhi = syscon_node_to_regmap(dev_get_parent(dev)->node);
 399         if (IS_ERR(priv->regmap_hhi))
 400                 return PTR_ERR(priv->regmap_hhi);
 401
 402         ret = ofnode_read_u32(dev->node, "amlogic,ao-sysctrl",
 403                               &ao_phandle);
 404         if (ret)
 405                 return ret;
 406
 407         ao_node = ofnode_get_by_phandle(ao_phandle);
 408         if (!ofnode_valid(ao_node))
 409                 return -EINVAL;
 410
 411         priv->regmap_ao = syscon_node_to_regmap(ao_node);
 412         if (IS_ERR(priv->regmap_ao))
 413                 return PTR_ERR(priv->regmap_ao);
 414
 415         ret = reset_get_bulk(dev, &priv->resets);
 416         if (ret)
 417                 return ret;
 418
 419         ret = clk_get_bulk(dev, &priv->clks);
 420         if (ret)
 421                 return ret;
 422
 423         return 0;
 424 }
 425
 426 U_BOOT_DRIVER(meson_ee_pwrc) = {
 427         .name = "meson_ee_pwrc",
 428         .id = UCLASS_POWER_DOMAIN,
 429         .of_match = meson_ee_pwrc_ids,
 430         .probe = meson_ee_pwrc_probe,
 431         .ops = &meson_ee_pwrc_ops,
 432         .priv_auto_alloc_size = sizeof(struct meson_ee_pwrc_priv),
 433 };