drivers/pinctrl/rockchip/pinctrl_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   4  * (C) 2018 Theobroma Systems Design und Consulting GmbH
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <syscon.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/grf_rk3399.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/periph.h>
  15 #include <asm/arch/clock.h>
  16 #include <dm/pinctrl.h>
  17
  18 #if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
  19 static const u32 RK_GRF_P_PULLUP = 1;
  20 static const u32 RK_GRF_P_PULLDOWN = 2;
  21 #endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
  22
  23 struct rk3399_pinctrl_priv {
  24         struct rk3399_grf_regs *grf;
  25         struct rk3399_pmugrf_regs *pmugrf;
  26         struct rockchip_pin_bank *banks;
  27 };
  28
  29 #if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
  30 /* Location of pinctrl/pinconf registers. */
  31 enum rk_grf_location {
  32         RK_GRF,
  33         RK_PMUGRF,
  34 };
  35
  36 /**
  37  * @nr_pins: number of pins in this bank
  38  * @grf_location: location of pinctrl/pinconf registers
  39  * @bank_num: number of the bank, to account for holes
  40  * @iomux: array describing the 4 iomux sources of the bank
  41  */
  42 struct rockchip_pin_bank {
  43         u8 nr_pins;
  44         enum rk_grf_location grf_location;
  45         size_t iomux_offset;
  46         size_t pupd_offset;
  47 };
  48
  49 #define PIN_BANK(pins, grf, iomux, pupd)                \
  50         {                                               \
  51                 .nr_pins = pins,                        \
  52                 .grf_location = grf,                    \
  53                 .iomux_offset = iomux,                  \
  54                 .pupd_offset = pupd,                    \
  55         }
  56
  57 static struct rockchip_pin_bank rk3399_pin_banks[] = {
  58         PIN_BANK(16, RK_PMUGRF,
  59                  offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux),
  60                  offsetof(struct rk3399_pmugrf_regs, gpio0_p)),
  61         PIN_BANK(32, RK_PMUGRF,
  62                  offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux),
  63                  offsetof(struct rk3399_pmugrf_regs, gpio1_p)),
  64         PIN_BANK(32, RK_GRF,
  65                  offsetof(struct rk3399_grf_regs, gpio2a_iomux),
  66                  offsetof(struct rk3399_grf_regs, gpio2_p)),
  67         PIN_BANK(32, RK_GRF,
  68                  offsetof(struct rk3399_grf_regs, gpio3a_iomux),
  69                  offsetof(struct rk3399_grf_regs, gpio3_p)),
  70         PIN_BANK(32, RK_GRF,
  71                  offsetof(struct rk3399_grf_regs, gpio4a_iomux),
  72                  offsetof(struct rk3399_grf_regs, gpio4_p)),
  73 };
  74
  75 static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr,
  76                                 u32 *shift, u32 *mask)
  77 {
  78         /*
  79          * In general we four subsequent 32-bit configuration registers
  80          * per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P).
  81          * The configuration for each pin has two bits.
  82          *
  83          * @base...contains the address to the first register.
  84          * @index...defines the pin within the bank (0..31).
  85          * @addr...will be the address of the actual register to use
  86          * @shift...will be the bit position in the configuration register
  87          * @mask...will be the (unshifted) mask
  88          */
  89
  90         const u32 pins_per_register = 8;
  91         const u32 config_bits_per_pin = 2;
  92
  93         /* Get the address of the configuration register. */
  94         *addr = base + (index / pins_per_register) * sizeof(u32);
  95
  96         /* Get the bit offset within the configuration register. */
  97         *shift = (index & (pins_per_register - 1)) * config_bits_per_pin;
  98
  99         /* Get the (unshifted) mask for the configuration pins. */
 100         *mask = ((1 << config_bits_per_pin) - 1);
 101
 102         pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n",
 103                  __func__, *addr, *mask, *shift);
 104 }
 105
 106 static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr,
 107                                          struct rockchip_pin_bank *bank,
 108                                          u32 index, u32 muxval)
 109 {
 110         uintptr_t iomux_base, addr;
 111         u32 shift, mask;
 112
 113         iomux_base = grf_addr + bank->iomux_offset;
 114         rk_pinctrl_get_info(iomux_base, index, &addr, &shift, &mask);
 115
 116         /* Set pinmux register */
 117         rk_clrsetreg(addr, mask << shift, muxval << shift);
 118 }
 119
 120 static void rk3399_pinctrl_set_pin_pupd(uintptr_t grf_addr,
 121                                         struct rockchip_pin_bank *bank,
 122                                         u32 index, int pinconfig)
 123 {
 124         uintptr_t pupd_base, addr;
 125         u32 shift, mask, pupdval;
 126
 127         /* Fast path in case there's nothing to do. */
 128         if (!pinconfig)
 129                 return;
 130
 131         if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_UP))
 132                 pupdval = RK_GRF_P_PULLUP;
 133         else if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
 134                 pupdval = RK_GRF_P_PULLDOWN;
 135         else
 136                 /* Flag not supported. */
 137                 pr_warn("%s: Unsupported pinconfig flag: 0x%x\n", __func__,
 138                         pinconfig);
 139                 return;
 140
 141         pupd_base = grf_addr + (uintptr_t)bank->pupd_offset;
 142         rk_pinctrl_get_info(pupd_base, index, &addr, &shift, &mask);
 143
 144         /* Set pull-up/pull-down regisrer */
 145         rk_clrsetreg(addr, mask << shift, pupdval << shift);
 146 }
 147
 148 static int rk3399_pinctrl_set_pin(struct udevice *dev, u32 banknum, u32 index,
 149                                   u32 muxval, int pinconfig)
 150 {
 151         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 152         struct rockchip_pin_bank *bank = &priv->banks[banknum];
 153         uintptr_t grf_addr;
 154
 155         pr_debug("%s: 0x%x 0x%x 0x%x 0x%x\n", __func__, banknum, index, muxval,
 156                  pinconfig);
 157
 158         if (bank->grf_location == RK_GRF)
 159                 grf_addr = (uintptr_t)priv->grf;
 160         else if (bank->grf_location == RK_PMUGRF)
 161                 grf_addr = (uintptr_t)priv->pmugrf;
 162         else
 163                 return -EINVAL;
 164
 165         rk3399_pinctrl_set_pin_iomux(grf_addr, bank, index, muxval);
 166
 167         rk3399_pinctrl_set_pin_pupd(grf_addr, bank, index, pinconfig);
 168         return 0;
 169 }
 170
 171 static int rk3399_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 172 {
 173         /*
 174          * The order of the fields in this struct must match the order of
 175          * the fields in the "rockchip,pins" property.
 176          */
 177         struct rk_pin {
 178                 u32 banknum;
 179                 u32 index;
 180                 u32 muxval;
 181                 u32 phandle;
 182         } __packed;
 183
 184         u32 *fields = NULL;
 185         const int fields_per_pin = 4;
 186         int num_fields, num_pins;
 187         int ret;
 188         int size;
 189         int i;
 190         struct rk_pin *pin;
 191
 192         pr_debug("%s: %s\n", __func__, config->name);
 193
 194         size = dev_read_size(config, "rockchip,pins");
 195         if (size < 0)
 196                 return -EINVAL;
 197
 198         num_fields = size / sizeof(u32);
 199         num_pins = num_fields / fields_per_pin;
 200
 201         if (num_fields * sizeof(u32) != size ||
 202             num_pins * fields_per_pin != num_fields) {
 203                 pr_warn("Invalid number of rockchip,pins fields.\n");
 204                 return -EINVAL;
 205         }
 206
 207         fields = calloc(num_fields, sizeof(u32));
 208         if (!fields)
 209                 return -ENOMEM;
 210
 211         ret = dev_read_u32_array(config, "rockchip,pins", fields, num_fields);
 212         if (ret) {
 213                 pr_warn("%s: Failed to read rockchip,pins fields.\n",
 214                         config->name);
 215                 goto end;
 216         }
 217
 218         pin = (struct rk_pin *)fields;
 219         for (i = 0; i < num_pins; i++, pin++) {
 220                 struct udevice *dev_pinconfig;
 221                 int pinconfig;
 222
 223                 ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG,
 224                                                       pin->phandle,
 225                                                       &dev_pinconfig);
 226                 if (ret) {
 227                         pr_debug("Could not get pinconfig device\n");
 228                         goto end;
 229                 }
 230
 231                 pinconfig = pinctrl_decode_pin_config_dm(dev_pinconfig);
 232                 if (pinconfig < 0) {
 233                         pr_warn("Could not parse pinconfig\n");
 234                         goto end;
 235                 }
 236
 237                 ret = rk3399_pinctrl_set_pin(dev, pin->banknum, pin->index,
 238                                              pin->muxval, pinconfig);
 239                 if (ret) {
 240                         pr_warn("Could not set pinctrl settings\n");
 241                         goto end;
 242                 }
 243         }
 244
 245 end:
 246         free(fields);
 247         return ret;
 248 }
 249
 250 #endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
 251
 252 static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
 253                 struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
 254 {
 255         switch (pwm_id) {
 256         case PERIPH_ID_PWM0:
 257                 rk_clrsetreg(&grf->gpio4c_iomux,
 258                              GRF_GPIO4C2_SEL_MASK,
 259                              GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
 260                 break;
 261         case PERIPH_ID_PWM1:
 262                 rk_clrsetreg(&grf->gpio4c_iomux,
 263                              GRF_GPIO4C6_SEL_MASK,
 264                              GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
 265                 break;
 266         case PERIPH_ID_PWM2:
 267                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
 268                              PMUGRF_GPIO1C3_SEL_MASK,
 269                              PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
 270                 break;
 271         case PERIPH_ID_PWM3:
 272                 if (readl(&pmugrf->soc_con0) & (1 << 5))
 273                         rk_clrsetreg(&pmugrf->gpio1b_iomux,
 274                                      PMUGRF_GPIO1B6_SEL_MASK,
 275                                      PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
 276                 else
 277                         rk_clrsetreg(&pmugrf->gpio0a_iomux,
 278                                      PMUGRF_GPIO0A6_SEL_MASK,
 279                                      PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
 280                 break;
 281         default:
 282                 debug("pwm id = %d iomux error!\n", pwm_id);
 283                 break;
 284         }
 285 }
 286
 287 static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
 288                                       struct rk3399_pmugrf_regs *pmugrf,
 289                                       int i2c_id)
 290 {
 291         switch (i2c_id) {
 292         case PERIPH_ID_I2C0:
 293                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 294                              PMUGRF_GPIO1B7_SEL_MASK,
 295                              PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
 296                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
 297                              PMUGRF_GPIO1C0_SEL_MASK,
 298                              PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
 299                 break;
 300
 301         case PERIPH_ID_I2C1:
 302                 rk_clrsetreg(&grf->gpio4a_iomux,
 303                              GRF_GPIO4A1_SEL_MASK,
 304                              GRF_I2C1_SDA << GRF_GPIO4A1_SEL_SHIFT);
 305                 rk_clrsetreg(&grf->gpio4a_iomux,
 306                              GRF_GPIO4A2_SEL_MASK,
 307                              GRF_I2C1_SCL << GRF_GPIO4A2_SEL_SHIFT);
 308                 break;
 309
 310         case PERIPH_ID_I2C2:
 311                 rk_clrsetreg(&grf->gpio2a_iomux,
 312                              GRF_GPIO2A0_SEL_MASK,
 313                              GRF_I2C2_SDA << GRF_GPIO2A0_SEL_SHIFT);
 314                 rk_clrsetreg(&grf->gpio2a_iomux,
 315                              GRF_GPIO2A1_SEL_MASK,
 316                              GRF_I2C2_SCL << GRF_GPIO2A1_SEL_SHIFT);
 317                 break;
 318         case PERIPH_ID_I2C3:
 319                 rk_clrsetreg(&grf->gpio4c_iomux,
 320                              GRF_GPIO4C0_SEL_MASK,
 321                              GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT);
 322                 rk_clrsetreg(&grf->gpio4c_iomux,
 323                              GRF_GPIO4C1_SEL_MASK,
 324                              GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT);
 325                 break;
 326
 327         case PERIPH_ID_I2C4:
 328                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 329                              PMUGRF_GPIO1B3_SEL_MASK,
 330                              PMUGRF_I2C4_SDA << PMUGRF_GPIO1B3_SEL_SHIFT);
 331                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 332                              PMUGRF_GPIO1B4_SEL_MASK,
 333                              PMUGRF_I2C4_SCL << PMUGRF_GPIO1B4_SEL_SHIFT);
 334                 break;
 335
 336         case PERIPH_ID_I2C7:
 337                 rk_clrsetreg(&grf->gpio2a_iomux,
 338                              GRF_GPIO2A7_SEL_MASK,
 339                              GRF_I2C7_SDA << GRF_GPIO2A7_SEL_SHIFT);
 340                 rk_clrsetreg(&grf->gpio2b_iomux,
 341                              GRF_GPIO2B0_SEL_MASK,
 342                              GRF_I2C7_SCL << GRF_GPIO2B0_SEL_SHIFT);
 343                 break;
 344
 345         case PERIPH_ID_I2C6:
 346                 rk_clrsetreg(&grf->gpio2b_iomux,
 347                              GRF_GPIO2B1_SEL_MASK,
 348                              GRF_I2C6_SDA << GRF_GPIO2B1_SEL_SHIFT);
 349                 rk_clrsetreg(&grf->gpio2b_iomux,
 350                              GRF_GPIO2B2_SEL_MASK,
 351                              GRF_I2C6_SDA << GRF_GPIO2B2_SEL_SHIFT);
 352                 break;
 353
 354         case PERIPH_ID_I2C8:
 355                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
 356                              PMUGRF_GPIO1C4_SEL_MASK,
 357                              PMUGRF_I2C8PMU_SDA << PMUGRF_GPIO1C4_SEL_SHIFT);
 358                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
 359                              PMUGRF_GPIO1C5_SEL_MASK,
 360                              PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT);
 361                 break;
 362
 363         case PERIPH_ID_I2C5:
 364         default:
 365                 debug("i2c id = %d iomux error!\n", i2c_id);
 366                 break;
 367         }
 368 }
 369
 370 static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
 371 {
 372         switch (lcd_id) {
 373         case PERIPH_ID_LCDC0:
 374                 break;
 375         default:
 376                 debug("lcdc id = %d iomux error!\n", lcd_id);
 377                 break;
 378         }
 379 }
 380
 381 static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
 382                                      struct rk3399_pmugrf_regs *pmugrf,
 383                                      enum periph_id spi_id, int cs)
 384 {
 385         switch (spi_id) {
 386         case PERIPH_ID_SPI0:
 387                 switch (cs) {
 388                 case 0:
 389                         rk_clrsetreg(&grf->gpio3a_iomux,
 390                                      GRF_GPIO3A7_SEL_MASK,
 391                                      GRF_SPI0NORCODEC_CSN0
 392                                      << GRF_GPIO3A7_SEL_SHIFT);
 393                         break;
 394                 case 1:
 395                         rk_clrsetreg(&grf->gpio3b_iomux,
 396                                      GRF_GPIO3B0_SEL_MASK,
 397                                      GRF_SPI0NORCODEC_CSN1
 398                                      << GRF_GPIO3B0_SEL_SHIFT);
 399                         break;
 400                 default:
 401                         goto err;
 402                 }
 403                 rk_clrsetreg(&grf->gpio3a_iomux,
 404                              GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
 405                              | GRF_GPIO3A6_SEL_SHIFT,
 406                              GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
 407                              | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
 408                              | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
 409                 break;
 410         case PERIPH_ID_SPI1:
 411                 if (cs != 0)
 412                         goto err;
 413                 rk_clrsetreg(&pmugrf->gpio1a_iomux,
 414                              PMUGRF_GPIO1A7_SEL_MASK,
 415                              PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
 416                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 417                              PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
 418                              | PMUGRF_GPIO1B2_SEL_MASK,
 419                              PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
 420                              | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
 421                              | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
 422                 break;
 423         case PERIPH_ID_SPI2:
 424                 if (cs != 0)
 425                         goto err;
 426                 rk_clrsetreg(&grf->gpio2b_iomux,
 427                              GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
 428                              | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
 429                              GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
 430                              | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
 431                              | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
 432                              | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
 433                 break;
 434         case PERIPH_ID_SPI5:
 435                 if (cs != 0)
 436                         goto err;
 437                 rk_clrsetreg(&grf->gpio2c_iomux,
 438                              GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
 439                              | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
 440                              GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
 441                              | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
 442                              | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
 443                              | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
 444                 break;
 445         default:
 446                 printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
 447                 goto err;
 448         }
 449
 450         return 0;
 451 err:
 452         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 453         return -ENOENT;
 454 }
 455
 456 static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
 457                                        struct rk3399_pmugrf_regs *pmugrf,
 458                                        int uart_id)
 459 {
 460         switch (uart_id) {
 461         case PERIPH_ID_UART2:
 462                 /* Using channel-C by default */
 463                 rk_clrsetreg(&grf->gpio4c_iomux,
 464                              GRF_GPIO4C3_SEL_MASK,
 465                              GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
 466                 rk_clrsetreg(&grf->gpio4c_iomux,
 467                              GRF_GPIO4C4_SEL_MASK,
 468                              GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
 469                 break;
 470         case PERIPH_ID_UART0:
 471         case PERIPH_ID_UART1:
 472         case PERIPH_ID_UART3:
 473         case PERIPH_ID_UART4:
 474         default:
 475                 debug("uart id = %d iomux error!\n", uart_id);
 476                 break;
 477         }
 478 }
 479
 480 static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
 481 {
 482         switch (mmc_id) {
 483         case PERIPH_ID_EMMC:
 484                 break;
 485         case PERIPH_ID_SDCARD:
 486                 rk_clrsetreg(&grf->gpio4b_iomux,
 487                              GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
 488                              | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
 489                              | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
 490                              GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
 491                              | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
 492                              | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
 493                              | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
 494                              | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
 495                              | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
 496                 break;
 497         default:
 498                 debug("mmc id = %d iomux error!\n", mmc_id);
 499                 break;
 500         }
 501 }
 502
 503 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 504 static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
 505 {
 506         rk_clrsetreg(&grf->gpio3a_iomux,
 507                      GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
 508                      GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
 509                      GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
 510                      GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
 511                      GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
 512                      GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
 513                      GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
 514                      GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
 515                      GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
 516                      GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
 517                      GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
 518                      GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
 519         rk_clrsetreg(&grf->gpio3b_iomux,
 520                      GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
 521                                             GRF_GPIO3B3_SEL_MASK |
 522                      GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
 523                      GRF_GPIO3B6_SEL_MASK,
 524                      GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
 525                      GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
 526                      GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
 527                      GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
 528                      GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
 529                      GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
 530         rk_clrsetreg(&grf->gpio3c_iomux,
 531                      GRF_GPIO3C1_SEL_MASK,
 532                      GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
 533
 534         /* Set drive strength for GMAC tx io, value 3 means 13mA */
 535         rk_clrsetreg(&grf->gpio3_e[0],
 536                      GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK |
 537                      GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK,
 538                      3 << GRF_GPIO3A0_E_SHIFT |
 539                      3 << GRF_GPIO3A1_E_SHIFT |
 540                      3 << GRF_GPIO3A4_E_SHIFT |
 541                      1 << GRF_GPIO3A5_E0_SHIFT);
 542         rk_clrsetreg(&grf->gpio3_e[1],
 543                      GRF_GPIO3A5_E12_MASK,
 544                      1 << GRF_GPIO3A5_E12_SHIFT);
 545         rk_clrsetreg(&grf->gpio3_e[2],
 546                      GRF_GPIO3B4_E_MASK,
 547                      3 << GRF_GPIO3B4_E_SHIFT);
 548         rk_clrsetreg(&grf->gpio3_e[4],
 549                      GRF_GPIO3C1_E_MASK,
 550                      3 << GRF_GPIO3C1_E_SHIFT);
 551 }
 552 #endif
 553
 554 #if !defined(CONFIG_SPL_BUILD)
 555 static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs *grf, int hdmi_id)
 556 {
 557         switch (hdmi_id) {
 558         case PERIPH_ID_HDMI:
 559                 rk_clrsetreg(&grf->gpio4c_iomux,
 560                              GRF_GPIO4C0_SEL_MASK | GRF_GPIO4C1_SEL_MASK,
 561                              (GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT) |
 562                              (GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT));
 563                 break;
 564         default:
 565                 debug("%s: hdmi_id = %d unsupported\n", __func__, hdmi_id);
 566                 break;
 567         }
 568 }
 569 #endif
 570
 571 static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
 572 {
 573         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 574
 575         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 576         switch (func) {
 577         case PERIPH_ID_PWM0:
 578         case PERIPH_ID_PWM1:
 579         case PERIPH_ID_PWM2:
 580         case PERIPH_ID_PWM3:
 581         case PERIPH_ID_PWM4:
 582                 pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
 583                 break;
 584         case PERIPH_ID_I2C0:
 585         case PERIPH_ID_I2C1:
 586         case PERIPH_ID_I2C2:
 587         case PERIPH_ID_I2C3:
 588         case PERIPH_ID_I2C4:
 589         case PERIPH_ID_I2C5:
 590         case PERIPH_ID_I2C6:
 591         case PERIPH_ID_I2C7:
 592         case PERIPH_ID_I2C8:
 593                 pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
 594                 break;
 595         case PERIPH_ID_SPI0:
 596         case PERIPH_ID_SPI1:
 597         case PERIPH_ID_SPI2:
 598         case PERIPH_ID_SPI3:
 599         case PERIPH_ID_SPI4:
 600         case PERIPH_ID_SPI5:
 601                 pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
 602                 break;
 603         case PERIPH_ID_UART0:
 604         case PERIPH_ID_UART1:
 605         case PERIPH_ID_UART2:
 606         case PERIPH_ID_UART3:
 607         case PERIPH_ID_UART4:
 608                 pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
 609                 break;
 610         case PERIPH_ID_LCDC0:
 611         case PERIPH_ID_LCDC1:
 612                 pinctrl_rk3399_lcdc_config(priv->grf, func);
 613                 break;
 614         case PERIPH_ID_SDMMC0:
 615         case PERIPH_ID_SDMMC1:
 616                 pinctrl_rk3399_sdmmc_config(priv->grf, func);
 617                 break;
 618 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 619         case PERIPH_ID_GMAC:
 620                 pinctrl_rk3399_gmac_config(priv->grf, func);
 621                 break;
 622 #endif
 623 #if !defined(CONFIG_SPL_BUILD)
 624         case PERIPH_ID_HDMI:
 625                 pinctrl_rk3399_hdmi_config(priv->grf, func);
 626                 break;
 627 #endif
 628         default:
 629                 return -EINVAL;
 630         }
 631
 632         return 0;
 633 }
 634
 635 static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
 636                                         struct udevice *periph)
 637 {
 638 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 639         u32 cell[3];
 640         int ret;
 641
 642         ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 643         if (ret < 0)
 644                 return -EINVAL;
 645
 646         switch (cell[1]) {
 647         case 68:
 648                 return PERIPH_ID_SPI0;
 649         case 53:
 650                 return PERIPH_ID_SPI1;
 651         case 52:
 652                 return PERIPH_ID_SPI2;
 653         case 132:
 654                 return PERIPH_ID_SPI5;
 655         case 57:
 656                 return PERIPH_ID_I2C0;
 657         case 59: /* Note strange order */
 658                 return PERIPH_ID_I2C1;
 659         case 35:
 660                 return PERIPH_ID_I2C2;
 661         case 34:
 662                 return PERIPH_ID_I2C3;
 663         case 56:
 664                 return PERIPH_ID_I2C4;
 665         case 38:
 666                 return PERIPH_ID_I2C5;
 667         case 37:
 668                 return PERIPH_ID_I2C6;
 669         case 36:
 670                 return PERIPH_ID_I2C7;
 671         case 58:
 672                 return PERIPH_ID_I2C8;
 673         case 65:
 674                 return PERIPH_ID_SDMMC1;
 675 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 676         case 12:
 677                 return PERIPH_ID_GMAC;
 678 #endif
 679 #if !defined(CONFIG_SPL_BUILD)
 680         case 23:
 681                 return PERIPH_ID_HDMI;
 682 #endif
 683         }
 684 #endif
 685         return -ENOENT;
 686 }
 687
 688 static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
 689                                            struct udevice *periph)
 690 {
 691         int func;
 692
 693         func = rk3399_pinctrl_get_periph_id(dev, periph);
 694         if (func < 0)
 695                 return func;
 696
 697         return rk3399_pinctrl_request(dev, func, 0);
 698 }
 699
 700 static struct pinctrl_ops rk3399_pinctrl_ops = {
 701 #if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
 702         .set_state      = rk3399_pinctrl_set_state,
 703 #endif
 704         .set_state_simple       = rk3399_pinctrl_set_state_simple,
 705         .request        = rk3399_pinctrl_request,
 706         .get_periph_id  = rk3399_pinctrl_get_periph_id,
 707 };
 708
 709 static int rk3399_pinctrl_probe(struct udevice *dev)
 710 {
 711         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 712         int ret = 0;
 713
 714         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 715         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 716         debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
 717 #if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
 718         priv->banks = rk3399_pin_banks;
 719 #endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
 720
 721         return ret;
 722 }
 723
 724 static const struct udevice_id rk3399_pinctrl_ids[] = {
 725         { .compatible = "rockchip,rk3399-pinctrl" },
 726         { }
 727 };
 728
 729 U_BOOT_DRIVER(pinctrl_rk3399) = {
 730         .name           = "rockchip_rk3399_pinctrl",
 731         .id             = UCLASS_PINCTRL,
 732         .of_match       = rk3399_pinctrl_ids,
 733         .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
 734         .ops            = &rk3399_pinctrl_ops,
 735 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 736         .bind           = dm_scan_fdt_dev,
 737 #endif
 738         .probe          = rk3399_pinctrl_probe,
 739 };