drivers/pinctrl/rockchip/pinctrl_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   4  * (C) 2018 Theobroma Systems Design und Consulting GmbH
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <syscon.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/grf_rk3399.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/periph.h>
  15 #include <asm/arch/clock.h>
  16 #include <dm/pinctrl.h>
  17
  18 static const u32 RK_GRF_P_PULLUP = 1;
  19 static const u32 RK_GRF_P_PULLDOWN = 2;
  20
  21 struct rk3399_pinctrl_priv {
  22         struct rk3399_grf_regs *grf;
  23         struct rk3399_pmugrf_regs *pmugrf;
  24         struct rockchip_pin_bank *banks;
  25 };
  26
  27 /* Location of pinctrl/pinconf registers. */
  28 enum rk_grf_location {
  29         RK_GRF,
  30         RK_PMUGRF,
  31 };
  32
  33 /**
  34  * @nr_pins: number of pins in this bank
  35  * @grf_location: location of pinctrl/pinconf registers
  36  * @bank_num: number of the bank, to account for holes
  37  * @iomux: array describing the 4 iomux sources of the bank
  38  */
  39 struct rockchip_pin_bank {
  40         u8 nr_pins;
  41         enum rk_grf_location grf_location;
  42         size_t iomux_offset;
  43         size_t pupd_offset;
  44 };
  45
  46 #define PIN_BANK(pins, grf, iomux, pupd)                \
  47         {                                               \
  48                 .nr_pins = pins,                        \
  49                 .grf_location = grf,                    \
  50                 .iomux_offset = iomux,                  \
  51                 .pupd_offset = pupd,                    \
  52         }
  53
  54 static struct rockchip_pin_bank rk3399_pin_banks[] = {
  55         PIN_BANK(16, RK_PMUGRF,
  56                  offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux),
  57                  offsetof(struct rk3399_pmugrf_regs, gpio0_p)),
  58         PIN_BANK(32, RK_PMUGRF,
  59                  offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux),
  60                  offsetof(struct rk3399_pmugrf_regs, gpio1_p)),
  61         PIN_BANK(32, RK_GRF,
  62                  offsetof(struct rk3399_grf_regs, gpio2a_iomux),
  63                  offsetof(struct rk3399_grf_regs, gpio2_p)),
  64         PIN_BANK(32, RK_GRF,
  65                  offsetof(struct rk3399_grf_regs, gpio3a_iomux),
  66                  offsetof(struct rk3399_grf_regs, gpio3_p)),
  67         PIN_BANK(32, RK_GRF,
  68                  offsetof(struct rk3399_grf_regs, gpio4a_iomux),
  69                  offsetof(struct rk3399_grf_regs, gpio4_p)),
  70 };
  71
  72 static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr,
  73                                 u32 *shift, u32 *mask)
  74 {
  75         /*
  76          * In general we four subsequent 32-bit configuration registers
  77          * per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P).
  78          * The configuration for each pin has two bits.
  79          *
  80          * @base...contains the address to the first register.
  81          * @index...defines the pin within the bank (0..31).
  82          * @addr...will be the address of the actual register to use
  83          * @shift...will be the bit position in the configuration register
  84          * @mask...will be the (unshifted) mask
  85          */
  86
  87         const u32 pins_per_register = 8;
  88         const u32 config_bits_per_pin = 2;
  89
  90         /* Get the address of the configuration register. */
  91         *addr = base + (index / pins_per_register) * sizeof(u32);
  92
  93         /* Get the bit offset within the configuration register. */
  94         *shift = (index & (pins_per_register - 1)) * config_bits_per_pin;
  95
  96         /* Get the (unshifted) mask for the configuration pins. */
  97         *mask = ((1 << config_bits_per_pin) - 1);
  98
  99         pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n",
 100                  __func__, *addr, *mask, *shift);
 101 }
 102
 103 static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr,
 104                                          struct rockchip_pin_bank *bank,
 105                                          u32 index, u32 muxval)
 106 {
 107         uintptr_t iomux_base, addr;
 108         u32 shift, mask;
 109
 110         iomux_base = grf_addr + bank->iomux_offset;
 111         rk_pinctrl_get_info(iomux_base, index, &addr, &shift, &mask);
 112
 113         /* Set pinmux register */
 114         rk_clrsetreg(addr, mask << shift, muxval << shift);
 115 }
 116
 117 static void rk3399_pinctrl_set_pin_pupd(uintptr_t grf_addr,
 118                                         struct rockchip_pin_bank *bank,
 119                                         u32 index, int pinconfig)
 120 {
 121         uintptr_t pupd_base, addr;
 122         u32 shift, mask, pupdval;
 123
 124         /* Fast path in case there's nothing to do. */
 125         if (!pinconfig)
 126                 return;
 127
 128         if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_UP))
 129                 pupdval = RK_GRF_P_PULLUP;
 130         else if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
 131                 pupdval = RK_GRF_P_PULLDOWN;
 132         else
 133                 /* Flag not supported. */
 134                 pr_warn("%s: Unsupported pinconfig flag: 0x%x\n", __func__,
 135                         pinconfig);
 136                 return;
 137
 138         pupd_base = grf_addr + (uintptr_t)bank->pupd_offset;
 139         rk_pinctrl_get_info(pupd_base, index, &addr, &shift, &mask);
 140
 141         /* Set pull-up/pull-down regisrer */
 142         rk_clrsetreg(addr, mask << shift, pupdval << shift);
 143 }
 144
 145 static int rk3399_pinctrl_set_pin(struct udevice *dev, u32 banknum, u32 index,
 146                                   u32 muxval, int pinconfig)
 147 {
 148         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 149         struct rockchip_pin_bank *bank = &priv->banks[banknum];
 150         uintptr_t grf_addr;
 151
 152         pr_debug("%s: 0x%x 0x%x 0x%x 0x%x\n", __func__, banknum, index, muxval,
 153                  pinconfig);
 154
 155         if (bank->grf_location == RK_GRF)
 156                 grf_addr = (uintptr_t)priv->grf;
 157         else if (bank->grf_location == RK_PMUGRF)
 158                 grf_addr = (uintptr_t)priv->pmugrf;
 159         else
 160                 return -EINVAL;
 161
 162         rk3399_pinctrl_set_pin_iomux(grf_addr, bank, index, muxval);
 163
 164         rk3399_pinctrl_set_pin_pupd(grf_addr, bank, index, pinconfig);
 165         return 0;
 166 }
 167
 168 static int rk3399_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 169 {
 170         /*
 171          * The order of the fields in this struct must match the order of
 172          * the fields in the "rockchip,pins" property.
 173          */
 174         struct rk_pin {
 175                 u32 banknum;
 176                 u32 index;
 177                 u32 muxval;
 178                 u32 phandle;
 179         } __packed;
 180
 181         u32 *fields = NULL;
 182         const int fields_per_pin = 4;
 183         int num_fields, num_pins;
 184         int ret;
 185         int size;
 186         int i;
 187         struct rk_pin *pin;
 188
 189         pr_debug("%s: %s\n", __func__, config->name);
 190
 191         size = dev_read_size(config, "rockchip,pins");
 192         if (size < 0)
 193                 return -EINVAL;
 194
 195         num_fields = size / sizeof(u32);
 196         num_pins = num_fields / fields_per_pin;
 197
 198         if (num_fields * sizeof(u32) != size ||
 199             num_pins * fields_per_pin != num_fields) {
 200                 pr_warn("Invalid number of rockchip,pins fields.\n");
 201                 return -EINVAL;
 202         }
 203
 204         fields = calloc(num_fields, sizeof(u32));
 205         if (!fields)
 206                 return -ENOMEM;
 207
 208         ret = dev_read_u32_array(config, "rockchip,pins", fields, num_fields);
 209         if (ret) {
 210                 pr_warn("%s: Failed to read rockchip,pins fields.\n",
 211                         config->name);
 212                 goto end;
 213         }
 214
 215         pin = (struct rk_pin *)fields;
 216         for (i = 0; i < num_pins; i++, pin++) {
 217                 struct udevice *dev_pinconfig;
 218                 int pinconfig;
 219
 220                 ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG,
 221                                                       pin->phandle,
 222                                                       &dev_pinconfig);
 223                 if (ret) {
 224                         pr_debug("Could not get pinconfig device\n");
 225                         goto end;
 226                 }
 227
 228                 pinconfig = pinctrl_decode_pin_config_dm(dev_pinconfig);
 229                 if (pinconfig < 0) {
 230                         pr_warn("Could not parse pinconfig\n");
 231                         goto end;
 232                 }
 233
 234                 ret = rk3399_pinctrl_set_pin(dev, pin->banknum, pin->index,
 235                                              pin->muxval, pinconfig);
 236                 if (ret) {
 237                         pr_warn("Could not set pinctrl settings\n");
 238                         goto end;
 239                 }
 240         }
 241
 242 end:
 243         free(fields);
 244         return ret;
 245 }
 246
 247 static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
 248                 struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
 249 {
 250         switch (pwm_id) {
 251         case PERIPH_ID_PWM0:
 252                 rk_clrsetreg(&grf->gpio4c_iomux,
 253                              GRF_GPIO4C2_SEL_MASK,
 254                              GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
 255                 break;
 256         case PERIPH_ID_PWM1:
 257                 rk_clrsetreg(&grf->gpio4c_iomux,
 258                              GRF_GPIO4C6_SEL_MASK,
 259                              GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
 260                 break;
 261         case PERIPH_ID_PWM2:
 262                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
 263                              PMUGRF_GPIO1C3_SEL_MASK,
 264                              PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
 265                 break;
 266         case PERIPH_ID_PWM3:
 267                 if (readl(&pmugrf->soc_con0) & (1 << 5))
 268                         rk_clrsetreg(&pmugrf->gpio1b_iomux,
 269                                      PMUGRF_GPIO1B6_SEL_MASK,
 270                                      PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
 271                 else
 272                         rk_clrsetreg(&pmugrf->gpio0a_iomux,
 273                                      PMUGRF_GPIO0A6_SEL_MASK,
 274                                      PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
 275                 break;
 276         default:
 277                 debug("pwm id = %d iomux error!\n", pwm_id);
 278                 break;
 279         }
 280 }
 281
 282 static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
 283                                       struct rk3399_pmugrf_regs *pmugrf,
 284                                       int i2c_id)
 285 {
 286         switch (i2c_id) {
 287         case PERIPH_ID_I2C0:
 288                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 289                              PMUGRF_GPIO1B7_SEL_MASK,
 290                              PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
 291                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
 292                              PMUGRF_GPIO1C0_SEL_MASK,
 293                              PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
 294                 break;
 295
 296         case PERIPH_ID_I2C1:
 297                 rk_clrsetreg(&grf->gpio4a_iomux,
 298                              GRF_GPIO4A1_SEL_MASK,
 299                              GRF_I2C1_SDA << GRF_GPIO4A1_SEL_SHIFT);
 300                 rk_clrsetreg(&grf->gpio4a_iomux,
 301                              GRF_GPIO4A2_SEL_MASK,
 302                              GRF_I2C1_SCL << GRF_GPIO4A2_SEL_SHIFT);
 303                 break;
 304
 305         case PERIPH_ID_I2C2:
 306                 rk_clrsetreg(&grf->gpio2a_iomux,
 307                              GRF_GPIO2A0_SEL_MASK,
 308                              GRF_I2C2_SDA << GRF_GPIO2A0_SEL_SHIFT);
 309                 rk_clrsetreg(&grf->gpio2a_iomux,
 310                              GRF_GPIO2A1_SEL_MASK,
 311                              GRF_I2C2_SCL << GRF_GPIO2A1_SEL_SHIFT);
 312                 break;
 313         case PERIPH_ID_I2C3:
 314                 rk_clrsetreg(&grf->gpio4c_iomux,
 315                              GRF_GPIO4C0_SEL_MASK,
 316                              GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT);
 317                 rk_clrsetreg(&grf->gpio4c_iomux,
 318                              GRF_GPIO4C1_SEL_MASK,
 319                              GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT);
 320                 break;
 321
 322         case PERIPH_ID_I2C4:
 323                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 324                              PMUGRF_GPIO1B3_SEL_MASK,
 325                              PMUGRF_I2C4_SDA << PMUGRF_GPIO1B3_SEL_SHIFT);
 326                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 327                              PMUGRF_GPIO1B4_SEL_MASK,
 328                              PMUGRF_I2C4_SCL << PMUGRF_GPIO1B4_SEL_SHIFT);
 329                 break;
 330
 331         case PERIPH_ID_I2C7:
 332                 rk_clrsetreg(&grf->gpio2a_iomux,
 333                              GRF_GPIO2A7_SEL_MASK,
 334                              GRF_I2C7_SDA << GRF_GPIO2A7_SEL_SHIFT);
 335                 rk_clrsetreg(&grf->gpio2b_iomux,
 336                              GRF_GPIO2B0_SEL_MASK,
 337                              GRF_I2C7_SCL << GRF_GPIO2B0_SEL_SHIFT);
 338                 break;
 339
 340         case PERIPH_ID_I2C6:
 341                 rk_clrsetreg(&grf->gpio2b_iomux,
 342                              GRF_GPIO2B1_SEL_MASK,
 343                              GRF_I2C6_SDA << GRF_GPIO2B1_SEL_SHIFT);
 344                 rk_clrsetreg(&grf->gpio2b_iomux,
 345                              GRF_GPIO2B2_SEL_MASK,
 346                              GRF_I2C6_SDA << GRF_GPIO2B2_SEL_SHIFT);
 347                 break;
 348
 349         case PERIPH_ID_I2C8:
 350                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
 351                              PMUGRF_GPIO1C4_SEL_MASK,
 352                              PMUGRF_I2C8PMU_SDA << PMUGRF_GPIO1C4_SEL_SHIFT);
 353                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
 354                              PMUGRF_GPIO1C5_SEL_MASK,
 355                              PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT);
 356                 break;
 357
 358         case PERIPH_ID_I2C5:
 359         default:
 360                 debug("i2c id = %d iomux error!\n", i2c_id);
 361                 break;
 362         }
 363 }
 364
 365 static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
 366 {
 367         switch (lcd_id) {
 368         case PERIPH_ID_LCDC0:
 369                 break;
 370         default:
 371                 debug("lcdc id = %d iomux error!\n", lcd_id);
 372                 break;
 373         }
 374 }
 375
 376 static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
 377                                      struct rk3399_pmugrf_regs *pmugrf,
 378                                      enum periph_id spi_id, int cs)
 379 {
 380         switch (spi_id) {
 381         case PERIPH_ID_SPI0:
 382                 switch (cs) {
 383                 case 0:
 384                         rk_clrsetreg(&grf->gpio3a_iomux,
 385                                      GRF_GPIO3A7_SEL_MASK,
 386                                      GRF_SPI0NORCODEC_CSN0
 387                                      << GRF_GPIO3A7_SEL_SHIFT);
 388                         break;
 389                 case 1:
 390                         rk_clrsetreg(&grf->gpio3b_iomux,
 391                                      GRF_GPIO3B0_SEL_MASK,
 392                                      GRF_SPI0NORCODEC_CSN1
 393                                      << GRF_GPIO3B0_SEL_SHIFT);
 394                         break;
 395                 default:
 396                         goto err;
 397                 }
 398                 rk_clrsetreg(&grf->gpio3a_iomux,
 399                              GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
 400                              | GRF_GPIO3A6_SEL_SHIFT,
 401                              GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
 402                              | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
 403                              | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
 404                 break;
 405         case PERIPH_ID_SPI1:
 406                 if (cs != 0)
 407                         goto err;
 408                 rk_clrsetreg(&pmugrf->gpio1a_iomux,
 409                              PMUGRF_GPIO1A7_SEL_MASK,
 410                              PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
 411                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 412                              PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
 413                              | PMUGRF_GPIO1B2_SEL_MASK,
 414                              PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
 415                              | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
 416                              | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
 417                 break;
 418         case PERIPH_ID_SPI2:
 419                 if (cs != 0)
 420                         goto err;
 421                 rk_clrsetreg(&grf->gpio2b_iomux,
 422                              GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
 423                              | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
 424                              GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
 425                              | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
 426                              | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
 427                              | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
 428                 break;
 429         case PERIPH_ID_SPI5:
 430                 if (cs != 0)
 431                         goto err;
 432                 rk_clrsetreg(&grf->gpio2c_iomux,
 433                              GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
 434                              | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
 435                              GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
 436                              | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
 437                              | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
 438                              | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
 439                 break;
 440         default:
 441                 printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
 442                 goto err;
 443         }
 444
 445         return 0;
 446 err:
 447         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 448         return -ENOENT;
 449 }
 450
 451 static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
 452                                        struct rk3399_pmugrf_regs *pmugrf,
 453                                        int uart_id)
 454 {
 455         switch (uart_id) {
 456         case PERIPH_ID_UART2:
 457                 /* Using channel-C by default */
 458                 rk_clrsetreg(&grf->gpio4c_iomux,
 459                              GRF_GPIO4C3_SEL_MASK,
 460                              GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
 461                 rk_clrsetreg(&grf->gpio4c_iomux,
 462                              GRF_GPIO4C4_SEL_MASK,
 463                              GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
 464                 break;
 465         case PERIPH_ID_UART0:
 466         case PERIPH_ID_UART1:
 467         case PERIPH_ID_UART3:
 468         case PERIPH_ID_UART4:
 469         default:
 470                 debug("uart id = %d iomux error!\n", uart_id);
 471                 break;
 472         }
 473 }
 474
 475 static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
 476 {
 477         switch (mmc_id) {
 478         case PERIPH_ID_EMMC:
 479                 break;
 480         case PERIPH_ID_SDCARD:
 481                 rk_clrsetreg(&grf->gpio4b_iomux,
 482                              GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
 483                              | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
 484                              | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
 485                              GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
 486                              | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
 487                              | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
 488                              | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
 489                              | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
 490                              | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
 491                 break;
 492         default:
 493                 debug("mmc id = %d iomux error!\n", mmc_id);
 494                 break;
 495         }
 496 }
 497
 498 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 499 static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
 500 {
 501         rk_clrsetreg(&grf->gpio3a_iomux,
 502                      GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
 503                      GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
 504                      GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
 505                      GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
 506                      GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
 507                      GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
 508                      GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
 509                      GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
 510                      GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
 511                      GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
 512                      GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
 513                      GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
 514         rk_clrsetreg(&grf->gpio3b_iomux,
 515                      GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
 516                                             GRF_GPIO3B3_SEL_MASK |
 517                      GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
 518                      GRF_GPIO3B6_SEL_MASK,
 519                      GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
 520                      GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
 521                      GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
 522                      GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
 523                      GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
 524                      GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
 525         rk_clrsetreg(&grf->gpio3c_iomux,
 526                      GRF_GPIO3C1_SEL_MASK,
 527                      GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
 528
 529         /* Set drive strength for GMAC tx io, value 3 means 13mA */
 530         rk_clrsetreg(&grf->gpio3_e[0],
 531                      GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK |
 532                      GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK,
 533                      3 << GRF_GPIO3A0_E_SHIFT |
 534                      3 << GRF_GPIO3A1_E_SHIFT |
 535                      3 << GRF_GPIO3A4_E_SHIFT |
 536                      1 << GRF_GPIO3A5_E0_SHIFT);
 537         rk_clrsetreg(&grf->gpio3_e[1],
 538                      GRF_GPIO3A5_E12_MASK,
 539                      1 << GRF_GPIO3A5_E12_SHIFT);
 540         rk_clrsetreg(&grf->gpio3_e[2],
 541                      GRF_GPIO3B4_E_MASK,
 542                      3 << GRF_GPIO3B4_E_SHIFT);
 543         rk_clrsetreg(&grf->gpio3_e[4],
 544                      GRF_GPIO3C1_E_MASK,
 545                      3 << GRF_GPIO3C1_E_SHIFT);
 546 }
 547 #endif
 548
 549 #if !defined(CONFIG_SPL_BUILD)
 550 static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs *grf, int hdmi_id)
 551 {
 552         switch (hdmi_id) {
 553         case PERIPH_ID_HDMI:
 554                 rk_clrsetreg(&grf->gpio4c_iomux,
 555                              GRF_GPIO4C0_SEL_MASK | GRF_GPIO4C1_SEL_MASK,
 556                              (GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT) |
 557                              (GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT));
 558                 break;
 559         default:
 560                 debug("%s: hdmi_id = %d unsupported\n", __func__, hdmi_id);
 561                 break;
 562         }
 563 }
 564 #endif
 565
 566 static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
 567 {
 568         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 569
 570         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 571         switch (func) {
 572         case PERIPH_ID_PWM0:
 573         case PERIPH_ID_PWM1:
 574         case PERIPH_ID_PWM2:
 575         case PERIPH_ID_PWM3:
 576         case PERIPH_ID_PWM4:
 577                 pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
 578                 break;
 579         case PERIPH_ID_I2C0:
 580         case PERIPH_ID_I2C1:
 581         case PERIPH_ID_I2C2:
 582         case PERIPH_ID_I2C3:
 583         case PERIPH_ID_I2C4:
 584         case PERIPH_ID_I2C5:
 585         case PERIPH_ID_I2C6:
 586         case PERIPH_ID_I2C7:
 587         case PERIPH_ID_I2C8:
 588                 pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
 589                 break;
 590         case PERIPH_ID_SPI0:
 591         case PERIPH_ID_SPI1:
 592         case PERIPH_ID_SPI2:
 593         case PERIPH_ID_SPI3:
 594         case PERIPH_ID_SPI4:
 595         case PERIPH_ID_SPI5:
 596                 pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
 597                 break;
 598         case PERIPH_ID_UART0:
 599         case PERIPH_ID_UART1:
 600         case PERIPH_ID_UART2:
 601         case PERIPH_ID_UART3:
 602         case PERIPH_ID_UART4:
 603                 pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
 604                 break;
 605         case PERIPH_ID_LCDC0:
 606         case PERIPH_ID_LCDC1:
 607                 pinctrl_rk3399_lcdc_config(priv->grf, func);
 608                 break;
 609         case PERIPH_ID_SDMMC0:
 610         case PERIPH_ID_SDMMC1:
 611                 pinctrl_rk3399_sdmmc_config(priv->grf, func);
 612                 break;
 613 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 614         case PERIPH_ID_GMAC:
 615                 pinctrl_rk3399_gmac_config(priv->grf, func);
 616                 break;
 617 #endif
 618 #if !defined(CONFIG_SPL_BUILD)
 619         case PERIPH_ID_HDMI:
 620                 pinctrl_rk3399_hdmi_config(priv->grf, func);
 621                 break;
 622 #endif
 623         default:
 624                 return -EINVAL;
 625         }
 626
 627         return 0;
 628 }
 629
 630 static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
 631                                         struct udevice *periph)
 632 {
 633 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 634         u32 cell[3];
 635         int ret;
 636
 637         ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 638         if (ret < 0)
 639                 return -EINVAL;
 640
 641         switch (cell[1]) {
 642         case 68:
 643                 return PERIPH_ID_SPI0;
 644         case 53:
 645                 return PERIPH_ID_SPI1;
 646         case 52:
 647                 return PERIPH_ID_SPI2;
 648         case 132:
 649                 return PERIPH_ID_SPI5;
 650         case 57:
 651                 return PERIPH_ID_I2C0;
 652         case 59: /* Note strange order */
 653                 return PERIPH_ID_I2C1;
 654         case 35:
 655                 return PERIPH_ID_I2C2;
 656         case 34:
 657                 return PERIPH_ID_I2C3;
 658         case 56:
 659                 return PERIPH_ID_I2C4;
 660         case 38:
 661                 return PERIPH_ID_I2C5;
 662         case 37:
 663                 return PERIPH_ID_I2C6;
 664         case 36:
 665                 return PERIPH_ID_I2C7;
 666         case 58:
 667                 return PERIPH_ID_I2C8;
 668         case 65:
 669                 return PERIPH_ID_SDMMC1;
 670 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 671         case 12:
 672                 return PERIPH_ID_GMAC;
 673 #endif
 674 #if !defined(CONFIG_SPL_BUILD)
 675         case 23:
 676                 return PERIPH_ID_HDMI;
 677 #endif
 678         }
 679 #endif
 680         return -ENOENT;
 681 }
 682
 683 static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
 684                                            struct udevice *periph)
 685 {
 686         int func;
 687
 688         func = rk3399_pinctrl_get_periph_id(dev, periph);
 689         if (func < 0)
 690                 return func;
 691
 692         return rk3399_pinctrl_request(dev, func, 0);
 693 }
 694
 695 static struct pinctrl_ops rk3399_pinctrl_ops = {
 696         .set_state      = rk3399_pinctrl_set_state,
 697         .set_state_simple       = rk3399_pinctrl_set_state_simple,
 698         .request        = rk3399_pinctrl_request,
 699         .get_periph_id  = rk3399_pinctrl_get_periph_id,
 700 };
 701
 702 static int rk3399_pinctrl_probe(struct udevice *dev)
 703 {
 704         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 705         int ret = 0;
 706
 707         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 708         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 709         debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
 710         priv->banks = rk3399_pin_banks;
 711
 712         return ret;
 713 }
 714
 715 static const struct udevice_id rk3399_pinctrl_ids[] = {
 716         { .compatible = "rockchip,rk3399-pinctrl" },
 717         { }
 718 };
 719
 720 U_BOOT_DRIVER(pinctrl_rk3399) = {
 721         .name           = "rockchip_rk3399_pinctrl",
 722         .id             = UCLASS_PINCTRL,
 723         .of_match       = rk3399_pinctrl_ids,
 724         .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
 725         .ops            = &rk3399_pinctrl_ops,
 726 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 727         .bind           = dm_scan_fdt_dev,
 728 #endif
 729         .probe          = rk3399_pinctrl_probe,
 730 };