drivers/pinctrl/renesas/pfc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pin Control driver for SuperH Pin Function Controller.
   4  *
   5  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   6  *
   7  * Copyright (C) 2008 Magnus Damm
   8  * Copyright (C) 2009 - 2012 Paul Mundt
   9  * Copyright (C) 2017 Marek Vasut
  10  */
  11
  12 #define DRV_NAME "sh-pfc"
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <dm/device_compat.h>
  18 #include <dm/devres.h>
  19 #include <dm/pinctrl.h>
  20 #include <linux/bitops.h>
  21 #include <linux/bug.h>
  22 #include <linux/io.h>
  23 #include <linux/sizes.h>
  24
  25 #include "sh_pfc.h"
  26
  27 enum sh_pfc_model {
  28         SH_PFC_R8A7790 = 0,
  29         SH_PFC_R8A7791,
  30         SH_PFC_R8A7792,
  31         SH_PFC_R8A7793,
  32         SH_PFC_R8A7794,
  33         SH_PFC_R8A7795,
  34         SH_PFC_R8A7796,
  35         SH_PFC_R8A77965,
  36         SH_PFC_R8A77970,
  37         SH_PFC_R8A77980,
  38         SH_PFC_R8A77990,
  39         SH_PFC_R8A77995,
  40 };
  41
  42 struct sh_pfc_pin_config {
  43         u32 type;
  44 };
  45
  46 struct sh_pfc_pinctrl {
  47         struct sh_pfc *pfc;
  48
  49         struct sh_pfc_pin_config *configs;
  50
  51         const char *func_prop_name;
  52         const char *groups_prop_name;
  53         const char *pins_prop_name;
  54 };
  55
  56 struct sh_pfc_pin_range {
  57         u16 start;
  58         u16 end;
  59 };
  60
  61 struct sh_pfc_pinctrl_priv {
  62         struct sh_pfc                   pfc;
  63         struct sh_pfc_pinctrl           pmx;
  64 };
  65
  66 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  67 {
  68         unsigned int offset;
  69         unsigned int i;
  70
  71         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  72                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  73
  74                 if (pin <= range->end)
  75                         return pin >= range->start
  76                              ? offset + pin - range->start : -1;
  77
  78                 offset += range->end - range->start + 1;
  79         }
  80
  81         return -EINVAL;
  82 }
  83
  84 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  85 {
  86         if (enum_id < r->begin)
  87                 return 0;
  88
  89         if (enum_id > r->end)
  90                 return 0;
  91
  92         return 1;
  93 }
  94
  95 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  96 {
  97         switch (reg_width) {
  98         case 8:
  99                 return readb(mapped_reg);
 100         case 16:
 101                 return readw(mapped_reg);
 102         case 32:
 103                 return readl(mapped_reg);
 104         }
 105
 106         BUG();
 107         return 0;
 108 }
 109
 110 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 111                           u32 data)
 112 {
 113         switch (reg_width) {
 114         case 8:
 115                 writeb(data, mapped_reg);
 116                 return;
 117         case 16:
 118                 writew(data, mapped_reg);
 119                 return;
 120         case 32:
 121                 writel(data, mapped_reg);
 122                 return;
 123         }
 124
 125         BUG();
 126 }
 127
 128 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
 129 {
 130         return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
 131 }
 132
 133 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
 134 {
 135         void __iomem *unlock_reg =
 136                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 137
 138         if (pfc->info->unlock_reg)
 139                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 140
 141         sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
 142 }
 143
 144 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 145                                      const struct pinmux_cfg_reg *crp,
 146                                      unsigned int in_pos,
 147                                      void __iomem **mapped_regp, u32 *maskp,
 148                                      unsigned int *posp)
 149 {
 150         unsigned int k;
 151
 152         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
 153
 154         if (crp->field_width) {
 155                 *maskp = (1 << crp->field_width) - 1;
 156                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 157         } else {
 158                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 159                 *posp = crp->reg_width;
 160                 for (k = 0; k <= in_pos; k++)
 161                         *posp -= crp->var_field_width[k];
 162         }
 163 }
 164
 165 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 166                                     const struct pinmux_cfg_reg *crp,
 167                                     unsigned int field, u32 value)
 168 {
 169         void __iomem *mapped_reg;
 170         void __iomem *unlock_reg =
 171                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 172         unsigned int pos;
 173         u32 mask, data;
 174
 175         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 176
 177         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 178                 "r_width = %u, f_width = %u\n",
 179                 crp->reg, value, field, crp->reg_width, crp->field_width);
 180
 181         mask = ~(mask << pos);
 182         value = value << pos;
 183
 184         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 185         data &= mask;
 186         data |= value;
 187
 188         if (pfc->info->unlock_reg)
 189                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 190
 191         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 192 }
 193
 194 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 195                                  const struct pinmux_cfg_reg **crp,
 196                                  unsigned int *fieldp, u32 *valuep)
 197 {
 198         unsigned int k = 0;
 199
 200         while (1) {
 201                 const struct pinmux_cfg_reg *config_reg =
 202                         pfc->info->cfg_regs + k;
 203                 unsigned int r_width = config_reg->reg_width;
 204                 unsigned int f_width = config_reg->field_width;
 205                 unsigned int curr_width;
 206                 unsigned int bit_pos;
 207                 unsigned int pos = 0;
 208                 unsigned int m = 0;
 209
 210                 if (!r_width)
 211                         break;
 212
 213                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 214                         u32 ncomb;
 215                         u32 n;
 216
 217                         if (f_width)
 218                                 curr_width = f_width;
 219                         else
 220                                 curr_width = config_reg->var_field_width[m];
 221
 222                         ncomb = 1 << curr_width;
 223                         for (n = 0; n < ncomb; n++) {
 224                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 225                                         *crp = config_reg;
 226                                         *fieldp = m;
 227                                         *valuep = n;
 228                                         return 0;
 229                                 }
 230                         }
 231                         pos += ncomb;
 232                         m++;
 233                 }
 234                 k++;
 235         }
 236
 237         return -EINVAL;
 238 }
 239
 240 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 241                               u16 *enum_idp)
 242 {
 243         const u16 *data = pfc->info->pinmux_data;
 244         unsigned int k;
 245
 246         if (pos) {
 247                 *enum_idp = data[pos + 1];
 248                 return pos + 1;
 249         }
 250
 251         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 252                 if (data[k] == mark) {
 253                         *enum_idp = data[k + 1];
 254                         return k + 1;
 255                 }
 256         }
 257
 258         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 259                 mark);
 260         return -EINVAL;
 261 }
 262
 263 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 264 {
 265         const struct pinmux_range *range;
 266         int pos = 0;
 267
 268         switch (pinmux_type) {
 269         case PINMUX_TYPE_GPIO:
 270         case PINMUX_TYPE_FUNCTION:
 271                 range = NULL;
 272                 break;
 273
 274         case PINMUX_TYPE_OUTPUT:
 275                 range = &pfc->info->output;
 276                 break;
 277
 278         case PINMUX_TYPE_INPUT:
 279                 range = &pfc->info->input;
 280                 break;
 281
 282         default:
 283                 return -EINVAL;
 284         }
 285
 286         /* Iterate over all the configuration fields we need to update. */
 287         while (1) {
 288                 const struct pinmux_cfg_reg *cr;
 289                 unsigned int field;
 290                 u16 enum_id;
 291                 u32 value;
 292                 int in_range;
 293                 int ret;
 294
 295                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 296                 if (pos < 0)
 297                         return pos;
 298
 299                 if (!enum_id)
 300                         break;
 301
 302                 /* Check if the configuration field selects a function. If it
 303                  * doesn't, skip the field if it's not applicable to the
 304                  * requested pinmux type.
 305                  */
 306                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 307                 if (!in_range) {
 308                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 309                                 /* Functions are allowed to modify all
 310                                  * fields.
 311                                  */
 312                                 in_range = 1;
 313                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 314                                 /* Input/output types can only modify fields
 315                                  * that correspond to their respective ranges.
 316                                  */
 317                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 318
 319                                 /*
 320                                  * special case pass through for fixed
 321                                  * input-only or output-only pins without
 322                                  * function enum register association.
 323                                  */
 324                                 if (in_range && enum_id == range->force)
 325                                         continue;
 326                         }
 327                         /* GPIOs are only allowed to modify function fields. */
 328                 }
 329
 330                 if (!in_range)
 331                         continue;
 332
 333                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 334                 if (ret < 0)
 335                         return ret;
 336
 337                 sh_pfc_write_config_reg(pfc, cr, field, value);
 338         }
 339
 340         return 0;
 341 }
 342
 343 const struct pinmux_bias_reg *
 344 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
 345                        unsigned int *bit)
 346 {
 347         unsigned int i, j;
 348
 349         for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 350                 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
 351                         if (pfc->info->bias_regs[i].pins[j] == pin) {
 352                                 *bit = j;
 353                                 return &pfc->info->bias_regs[i];
 354                         }
 355                 }
 356         }
 357
 358         WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
 359
 360         return NULL;
 361 }
 362
 363 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 364 {
 365         struct sh_pfc_pin_range *range;
 366         unsigned int nr_ranges;
 367         unsigned int i;
 368
 369         if (pfc->info->pins[0].pin == (u16)-1) {
 370                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 371                  * in its pin arrays yet. Consider the pin numbers range as
 372                  * continuous and allocate a single range.
 373                  */
 374                 pfc->nr_ranges = 1;
 375                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
 376                 if (pfc->ranges == NULL)
 377                         return -ENOMEM;
 378
 379                 pfc->ranges->start = 0;
 380                 pfc->ranges->end = pfc->info->nr_pins - 1;
 381                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 382
 383                 return 0;
 384         }
 385
 386         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 387          * be sorted by pin numbers, and pins without a GPIO port must come
 388          * last.
 389          */
 390         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 391                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 392                         nr_ranges++;
 393         }
 394
 395         pfc->nr_ranges = nr_ranges;
 396         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
 397         if (pfc->ranges == NULL)
 398                 return -ENOMEM;
 399
 400         range = pfc->ranges;
 401         range->start = pfc->info->pins[0].pin;
 402
 403         for (i = 1; i < pfc->info->nr_pins; ++i) {
 404                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 405                         continue;
 406
 407                 range->end = pfc->info->pins[i-1].pin;
 408                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 409                         pfc->nr_gpio_pins = range->end + 1;
 410
 411                 range++;
 412                 range->start = pfc->info->pins[i].pin;
 413         }
 414
 415         range->end = pfc->info->pins[i-1].pin;
 416         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 417                 pfc->nr_gpio_pins = range->end + 1;
 418
 419         return 0;
 420 }
 421
 422 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
 423 {
 424         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 425
 426         return priv->pfc.info->nr_pins;
 427 }
 428
 429 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
 430                                                   unsigned selector)
 431 {
 432         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 433
 434         return priv->pfc.info->pins[selector].name;
 435 }
 436
 437 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
 438 {
 439         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 440
 441         return priv->pfc.info->nr_groups;
 442 }
 443
 444 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
 445                                                   unsigned selector)
 446 {
 447         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 448
 449         return priv->pfc.info->groups[selector].name;
 450 }
 451
 452 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
 453 {
 454         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 455
 456         return priv->pfc.info->nr_functions;
 457 }
 458
 459 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
 460                                                   unsigned selector)
 461 {
 462         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 463
 464         return priv->pfc.info->functions[selector].name;
 465 }
 466
 467 static int sh_pfc_gpio_request_enable(struct udevice *dev,
 468                                       unsigned pin_selector)
 469 {
 470         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 471         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 472         struct sh_pfc *pfc = &priv->pfc;
 473         struct sh_pfc_pin_config *cfg;
 474         const struct sh_pfc_pin *pin = NULL;
 475         int i, ret, idx;
 476
 477         for (i = 0; i < pfc->info->nr_pins; i++) {
 478                 if (priv->pfc.info->pins[i].pin != pin_selector)
 479                         continue;
 480
 481                 pin = &priv->pfc.info->pins[i];
 482                 break;
 483         }
 484
 485         if (!pin)
 486                 return -EINVAL;
 487
 488         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 489         cfg = &pmx->configs[idx];
 490
 491         if (cfg->type != PINMUX_TYPE_NONE)
 492                 return -EBUSY;
 493
 494         ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
 495         if (ret)
 496                 return ret;
 497
 498         cfg->type = PINMUX_TYPE_GPIO;
 499
 500         return 0;
 501 }
 502
 503 static int sh_pfc_gpio_disable_free(struct udevice *dev,
 504                                     unsigned pin_selector)
 505 {
 506         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 507         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 508         struct sh_pfc *pfc = &priv->pfc;
 509         struct sh_pfc_pin_config *cfg;
 510         const struct sh_pfc_pin *pin = NULL;
 511         int i, idx;
 512
 513         for (i = 0; i < pfc->info->nr_pins; i++) {
 514                 if (priv->pfc.info->pins[i].pin != pin_selector)
 515                         continue;
 516
 517                 pin = &priv->pfc.info->pins[i];
 518                 break;
 519         }
 520
 521         if (!pin)
 522                 return -EINVAL;
 523
 524         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 525         cfg = &pmx->configs[idx];
 526
 527         cfg->type = PINMUX_TYPE_NONE;
 528
 529         return 0;
 530 }
 531
 532 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
 533                                   unsigned func_selector)
 534 {
 535         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 536         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 537         struct sh_pfc *pfc = &priv->pfc;
 538         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
 539         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
 540         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 541
 542         if (cfg->type != PINMUX_TYPE_NONE)
 543                 return -EBUSY;
 544
 545         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
 546 }
 547
 548 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
 549                                      unsigned func_selector)
 550 {
 551         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 552         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 553         struct sh_pfc *pfc = &priv->pfc;
 554         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
 555         unsigned int i;
 556         int ret = 0;
 557
 558         for (i = 0; i < grp->nr_pins; ++i) {
 559                 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
 560                 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 561
 562                 if (cfg->type != PINMUX_TYPE_NONE) {
 563                         ret = -EBUSY;
 564                         goto done;
 565                 }
 566         }
 567
 568         for (i = 0; i < grp->nr_pins; ++i) {
 569                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
 570                 if (ret < 0)
 571                         break;
 572         }
 573
 574 done:
 575         return ret;
 576 }
 577 #if CONFIG_IS_ENABLED(PINCONF)
 578 static const struct pinconf_param sh_pfc_pinconf_params[] = {
 579         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
 580         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
 581         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
 582         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
 583         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
 584 };
 585
 586 static void __iomem *
 587 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
 588                                        unsigned int *offset, unsigned int *size)
 589 {
 590         const struct pinmux_drive_reg_field *field;
 591         const struct pinmux_drive_reg *reg;
 592         unsigned int i;
 593
 594         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
 595                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
 596                         field = &reg->fields[i];
 597
 598                         if (field->size && field->pin == pin) {
 599                                 *offset = field->offset;
 600                                 *size = field->size;
 601
 602                                 return (void __iomem *)(uintptr_t)reg->reg;
 603                         }
 604                 }
 605         }
 606
 607         return NULL;
 608 }
 609
 610 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 611                                              unsigned int pin, u16 strength)
 612 {
 613         unsigned int offset;
 614         unsigned int size;
 615         unsigned int step;
 616         void __iomem *reg;
 617         void __iomem *unlock_reg =
 618                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 619         u32 val;
 620
 621         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
 622         if (!reg)
 623                 return -EINVAL;
 624
 625         step = size == 2 ? 6 : 3;
 626
 627         if (strength < step || strength > 24)
 628                 return -EINVAL;
 629
 630         /* Convert the value from mA based on a full drive strength value of
 631          * 24mA. We can make the full value configurable later if needed.
 632          */
 633         strength = strength / step - 1;
 634
 635         val = sh_pfc_read_raw_reg(reg, 32);
 636         val &= ~GENMASK(offset + 4 - 1, offset);
 637         val |= strength << offset;
 638
 639         if (unlock_reg)
 640                 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 641
 642         sh_pfc_write_raw_reg(reg, 32, val);
 643
 644         return 0;
 645 }
 646
 647 /* Check whether the requested parameter is supported for a pin. */
 648 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
 649                                     unsigned int param)
 650 {
 651         int idx = sh_pfc_get_pin_index(pfc, _pin);
 652         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 653
 654         switch (param) {
 655         case PIN_CONFIG_BIAS_DISABLE:
 656                 return pin->configs &
 657                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
 658
 659         case PIN_CONFIG_BIAS_PULL_UP:
 660                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 661
 662         case PIN_CONFIG_BIAS_PULL_DOWN:
 663                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 664
 665         case PIN_CONFIG_DRIVE_STRENGTH:
 666                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 667
 668         case PIN_CONFIG_POWER_SOURCE:
 669                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
 670
 671         default:
 672                 return false;
 673         }
 674 }
 675
 676 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 677                               unsigned int param, unsigned int arg)
 678 {
 679         struct sh_pfc *pfc = pmx->pfc;
 680         void __iomem *pocctrl;
 681         void __iomem *unlock_reg =
 682                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 683         u32 addr, val;
 684         int bit, ret;
 685
 686         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
 687                 return -ENOTSUPP;
 688
 689         switch (param) {
 690         case PIN_CONFIG_BIAS_PULL_UP:
 691         case PIN_CONFIG_BIAS_PULL_DOWN:
 692         case PIN_CONFIG_BIAS_DISABLE:
 693                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
 694                         return -ENOTSUPP;
 695
 696                 pfc->info->ops->set_bias(pfc, _pin, param);
 697
 698                 break;
 699
 700         case PIN_CONFIG_DRIVE_STRENGTH:
 701                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
 702                 if (ret < 0)
 703                         return ret;
 704
 705                 break;
 706
 707         case PIN_CONFIG_POWER_SOURCE:
 708                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 709                         return -ENOTSUPP;
 710
 711                 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
 712                 if (bit < 0) {
 713                         printf("invalid pin %#x", _pin);
 714                         return bit;
 715                 }
 716
 717                 if (arg != 1800 && arg != 3300)
 718                         return -EINVAL;
 719
 720                 pocctrl = (void __iomem *)(uintptr_t)addr;
 721
 722                 val = sh_pfc_read_raw_reg(pocctrl, 32);
 723                 if (arg == 3300)
 724                         val |= BIT(bit);
 725                 else
 726                         val &= ~BIT(bit);
 727
 728                 if (unlock_reg)
 729                         sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 730
 731                 sh_pfc_write_raw_reg(pocctrl, 32, val);
 732
 733                 break;
 734
 735         default:
 736                 return -ENOTSUPP;
 737         }
 738
 739         return 0;
 740 }
 741
 742 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
 743                                   unsigned int pin_selector,
 744                                   unsigned int param, unsigned int arg)
 745 {
 746         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 747         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 748         struct sh_pfc *pfc = &priv->pfc;
 749         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
 750
 751         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
 752
 753         return 0;
 754 }
 755
 756 static int sh_pfc_pinconf_group_set(struct udevice *dev,
 757                                       unsigned int group_selector,
 758                                       unsigned int param, unsigned int arg)
 759 {
 760         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 761         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 762         struct sh_pfc *pfc = &priv->pfc;
 763         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
 764         unsigned int i;
 765
 766         for (i = 0; i < grp->nr_pins; i++)
 767                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
 768
 769         return 0;
 770 }
 771 #endif
 772
 773 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 774         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
 775         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
 776         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
 777         .get_group_name         = sh_pfc_pinctrl_get_group_name,
 778         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
 779         .get_function_name      = sh_pfc_pinctrl_get_function_name,
 780
 781 #if CONFIG_IS_ENABLED(PINCONF)
 782         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
 783         .pinconf_params         = sh_pfc_pinconf_params,
 784         .pinconf_set            = sh_pfc_pinconf_pin_set,
 785         .pinconf_group_set      = sh_pfc_pinconf_group_set,
 786 #endif
 787         .pinmux_set             = sh_pfc_pinctrl_pin_set,
 788         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
 789         .set_state              = pinctrl_generic_set_state,
 790
 791         .gpio_request_enable    = sh_pfc_gpio_request_enable,
 792         .gpio_disable_free      = sh_pfc_gpio_disable_free,
 793 };
 794
 795 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 796 {
 797         unsigned int i;
 798
 799         /* Allocate and initialize the pins and configs arrays. */
 800         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
 801                                     GFP_KERNEL);
 802         if (unlikely(!pmx->configs))
 803                 return -ENOMEM;
 804
 805         for (i = 0; i < pfc->info->nr_pins; ++i) {
 806                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
 807                 cfg->type = PINMUX_TYPE_NONE;
 808         }
 809
 810         return 0;
 811 }
 812
 813
 814 static int sh_pfc_pinctrl_probe(struct udevice *dev)
 815 {
 816         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 817         enum sh_pfc_model model = dev_get_driver_data(dev);
 818         fdt_addr_t base;
 819
 820         base = devfdt_get_addr(dev);
 821         if (base == FDT_ADDR_T_NONE)
 822                 return -EINVAL;
 823
 824         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
 825         if (!priv->pfc.regs)
 826                 return -ENOMEM;
 827
 828 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 829         if (model == SH_PFC_R8A7790)
 830                 priv->pfc.info = &r8a7790_pinmux_info;
 831 #endif
 832 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 833         if (model == SH_PFC_R8A7791)
 834                 priv->pfc.info = &r8a7791_pinmux_info;
 835 #endif
 836 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 837         if (model == SH_PFC_R8A7792)
 838                 priv->pfc.info = &r8a7792_pinmux_info;
 839 #endif
 840 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 841         if (model == SH_PFC_R8A7793)
 842                 priv->pfc.info = &r8a7793_pinmux_info;
 843 #endif
 844 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 845         if (model == SH_PFC_R8A7794)
 846                 priv->pfc.info = &r8a7794_pinmux_info;
 847 #endif
 848 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 849         if (model == SH_PFC_R8A7795)
 850                 priv->pfc.info = &r8a7795_pinmux_info;
 851 #endif
 852 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 853         if (model == SH_PFC_R8A7796)
 854                 priv->pfc.info = &r8a7796_pinmux_info;
 855 #endif
 856 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 857         if (model == SH_PFC_R8A77965)
 858                 priv->pfc.info = &r8a77965_pinmux_info;
 859 #endif
 860 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 861         if (model == SH_PFC_R8A77970)
 862                 priv->pfc.info = &r8a77970_pinmux_info;
 863 #endif
 864 #ifdef CONFIG_PINCTRL_PFC_R8A77980
 865         if (model == SH_PFC_R8A77980)
 866                 priv->pfc.info = &r8a77980_pinmux_info;
 867 #endif
 868 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 869         if (model == SH_PFC_R8A77990)
 870                 priv->pfc.info = &r8a77990_pinmux_info;
 871 #endif
 872 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 873         if (model == SH_PFC_R8A77995)
 874                 priv->pfc.info = &r8a77995_pinmux_info;
 875 #endif
 876
 877         priv->pmx.pfc = &priv->pfc;
 878         sh_pfc_init_ranges(&priv->pfc);
 879         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
 880
 881         return 0;
 882 }
 883
 884 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
 885 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 886         {
 887                 .compatible = "renesas,pfc-r8a7790",
 888                 .data = SH_PFC_R8A7790,
 889         },
 890 #endif
 891 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 892         {
 893                 .compatible = "renesas,pfc-r8a7791",
 894                 .data = SH_PFC_R8A7791,
 895         },
 896 #endif
 897 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 898         {
 899                 .compatible = "renesas,pfc-r8a7792",
 900                 .data = SH_PFC_R8A7792,
 901         },
 902 #endif
 903 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 904         {
 905                 .compatible = "renesas,pfc-r8a7793",
 906                 .data = SH_PFC_R8A7793,
 907         },
 908 #endif
 909 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 910         {
 911                 .compatible = "renesas,pfc-r8a7794",
 912                 .data = SH_PFC_R8A7794,
 913         },
 914 #endif
 915 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 916         {
 917                 .compatible = "renesas,pfc-r8a7795",
 918                 .data = SH_PFC_R8A7795,
 919         },
 920 #endif
 921 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 922         {
 923                 .compatible = "renesas,pfc-r8a7796",
 924                 .data = SH_PFC_R8A7796,
 925         },
 926 #endif
 927 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 928         {
 929                 .compatible = "renesas,pfc-r8a77965",
 930                 .data = SH_PFC_R8A77965,
 931         },
 932 #endif
 933 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 934         {
 935                 .compatible = "renesas,pfc-r8a77970",
 936                 .data = SH_PFC_R8A77970,
 937         },
 938 #endif
 939 #ifdef CONFIG_PINCTRL_PFC_R8A77980
 940         {
 941                 .compatible = "renesas,pfc-r8a77980",
 942                 .data = SH_PFC_R8A77980,
 943         },
 944 #endif
 945 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 946         {
 947                 .compatible = "renesas,pfc-r8a77990",
 948                 .data = SH_PFC_R8A77990,
 949         },
 950 #endif
 951 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 952         {
 953                 .compatible = "renesas,pfc-r8a77995",
 954                 .data = SH_PFC_R8A77995,
 955         },
 956 #endif
 957         { },
 958 };
 959
 960 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
 961         .name           = "sh_pfc_pinctrl",
 962         .id             = UCLASS_PINCTRL,
 963         .of_match       = sh_pfc_pinctrl_ids,
 964         .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
 965         .ops            = &sh_pfc_pinctrl_ops,
 966         .probe          = sh_pfc_pinctrl_probe,
 967 };