drivers/pinctrl/pinctrl-single.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <dm/device_compat.h>
   9 #include <dm/pinctrl.h>
  10 #include <linux/libfdt.h>
  11 #include <asm/io.h>
  12
  13 struct single_pdata {
  14         fdt_addr_t base;        /* first configuration register */
  15         int offset;             /* index of last configuration register */
  16         u32 mask;               /* configuration-value mask bits */
  17         int width;              /* configuration register bit width */
  18         bool bits_per_mux;
  19 };
  20
  21 struct single_fdt_pin_cfg {
  22         fdt32_t reg;            /* configuration register offset */
  23         fdt32_t val;            /* configuration register value */
  24 };
  25
  26 struct single_fdt_bits_cfg {
  27         fdt32_t reg;            /* configuration register offset */
  28         fdt32_t val;            /* configuration register value */
  29         fdt32_t mask;           /* configuration register mask */
  30 };
  31
  32 /**
  33  * single_configure_pins() - Configure pins based on FDT data
  34  *
  35  * @dev: Pointer to single pin configuration device which is the parent of
  36  *       the pins node holding the pin configuration data.
  37  * @pins: Pointer to the first element of an array of register/value pairs
  38  *        of type 'struct single_fdt_pin_cfg'. Each such pair describes the
  39  *        the pin to be configured and the value to be used for configuration.
  40  *        This pointer points to a 'pinctrl-single,pins' property in the
  41  *        device-tree.
  42  * @size: Size of the 'pins' array in bytes.
  43  *        The number of register/value pairs in the 'pins' array therefore
  44  *        equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
  45  */
  46 static int single_configure_pins(struct udevice *dev,
  47                                  const struct single_fdt_pin_cfg *pins,
  48                                  int size)
  49 {
  50         struct single_pdata *pdata = dev->platdata;
  51         int count = size / sizeof(struct single_fdt_pin_cfg);
  52         phys_addr_t n, reg;
  53         u32 val;
  54
  55         for (n = 0; n < count; n++, pins++) {
  56                 reg = fdt32_to_cpu(pins->reg);
  57                 if ((reg < 0) || (reg > pdata->offset)) {
  58                         dev_dbg(dev, "  invalid register offset 0x%pa\n", &reg);
  59                         continue;
  60                 }
  61                 reg += pdata->base;
  62                 val = fdt32_to_cpu(pins->val) & pdata->mask;
  63                 switch (pdata->width) {
  64                 case 16:
  65                         writew((readw(reg) & ~pdata->mask) | val, reg);
  66                         break;
  67                 case 32:
  68                         writel((readl(reg) & ~pdata->mask) | val, reg);
  69                         break;
  70                 default:
  71                         dev_warn(dev, "unsupported register width %i\n",
  72                                  pdata->width);
  73                         continue;
  74                 }
  75                 dev_dbg(dev, "  reg/val 0x%pa/0x%08x\n", &reg, val);
  76         }
  77         return 0;
  78 }
  79
  80 static int single_configure_bits(struct udevice *dev,
  81                                  const struct single_fdt_bits_cfg *pins,
  82                                  int size)
  83 {
  84         struct single_pdata *pdata = dev->platdata;
  85         int count = size / sizeof(struct single_fdt_bits_cfg);
  86         phys_addr_t n, reg;
  87         u32 val, mask;
  88
  89         for (n = 0; n < count; n++, pins++) {
  90                 reg = fdt32_to_cpu(pins->reg);
  91                 if ((reg < 0) || (reg > pdata->offset)) {
  92                         dev_dbg(dev, "  invalid register offset 0x%pa\n", &reg);
  93                         continue;
  94                 }
  95                 reg += pdata->base;
  96
  97                 mask = fdt32_to_cpu(pins->mask);
  98                 val = fdt32_to_cpu(pins->val) & mask;
  99
 100                 switch (pdata->width) {
 101                 case 16:
 102                         writew((readw(reg) & ~mask) | val, reg);
 103                         break;
 104                 case 32:
 105                         writel((readl(reg) & ~mask) | val, reg);
 106                         break;
 107                 default:
 108                         dev_warn(dev, "unsupported register width %i\n",
 109                                  pdata->width);
 110                         continue;
 111                 }
 112                 dev_dbg(dev, "  reg/val 0x%pa/0x%08x\n", &reg, val);
 113         }
 114         return 0;
 115 }
 116 static int single_set_state(struct udevice *dev,
 117                             struct udevice *config)
 118 {
 119         const struct single_fdt_pin_cfg *prop;
 120         const struct single_fdt_bits_cfg *prop_bits;
 121         int len;
 122
 123         prop = dev_read_prop(config, "pinctrl-single,pins", &len);
 124
 125         if (prop) {
 126                 dev_dbg(dev, "configuring pins for %s\n", config->name);
 127                 if (len % sizeof(struct single_fdt_pin_cfg)) {
 128                         dev_dbg(dev, "  invalid pin configuration in fdt\n");
 129                         return -FDT_ERR_BADSTRUCTURE;
 130                 }
 131                 single_configure_pins(dev, prop, len);
 132                 return 0;
 133         }
 134
 135         /* pinctrl-single,pins not found so check for pinctrl-single,bits */
 136         prop_bits = dev_read_prop(config, "pinctrl-single,bits", &len);
 137         if (prop_bits) {
 138                 dev_dbg(dev, "configuring pins for %s\n", config->name);
 139                 if (len % sizeof(struct single_fdt_bits_cfg)) {
 140                         dev_dbg(dev, "  invalid bits configuration in fdt\n");
 141                         return -FDT_ERR_BADSTRUCTURE;
 142                 }
 143                 single_configure_bits(dev, prop_bits, len);
 144                 return 0;
 145         }
 146
 147         /* Neither 'pinctrl-single,pins' nor 'pinctrl-single,bits' were found */
 148         return len;
 149 }
 150
 151 static int single_ofdata_to_platdata(struct udevice *dev)
 152 {
 153         fdt_addr_t addr;
 154         u32 of_reg[2];
 155         int res;
 156         struct single_pdata *pdata = dev->platdata;
 157
 158         pdata->width =
 159                 dev_read_u32_default(dev, "pinctrl-single,register-width", 0);
 160
 161         res = dev_read_u32_array(dev, "reg", of_reg, 2);
 162         if (res)
 163                 return res;
 164         pdata->offset = of_reg[1] - pdata->width / 8;
 165
 166         addr = dev_read_addr(dev);
 167         if (addr == FDT_ADDR_T_NONE) {
 168                 dev_dbg(dev, "no valid base register address\n");
 169                 return -EINVAL;
 170         }
 171         pdata->base = addr;
 172
 173         pdata->mask = dev_read_u32_default(dev, "pinctrl-single,function-mask",
 174                                            0xffffffff);
 175         pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux");
 176
 177         return 0;
 178 }
 179
 180 const struct pinctrl_ops single_pinctrl_ops = {
 181         .set_state = single_set_state,
 182 };
 183
 184 static const struct udevice_id single_pinctrl_match[] = {
 185         { .compatible = "pinctrl-single" },
 186         { /* sentinel */ }
 187 };
 188
 189 U_BOOT_DRIVER(single_pinctrl) = {
 190         .name = "single-pinctrl",
 191         .id = UCLASS_PINCTRL,
 192         .of_match = single_pinctrl_match,
 193         .ops = &single_pinctrl_ops,
 194         .platdata_auto_alloc_size = sizeof(struct single_pdata),
 195         .ofdata_to_platdata = single_ofdata_to_platdata,
 196 };