drivers/pinctrl/nxp/pinctrl-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <mapmem.h>
   8 #include <dm/devres.h>
   9 #include <linux/io.h>
  10 #include <linux/err.h>
  11 #include <dm.h>
  12 #include <dm/pinctrl.h>
  13
  14 #include "pinctrl-imx.h"
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  19 {
  20         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
  21         struct imx_pinctrl_soc_info *info = priv->info;
  22         int node = dev_of_offset(config);
  23         const struct fdt_property *prop;
  24         u32 *pin_data;
  25         int npins, size, pin_size;
  26         int mux_reg, conf_reg, input_reg;
  27         u32 input_val, mux_mode, config_val;
  28         u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
  29         int i, j = 0;
  30
  31         dev_dbg(dev, "%s: %s\n", __func__, config->name);
  32
  33         if (info->flags & IMX8_USE_SCU)
  34                 pin_size = SHARE_IMX8_PIN_SIZE;
  35         else if (info->flags & SHARE_MUX_CONF_REG)
  36                 pin_size = SHARE_FSL_PIN_SIZE;
  37         else
  38                 pin_size = FSL_PIN_SIZE;
  39
  40         prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
  41         if (!prop) {
  42                 dev_err(dev, "No fsl,pins property in node %s\n", config->name);
  43                 return -EINVAL;
  44         }
  45
  46         if (!size || size % pin_size) {
  47                 dev_err(dev, "Invalid fsl,pins property in node %s\n",
  48                         config->name);
  49                 return -EINVAL;
  50         }
  51
  52         pin_data = devm_kzalloc(dev, size, 0);
  53         if (!pin_data)
  54                 return -ENOMEM;
  55
  56         if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
  57                                  pin_data, size >> 2)) {
  58                 dev_err(dev, "Error reading pin data.\n");
  59                 devm_kfree(dev, pin_data);
  60                 return -EINVAL;
  61         }
  62
  63         npins = size / pin_size;
  64
  65         if (info->flags & IMX8_USE_SCU) {
  66                 imx_pinctrl_scu_conf_pins(info, pin_data, npins);
  67         } else {
  68                 /*
  69                  * Refer to linux documentation for details:
  70                  * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
  71                  */
  72                 for (i = 0; i < npins; i++) {
  73                         mux_reg = pin_data[j++];
  74
  75                         if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
  76                                 mux_reg = -1;
  77
  78                         if (info->flags & SHARE_MUX_CONF_REG) {
  79                                 conf_reg = mux_reg;
  80                         } else {
  81                                 conf_reg = pin_data[j++];
  82                                 if (!(info->flags & ZERO_OFFSET_VALID) &&
  83                                     !conf_reg)
  84                                         conf_reg = -1;
  85                         }
  86
  87                         if ((mux_reg == -1) || (conf_reg == -1)) {
  88                                 dev_err(dev, "Error mux_reg or conf_reg\n");
  89                                 devm_kfree(dev, pin_data);
  90                                 return -EINVAL;
  91                         }
  92
  93                         input_reg = pin_data[j++];
  94                         mux_mode = pin_data[j++];
  95                         input_val = pin_data[j++];
  96                         config_val = pin_data[j++];
  97
  98                         dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, "
  99                                 "input_reg 0x%x, mux_mode 0x%x, "
 100                                 "input_val 0x%x, config_val 0x%x\n",
 101                                 mux_reg, conf_reg, input_reg, mux_mode,
 102                                 input_val, config_val);
 103
 104                         if (config_val & IMX_PAD_SION)
 105                                 mux_mode |= IOMUXC_CONFIG_SION;
 106
 107                         config_val &= ~IMX_PAD_SION;
 108
 109                         /* Set Mux */
 110                         if (info->flags & SHARE_MUX_CONF_REG) {
 111                                 clrsetbits_le32(info->base + mux_reg,
 112                                                 info->mux_mask,
 113                                                 mux_mode << mux_shift);
 114                         } else {
 115                                 writel(mux_mode, info->base + mux_reg);
 116                         }
 117
 118                         dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n",
 119                                 mux_reg, mux_mode);
 120
 121                         /*
 122                          * Set select input
 123                          *
 124                          * If the select input value begins with 0xff,
 125                          * it's a quirky select input and the value should
 126                          * be interpreted as below.
 127                          *     31     23      15      7        0
 128                          *     | 0xff | shift | width | select |
 129                          * It's used to work around the problem that the
 130                          * select input for some pin is not implemented in
 131                          * the select input register but in some general
 132                          * purpose register. We encode the select input
 133                          * value, width and shift of the bit field into
 134                          * input_val cell of pin function ID in device tree,
 135                          * and then decode them here for setting up the select
 136                          * input bits in general purpose register.
 137                          */
 138
 139                         if (input_val >> 24 == 0xff) {
 140                                 u32 val = input_val;
 141                                 u8 select = val & 0xff;
 142                                 u8 width = (val >> 8) & 0xff;
 143                                 u8 shift = (val >> 16) & 0xff;
 144                                 u32 mask = ((1 << width) - 1) << shift;
 145                                 /*
 146                                  * The input_reg[i] here is actually some
 147                                  * IOMUXC general purpose register, not
 148                                  * regular select input register.
 149                                  */
 150                                 val = readl(info->base + input_reg);
 151                                 val &= ~mask;
 152                                 val |= select << shift;
 153                                 writel(val, info->base + input_reg);
 154                         } else if (input_reg) {
 155                                 /*
 156                                  * Regular select input register can never be
 157                                  * at offset 0, and we only print register
 158                                  * value for regular case.
 159                                  */
 160                                 if (info->input_sel_base)
 161                                         writel(input_val,
 162                                                info->input_sel_base +
 163                                                input_reg);
 164                                 else
 165                                         writel(input_val,
 166                                                info->base + input_reg);
 167
 168                                 dev_dbg(dev, "select_input: offset 0x%x val "
 169                                         "0x%x\n", input_reg, input_val);
 170                         }
 171
 172                         /* Set config */
 173                         if (!(config_val & IMX_NO_PAD_CTL)) {
 174                                 if (info->flags & SHARE_MUX_CONF_REG) {
 175                                         clrsetbits_le32(info->base + conf_reg,
 176                                                         ~info->mux_mask,
 177                                                         config_val);
 178                                 } else {
 179                                         writel(config_val,
 180                                                info->base + conf_reg);
 181                                 }
 182
 183                                 dev_dbg(dev, "write config: offset 0x%x val "
 184                                         "0x%x\n", conf_reg, config_val);
 185                         }
 186                 }
 187         }
 188
 189         devm_kfree(dev, pin_data);
 190
 191         return 0;
 192 }
 193
 194 const struct pinctrl_ops imx_pinctrl_ops  = {
 195         .set_state = imx_pinctrl_set_state,
 196 };
 197
 198 int imx_pinctrl_probe(struct udevice *dev,
 199                       struct imx_pinctrl_soc_info *info)
 200 {
 201         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 202         int node = dev_of_offset(dev), ret;
 203         struct fdtdec_phandle_args arg;
 204         fdt_addr_t addr;
 205         fdt_size_t size;
 206
 207         if (!info) {
 208                 dev_err(dev, "wrong pinctrl info\n");
 209                 return -EINVAL;
 210         }
 211
 212         priv->dev = dev;
 213         priv->info = info;
 214
 215         if (info->flags & IMX8_USE_SCU)
 216                 return 0;
 217
 218         addr = devfdt_get_addr_size_index(dev, 0, &size);
 219         if (addr == FDT_ADDR_T_NONE)
 220                 return -EINVAL;
 221
 222         info->base = map_sysmem(addr, size);
 223         if (!info->base)
 224                 return -ENOMEM;
 225         priv->info = info;
 226
 227         info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
 228         /*
 229          * Refer to linux documentation for details:
 230          * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
 231          */
 232         if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
 233                 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
 234                                                      node, "fsl,input-sel",
 235                                                      NULL, 0, 0, &arg);
 236                 if (ret) {
 237                         dev_err(dev, "iomuxc fsl,input-sel property not found\n");
 238                         return -EINVAL;
 239                 }
 240
 241                 addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
 242                                             &size);
 243                 if (addr == FDT_ADDR_T_NONE)
 244                         return -EINVAL;
 245
 246                 info->input_sel_base = map_sysmem(addr, size);
 247                 if (!info->input_sel_base)
 248                         return -ENOMEM;
 249         }
 250
 251         dev_dbg(dev, "initialized IMX pinctrl driver\n");
 252
 253         return 0;
 254 }
 255
 256 int imx_pinctrl_remove(struct udevice *dev)
 257 {
 258         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 259         struct imx_pinctrl_soc_info *info = priv->info;
 260
 261         if (info->flags & IMX8_USE_SCU)
 262                 return 0;
 263
 264         if (info->input_sel_base)
 265                 unmap_sysmem(info->input_sel_base);
 266         if (info->base)
 267                 unmap_sysmem(info->base);
 268
 269         return 0;
 270 }