drivers/phy/ti-pipe3-phy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
   4  * Written by Jean-Jacques Hiblot  <jjhiblot@ti.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <dm/device.h>
  10 #include <generic-phy.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <syscon.h>
  14 #include <regmap.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17
  18 /* PLLCTRL Registers */
  19 #define PLL_STATUS              0x00000004
  20 #define PLL_GO                  0x00000008
  21 #define PLL_CONFIGURATION1      0x0000000C
  22 #define PLL_CONFIGURATION2      0x00000010
  23 #define PLL_CONFIGURATION3      0x00000014
  24 #define PLL_CONFIGURATION4      0x00000020
  25
  26 #define PLL_REGM_MASK           0x001FFE00
  27 #define PLL_REGM_SHIFT          9
  28 #define PLL_REGM_F_MASK         0x0003FFFF
  29 #define PLL_REGM_F_SHIFT        0
  30 #define PLL_REGN_MASK           0x000001FE
  31 #define PLL_REGN_SHIFT          1
  32 #define PLL_SELFREQDCO_MASK     0x0000000E
  33 #define PLL_SELFREQDCO_SHIFT    1
  34 #define PLL_SD_MASK             0x0003FC00
  35 #define PLL_SD_SHIFT            10
  36 #define SET_PLL_GO              0x1
  37 #define PLL_TICOPWDN            BIT(16)
  38 #define PLL_LDOPWDN             BIT(15)
  39 #define PLL_LOCK                0x2
  40 #define PLL_IDLE                0x1
  41
  42 /* Software rest for the SATA PLL (in CTRL_CORE_SMA_SW_0 register)*/
  43 #define SATA_PLL_SOFT_RESET (1<<18)
  44
  45 /* PHY POWER CONTROL Register */
  46 #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK   GENMASK(21, 14)
  47 #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT  14
  48
  49 #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK  GENMASK(31, 22)
  50 #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
  51
  52 #define PIPE3_PHY_RX_POWERON       (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  53 #define PIPE3_PHY_TX_POWERON       (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  54
  55 /* PHY RX Registers */
  56 #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY        0x0000000C
  57 #define INTERFACE_MASK                  GENMASK(31, 27)
  58 #define INTERFACE_SHIFT                 27
  59 #define INTERFACE_MODE_USBSS            BIT(4)
  60 #define INTERFACE_MODE_SATA_1P5         BIT(3)
  61 #define INTERFACE_MODE_SATA_3P0         BIT(2)
  62 #define INTERFACE_MODE_PCIE             BIT(0)
  63
  64 #define LOSD_MASK                       GENMASK(17, 14)
  65 #define LOSD_SHIFT                      14
  66 #define MEM_PLLDIV                      GENMASK(6, 5)
  67
  68 #define PIPE3_PHY_RX_TRIM               0x0000001C
  69 #define MEM_DLL_TRIM_SEL_MASK           GENMASK(31, 30)
  70 #define MEM_DLL_TRIM_SHIFT              30
  71
  72 #define PIPE3_PHY_RX_DLL                0x00000024
  73 #define MEM_DLL_PHINT_RATE_MASK         GENMASK(31, 30)
  74 #define MEM_DLL_PHINT_RATE_SHIFT        30
  75
  76 #define PIPE3_PHY_RX_DIGITAL_MODES              0x00000028
  77 #define MEM_HS_RATE_MASK                GENMASK(28, 27)
  78 #define MEM_HS_RATE_SHIFT               27
  79 #define MEM_OVRD_HS_RATE                BIT(26)
  80 #define MEM_OVRD_HS_RATE_SHIFT          26
  81 #define MEM_CDR_FASTLOCK                BIT(23)
  82 #define MEM_CDR_FASTLOCK_SHIFT          23
  83 #define MEM_CDR_LBW_MASK                GENMASK(22, 21)
  84 #define MEM_CDR_LBW_SHIFT               21
  85 #define MEM_CDR_STEPCNT_MASK            GENMASK(20, 19)
  86 #define MEM_CDR_STEPCNT_SHIFT           19
  87 #define MEM_CDR_STL_MASK                GENMASK(18, 16)
  88 #define MEM_CDR_STL_SHIFT               16
  89 #define MEM_CDR_THR_MASK                GENMASK(15, 13)
  90 #define MEM_CDR_THR_SHIFT               13
  91 #define MEM_CDR_THR_MODE                BIT(12)
  92 #define MEM_CDR_THR_MODE_SHIFT          12
  93 #define MEM_CDR_2NDO_SDM_MODE           BIT(11)
  94 #define MEM_CDR_2NDO_SDM_MODE_SHIFT     11
  95
  96 #define PIPE3_PHY_RX_EQUALIZER          0x00000038
  97 #define MEM_EQLEV_MASK                  GENMASK(31, 16)
  98 #define MEM_EQLEV_SHIFT                 16
  99 #define MEM_EQFTC_MASK                  GENMASK(15, 11)
 100 #define MEM_EQFTC_SHIFT                 11
 101 #define MEM_EQCTL_MASK                  GENMASK(10, 7)
 102 #define MEM_EQCTL_SHIFT                 7
 103 #define MEM_OVRD_EQLEV                  BIT(2)
 104 #define MEM_OVRD_EQLEV_SHIFT            2
 105 #define MEM_OVRD_EQFTC                  BIT(1)
 106 #define MEM_OVRD_EQFTC_SHIFT            1
 107
 108 #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES        0x44
 109 #define MEM_CDR_LOS_SOURCE_MASK         GENMASK(10, 9)
 110 #define MEM_CDR_LOS_SOURCE_SHIFT        9
 111
 112 #define PLL_IDLE_TIME   100     /* in milliseconds */
 113 #define PLL_LOCK_TIME   100     /* in milliseconds */
 114
 115 enum pipe3_mode { PIPE3_MODE_PCIE = 1,
 116                   PIPE3_MODE_SATA,
 117                   PIPE3_MODE_USBSS };
 118
 119 struct pipe3_settings {
 120         u8 ana_interface;
 121         u8 ana_losd;
 122         u8 dig_fastlock;
 123         u8 dig_lbw;
 124         u8 dig_stepcnt;
 125         u8 dig_stl;
 126         u8 dig_thr;
 127         u8 dig_thr_mode;
 128         u8 dig_2ndo_sdm_mode;
 129         u8 dig_hs_rate;
 130         u8 dig_ovrd_hs_rate;
 131         u8 dll_trim_sel;
 132         u8 dll_phint_rate;
 133         u8 eq_lev;
 134         u8 eq_ftc;
 135         u8 eq_ctl;
 136         u8 eq_ovrd_lev;
 137         u8 eq_ovrd_ftc;
 138 };
 139
 140 struct omap_pipe3 {
 141         void __iomem            *pll_ctrl_base;
 142         void __iomem            *phy_rx;
 143         void __iomem            *power_reg;
 144         void __iomem            *pll_reset_reg;
 145         struct pipe3_dpll_map   *dpll_map;
 146         enum pipe3_mode         mode;
 147         struct pipe3_settings   settings;
 148 };
 149
 150 struct pipe3_dpll_params {
 151         u16     m;
 152         u8      n;
 153         u8      freq:3;
 154         u8      sd;
 155         u32     mf;
 156 };
 157
 158 struct pipe3_dpll_map {
 159         unsigned long rate;
 160         struct pipe3_dpll_params params;
 161 };
 162
 163 struct pipe3_data {
 164         enum pipe3_mode mode;
 165         struct pipe3_dpll_map *dpll_map;
 166         struct pipe3_settings settings;
 167 };
 168
 169 static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
 170 {
 171         return readl(addr + offset);
 172 }
 173
 174 static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
 175                 u32 data)
 176 {
 177         writel(data, addr + offset);
 178 }
 179
 180 static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
 181                                                                         *pipe3)
 182 {
 183         u32 rate;
 184         struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
 185
 186         rate = get_sys_clk_freq();
 187
 188         for (; dpll_map->rate; dpll_map++) {
 189                 if (rate == dpll_map->rate)
 190                         return &dpll_map->params;
 191         }
 192
 193         printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
 194                __func__, rate);
 195         return NULL;
 196 }
 197
 198 static int omap_pipe3_wait_lock(struct omap_pipe3 *pipe3)
 199 {
 200         u32 val;
 201         int timeout = PLL_LOCK_TIME;
 202
 203         do {
 204                 mdelay(1);
 205                 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
 206                 if (val & PLL_LOCK)
 207                         break;
 208         } while (--timeout);
 209
 210         if (!(val & PLL_LOCK)) {
 211                 printf("%s: DPLL failed to lock\n", __func__);
 212                 return -EBUSY;
 213         }
 214
 215         return 0;
 216 }
 217
 218 static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
 219 {
 220         u32                     val;
 221         struct pipe3_dpll_params *dpll_params;
 222
 223         dpll_params = omap_pipe3_get_dpll_params(pipe3);
 224         if (!dpll_params) {
 225                 printf("%s: Invalid DPLL parameters\n", __func__);
 226                 return -EINVAL;
 227         }
 228
 229         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
 230         val &= ~PLL_REGN_MASK;
 231         val |= dpll_params->n << PLL_REGN_SHIFT;
 232         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
 233
 234         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
 235         val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
 236         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 237         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
 238
 239         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
 240         val &= ~PLL_REGM_MASK;
 241         val |= dpll_params->m << PLL_REGM_SHIFT;
 242         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
 243
 244         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);
 245         val &= ~PLL_REGM_F_MASK;
 246         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 247         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);
 248
 249         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);
 250         val &= ~PLL_SD_MASK;
 251         val |= dpll_params->sd << PLL_SD_SHIFT;
 252         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);
 253
 254         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 255
 256         return omap_pipe3_wait_lock(pipe3);
 257 }
 258
 259 static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
 260 {
 261         u32 val, rate;
 262
 263         val = readl(pipe3->power_reg);
 264
 265         rate = get_sys_clk_freq();
 266         rate = rate/1000000;
 267
 268         if (on) {
 269                 val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
 270                          PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
 271                 val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
 272                 writel(val, pipe3->power_reg);
 273
 274                 /* Power up TX before RX for SATA & USB */
 275                 val |= PIPE3_PHY_TX_POWERON;
 276                 writel(val, pipe3->power_reg);
 277
 278                 val |= PIPE3_PHY_RX_POWERON;
 279                 writel(val, pipe3->power_reg);
 280         } else {
 281                 val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
 282                 writel(val, pipe3->power_reg);
 283         }
 284 }
 285
 286 static void ti_pipe3_calibrate(struct omap_pipe3 *phy)
 287 {
 288         u32 val;
 289         struct pipe3_settings *s = &phy->settings;
 290
 291         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
 292         val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
 293         val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
 294         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
 295
 296         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
 297         val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
 298                  MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
 299                  MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
 300         val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
 301                 s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
 302                 s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
 303                 s->dig_lbw << MEM_CDR_LBW_SHIFT |
 304                 s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
 305                 s->dig_stl << MEM_CDR_STL_SHIFT |
 306                 s->dig_thr << MEM_CDR_THR_SHIFT |
 307                 s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
 308                 s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
 309         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
 310
 311         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
 312         val &= ~MEM_DLL_TRIM_SEL_MASK;
 313         val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
 314         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
 315
 316         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
 317         val &= ~MEM_DLL_PHINT_RATE_MASK;
 318         val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
 319         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
 320
 321         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
 322         val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
 323                  MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
 324         val |= s->eq_lev << MEM_EQLEV_SHIFT |
 325                 s->eq_ftc << MEM_EQFTC_SHIFT |
 326                 s->eq_ctl << MEM_EQCTL_SHIFT |
 327                 s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
 328                 s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
 329         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
 330
 331         if (phy->mode == PIPE3_MODE_SATA) {
 332                 val = omap_pipe3_readl(phy->phy_rx,
 333                                        SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
 334                 val &= ~MEM_CDR_LOS_SOURCE_MASK;
 335                 omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
 336                                   val);
 337         }
 338 }
 339
 340 static int pipe3_init(struct phy *phy)
 341 {
 342         int ret;
 343         u32 val;
 344         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 345
 346         /* Program the DPLL only if not locked */
 347         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
 348         if (!(val & PLL_LOCK)) {
 349                 ret = omap_pipe3_dpll_program(pipe3);
 350                 if (ret)
 351                         return ret;
 352
 353                 ti_pipe3_calibrate(pipe3);
 354         } else {
 355                 /* else just bring it out of IDLE mode */
 356                 val = omap_pipe3_readl(pipe3->pll_ctrl_base,
 357                                        PLL_CONFIGURATION2);
 358                 if (val & PLL_IDLE) {
 359                         val &= ~PLL_IDLE;
 360                         omap_pipe3_writel(pipe3->pll_ctrl_base,
 361                                           PLL_CONFIGURATION2, val);
 362                         ret = omap_pipe3_wait_lock(pipe3);
 363                         if (ret)
 364                                 return ret;
 365                 }
 366         }
 367         return 0;
 368 }
 369
 370 static int pipe3_power_on(struct phy *phy)
 371 {
 372         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 373
 374         /* Power up the PHY */
 375         omap_control_pipe3_power(pipe3, 1);
 376
 377         return 0;
 378 }
 379
 380 static int pipe3_power_off(struct phy *phy)
 381 {
 382         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 383
 384         /* Power down the PHY */
 385         omap_control_pipe3_power(pipe3, 0);
 386
 387         return 0;
 388 }
 389
 390 static int pipe3_exit(struct phy *phy)
 391 {
 392         u32 val;
 393         int timeout = PLL_IDLE_TIME;
 394         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 395
 396         pipe3_power_off(phy);
 397
 398         /* Put DPLL in IDLE mode */
 399         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
 400         val |= PLL_IDLE;
 401         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
 402
 403         /* wait for LDO and Oscillator to power down */
 404         do {
 405                 mdelay(1);
 406                 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
 407                 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 408                         break;
 409         } while (--timeout);
 410
 411         if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 412                 pr_err("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
 413                       __func__, val);
 414                 return -EBUSY;
 415         }
 416
 417         if (pipe3->pll_reset_reg) {
 418                 val = readl(pipe3->pll_reset_reg);
 419                 writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
 420                 mdelay(1);
 421                 writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
 422         }
 423
 424         return 0;
 425 }
 426
 427 static void *get_reg(struct udevice *dev, const char *name)
 428 {
 429         struct udevice *syscon;
 430         struct regmap *regmap;
 431         const fdt32_t *cell;
 432         int len, err;
 433         void *base;
 434
 435         err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
 436                                            name, &syscon);
 437         if (err) {
 438                 pr_err("unable to find syscon device for %s (%d)\n",
 439                       name, err);
 440                 return NULL;
 441         }
 442
 443         regmap = syscon_get_regmap(syscon);
 444         if (IS_ERR(regmap)) {
 445                 pr_err("unable to find regmap for %s (%ld)\n",
 446                       name, PTR_ERR(regmap));
 447                 return NULL;
 448         }
 449
 450         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,
 451                            &len);
 452         if (len < 2*sizeof(fdt32_t)) {
 453                 pr_err("offset not available for %s\n", name);
 454                 return NULL;
 455         }
 456
 457         base = regmap_get_range(regmap, 0);
 458         if (!base)
 459                 return NULL;
 460
 461         return fdtdec_get_number(cell + 1, 1) + base;
 462 }
 463
 464 static int pipe3_phy_probe(struct udevice *dev)
 465 {
 466         fdt_addr_t addr;
 467         fdt_size_t sz;
 468         struct omap_pipe3 *pipe3 = dev_get_priv(dev);
 469         struct pipe3_data *data;
 470
 471         /* PHY_RX */
 472         addr = devfdt_get_addr_size_index(dev, 0, &sz);
 473         if (addr == FDT_ADDR_T_NONE) {
 474                 pr_err("missing phy_rx address\n");
 475                 return -EINVAL;
 476         }
 477
 478         pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE);
 479         if (!pipe3->phy_rx) {
 480                 pr_err("unable to remap phy_rx\n");
 481                 return -EINVAL;
 482         }
 483
 484         /* PLLCTRL */
 485         addr = devfdt_get_addr_size_index(dev, 2, &sz);
 486         if (addr == FDT_ADDR_T_NONE) {
 487                 pr_err("missing pll ctrl address\n");
 488                 return -EINVAL;
 489         }
 490
 491         pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
 492         if (!pipe3->pll_ctrl_base) {
 493                 pr_err("unable to remap pll ctrl\n");
 494                 return -EINVAL;
 495         }
 496
 497         pipe3->power_reg = get_reg(dev, "syscon-phy-power");
 498         if (!pipe3->power_reg)
 499                 return -EINVAL;
 500
 501         data = (struct pipe3_data *)dev_get_driver_data(dev);
 502         pipe3->mode = data->mode;
 503         pipe3->dpll_map = data->dpll_map;
 504         pipe3->settings = data->settings;
 505
 506         if (pipe3->mode == PIPE3_MODE_SATA) {
 507                 pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
 508                 if (!pipe3->pll_reset_reg)
 509                         return -EINVAL;
 510         }
 511
 512         return 0;
 513 }
 514
 515 static struct pipe3_dpll_map dpll_map_sata[] = {
 516         {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
 517         {16800000, {625, 6, 4, 7, 0} },         /* 16.8 MHz */
 518         {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
 519         {20000000, {750, 9, 4, 6, 0} },         /* 20 MHz */
 520         {26000000, {750, 12, 4, 6, 0} },        /* 26 MHz */
 521         {38400000, {625, 15, 4, 6, 0} },        /* 38.4 MHz */
 522         { },                                    /* Terminator */
 523 };
 524
 525 static struct pipe3_dpll_map dpll_map_usb[] = {
 526         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
 527         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
 528         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
 529         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
 530         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
 531         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
 532         { },                                    /* Terminator */
 533 };
 534
 535 static struct pipe3_data data_usb = {
 536         .mode = PIPE3_MODE_USBSS,
 537         .dpll_map = dpll_map_usb,
 538         .settings = {
 539         /* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */
 540                 .ana_interface = INTERFACE_MODE_USBSS,
 541                 .ana_losd = 0xa,
 542                 .dig_fastlock = 1,
 543                 .dig_lbw = 3,
 544                 .dig_stepcnt = 0,
 545                 .dig_stl = 0x3,
 546                 .dig_thr = 1,
 547                 .dig_thr_mode = 1,
 548                 .dig_2ndo_sdm_mode = 0,
 549                 .dig_hs_rate = 0,
 550                 .dig_ovrd_hs_rate = 1,
 551                 .dll_trim_sel = 0x2,
 552                 .dll_phint_rate = 0x3,
 553                 .eq_lev = 0,
 554                 .eq_ftc = 0,
 555                 .eq_ctl = 0x9,
 556                 .eq_ovrd_lev = 0,
 557                 .eq_ovrd_ftc = 0,
 558         },
 559 };
 560
 561 static struct pipe3_data data_sata = {
 562         .mode = PIPE3_MODE_SATA,
 563         .dpll_map = dpll_map_sata,
 564         .settings = {
 565         /* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */
 566                 .ana_interface = INTERFACE_MODE_SATA_3P0,
 567                 .ana_losd = 0x5,
 568                 .dig_fastlock = 1,
 569                 .dig_lbw = 3,
 570                 .dig_stepcnt = 0,
 571                 .dig_stl = 0x3,
 572                 .dig_thr = 1,
 573                 .dig_thr_mode = 1,
 574                 .dig_2ndo_sdm_mode = 0,
 575                 .dig_hs_rate = 0,       /* Not in TRM preferred settings */
 576                 .dig_ovrd_hs_rate = 0,  /* Not in TRM preferred settings */
 577                 .dll_trim_sel = 0x1,
 578                 .dll_phint_rate = 0x2,  /* for 1.5 GHz DPLL clock */
 579                 .eq_lev = 0,
 580                 .eq_ftc = 0x1f,
 581                 .eq_ctl = 0,
 582                 .eq_ovrd_lev = 1,
 583                 .eq_ovrd_ftc = 1,
 584         },
 585 };
 586
 587 static const struct udevice_id pipe3_phy_ids[] = {
 588         { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
 589         { .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
 590         { }
 591 };
 592
 593 static struct phy_ops pipe3_phy_ops = {
 594         .init = pipe3_init,
 595         .power_on = pipe3_power_on,
 596         .power_off = pipe3_power_off,
 597         .exit = pipe3_exit,
 598 };
 599
 600 U_BOOT_DRIVER(pipe3_phy) = {
 601         .name   = "pipe3_phy",
 602         .id     = UCLASS_PHY,
 603         .of_match = pipe3_phy_ids,
 604         .ops = &pipe3_phy_ops,
 605         .probe = pipe3_phy_probe,
 606         .priv_auto_alloc_size = sizeof(struct omap_pipe3),
 607 };