drivers/phy/ti-pipe3-phy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
   4  * Written by Jean-Jacques Hiblot  <jjhiblot@ti.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <dm/device.h>
  10 #include <generic-phy.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <syscon.h>
  14 #include <regmap.h>
  15 #include <linux/err.h>
  16
  17 /* PLLCTRL Registers */
  18 #define PLL_STATUS              0x00000004
  19 #define PLL_GO                  0x00000008
  20 #define PLL_CONFIGURATION1      0x0000000C
  21 #define PLL_CONFIGURATION2      0x00000010
  22 #define PLL_CONFIGURATION3      0x00000014
  23 #define PLL_CONFIGURATION4      0x00000020
  24
  25 #define PLL_REGM_MASK           0x001FFE00
  26 #define PLL_REGM_SHIFT          9
  27 #define PLL_REGM_F_MASK         0x0003FFFF
  28 #define PLL_REGM_F_SHIFT        0
  29 #define PLL_REGN_MASK           0x000001FE
  30 #define PLL_REGN_SHIFT          1
  31 #define PLL_SELFREQDCO_MASK     0x0000000E
  32 #define PLL_SELFREQDCO_SHIFT    1
  33 #define PLL_SD_MASK             0x0003FC00
  34 #define PLL_SD_SHIFT            10
  35 #define SET_PLL_GO              0x1
  36 #define PLL_TICOPWDN            BIT(16)
  37 #define PLL_LDOPWDN             BIT(15)
  38 #define PLL_LOCK                0x2
  39 #define PLL_IDLE                0x1
  40
  41 /* Software rest for the SATA PLL (in CTRL_CORE_SMA_SW_0 register)*/
  42 #define SATA_PLL_SOFT_RESET (1<<18)
  43
  44 /* PHY POWER CONTROL Register */
  45 #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK   GENMASK(21, 14)
  46 #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT  14
  47
  48 #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK  GENMASK(31, 22)
  49 #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
  50
  51 #define PIPE3_PHY_RX_POWERON       (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  52 #define PIPE3_PHY_TX_POWERON       (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  53
  54 /* PHY RX Registers */
  55 #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY        0x0000000C
  56 #define INTERFACE_MASK                  GENMASK(31, 27)
  57 #define INTERFACE_SHIFT                 27
  58 #define INTERFACE_MODE_USBSS            BIT(4)
  59 #define INTERFACE_MODE_SATA_1P5         BIT(3)
  60 #define INTERFACE_MODE_SATA_3P0         BIT(2)
  61 #define INTERFACE_MODE_PCIE             BIT(0)
  62
  63 #define LOSD_MASK                       GENMASK(17, 14)
  64 #define LOSD_SHIFT                      14
  65 #define MEM_PLLDIV                      GENMASK(6, 5)
  66
  67 #define PIPE3_PHY_RX_TRIM               0x0000001C
  68 #define MEM_DLL_TRIM_SEL_MASK           GENMASK(31, 30)
  69 #define MEM_DLL_TRIM_SHIFT              30
  70
  71 #define PIPE3_PHY_RX_DLL                0x00000024
  72 #define MEM_DLL_PHINT_RATE_MASK         GENMASK(31, 30)
  73 #define MEM_DLL_PHINT_RATE_SHIFT        30
  74
  75 #define PIPE3_PHY_RX_DIGITAL_MODES              0x00000028
  76 #define MEM_HS_RATE_MASK                GENMASK(28, 27)
  77 #define MEM_HS_RATE_SHIFT               27
  78 #define MEM_OVRD_HS_RATE                BIT(26)
  79 #define MEM_OVRD_HS_RATE_SHIFT          26
  80 #define MEM_CDR_FASTLOCK                BIT(23)
  81 #define MEM_CDR_FASTLOCK_SHIFT          23
  82 #define MEM_CDR_LBW_MASK                GENMASK(22, 21)
  83 #define MEM_CDR_LBW_SHIFT               21
  84 #define MEM_CDR_STEPCNT_MASK            GENMASK(20, 19)
  85 #define MEM_CDR_STEPCNT_SHIFT           19
  86 #define MEM_CDR_STL_MASK                GENMASK(18, 16)
  87 #define MEM_CDR_STL_SHIFT               16
  88 #define MEM_CDR_THR_MASK                GENMASK(15, 13)
  89 #define MEM_CDR_THR_SHIFT               13
  90 #define MEM_CDR_THR_MODE                BIT(12)
  91 #define MEM_CDR_THR_MODE_SHIFT          12
  92 #define MEM_CDR_2NDO_SDM_MODE           BIT(11)
  93 #define MEM_CDR_2NDO_SDM_MODE_SHIFT     11
  94
  95 #define PIPE3_PHY_RX_EQUALIZER          0x00000038
  96 #define MEM_EQLEV_MASK                  GENMASK(31, 16)
  97 #define MEM_EQLEV_SHIFT                 16
  98 #define MEM_EQFTC_MASK                  GENMASK(15, 11)
  99 #define MEM_EQFTC_SHIFT                 11
 100 #define MEM_EQCTL_MASK                  GENMASK(10, 7)
 101 #define MEM_EQCTL_SHIFT                 7
 102 #define MEM_OVRD_EQLEV                  BIT(2)
 103 #define MEM_OVRD_EQLEV_SHIFT            2
 104 #define MEM_OVRD_EQFTC                  BIT(1)
 105 #define MEM_OVRD_EQFTC_SHIFT            1
 106
 107 #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES        0x44
 108 #define MEM_CDR_LOS_SOURCE_MASK         GENMASK(10, 9)
 109 #define MEM_CDR_LOS_SOURCE_SHIFT        9
 110
 111 #define PLL_IDLE_TIME   100     /* in milliseconds */
 112 #define PLL_LOCK_TIME   100     /* in milliseconds */
 113
 114 enum pipe3_mode { PIPE3_MODE_PCIE = 1,
 115                   PIPE3_MODE_SATA,
 116                   PIPE3_MODE_USBSS };
 117
 118 struct pipe3_settings {
 119         u8 ana_interface;
 120         u8 ana_losd;
 121         u8 dig_fastlock;
 122         u8 dig_lbw;
 123         u8 dig_stepcnt;
 124         u8 dig_stl;
 125         u8 dig_thr;
 126         u8 dig_thr_mode;
 127         u8 dig_2ndo_sdm_mode;
 128         u8 dig_hs_rate;
 129         u8 dig_ovrd_hs_rate;
 130         u8 dll_trim_sel;
 131         u8 dll_phint_rate;
 132         u8 eq_lev;
 133         u8 eq_ftc;
 134         u8 eq_ctl;
 135         u8 eq_ovrd_lev;
 136         u8 eq_ovrd_ftc;
 137 };
 138
 139 struct omap_pipe3 {
 140         void __iomem            *pll_ctrl_base;
 141         void __iomem            *phy_rx;
 142         void __iomem            *power_reg;
 143         void __iomem            *pll_reset_reg;
 144         struct pipe3_dpll_map   *dpll_map;
 145         enum pipe3_mode         mode;
 146         struct pipe3_settings   settings;
 147 };
 148
 149 struct pipe3_dpll_params {
 150         u16     m;
 151         u8      n;
 152         u8      freq:3;
 153         u8      sd;
 154         u32     mf;
 155 };
 156
 157 struct pipe3_dpll_map {
 158         unsigned long rate;
 159         struct pipe3_dpll_params params;
 160 };
 161
 162 struct pipe3_data {
 163         enum pipe3_mode mode;
 164         struct pipe3_dpll_map *dpll_map;
 165         struct pipe3_settings settings;
 166 };
 167
 168 static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
 169 {
 170         return readl(addr + offset);
 171 }
 172
 173 static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
 174                 u32 data)
 175 {
 176         writel(data, addr + offset);
 177 }
 178
 179 static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
 180                                                                         *pipe3)
 181 {
 182         u32 rate;
 183         struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
 184
 185         rate = get_sys_clk_freq();
 186
 187         for (; dpll_map->rate; dpll_map++) {
 188                 if (rate == dpll_map->rate)
 189                         return &dpll_map->params;
 190         }
 191
 192         printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
 193                __func__, rate);
 194         return NULL;
 195 }
 196
 197 static int omap_pipe3_wait_lock(struct omap_pipe3 *pipe3)
 198 {
 199         u32 val;
 200         int timeout = PLL_LOCK_TIME;
 201
 202         do {
 203                 mdelay(1);
 204                 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
 205                 if (val & PLL_LOCK)
 206                         break;
 207         } while (--timeout);
 208
 209         if (!(val & PLL_LOCK)) {
 210                 printf("%s: DPLL failed to lock\n", __func__);
 211                 return -EBUSY;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
 218 {
 219         u32                     val;
 220         struct pipe3_dpll_params *dpll_params;
 221
 222         dpll_params = omap_pipe3_get_dpll_params(pipe3);
 223         if (!dpll_params) {
 224                 printf("%s: Invalid DPLL parameters\n", __func__);
 225                 return -EINVAL;
 226         }
 227
 228         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
 229         val &= ~PLL_REGN_MASK;
 230         val |= dpll_params->n << PLL_REGN_SHIFT;
 231         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
 232
 233         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
 234         val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
 235         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 236         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
 237
 238         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
 239         val &= ~PLL_REGM_MASK;
 240         val |= dpll_params->m << PLL_REGM_SHIFT;
 241         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
 242
 243         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);
 244         val &= ~PLL_REGM_F_MASK;
 245         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 246         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);
 247
 248         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);
 249         val &= ~PLL_SD_MASK;
 250         val |= dpll_params->sd << PLL_SD_SHIFT;
 251         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);
 252
 253         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 254
 255         return omap_pipe3_wait_lock(pipe3);
 256 }
 257
 258 static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
 259 {
 260         u32 val, rate;
 261
 262         val = readl(pipe3->power_reg);
 263
 264         rate = get_sys_clk_freq();
 265         rate = rate/1000000;
 266
 267         if (on) {
 268                 val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
 269                          PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
 270                 val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
 271                 writel(val, pipe3->power_reg);
 272
 273                 /* Power up TX before RX for SATA & USB */
 274                 val |= PIPE3_PHY_TX_POWERON;
 275                 writel(val, pipe3->power_reg);
 276
 277                 val |= PIPE3_PHY_RX_POWERON;
 278                 writel(val, pipe3->power_reg);
 279         } else {
 280                 val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
 281                 writel(val, pipe3->power_reg);
 282         }
 283 }
 284
 285 static void ti_pipe3_calibrate(struct omap_pipe3 *phy)
 286 {
 287         u32 val;
 288         struct pipe3_settings *s = &phy->settings;
 289
 290         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
 291         val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
 292         val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
 293         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
 294
 295         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
 296         val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
 297                  MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
 298                  MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
 299         val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
 300                 s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
 301                 s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
 302                 s->dig_lbw << MEM_CDR_LBW_SHIFT |
 303                 s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
 304                 s->dig_stl << MEM_CDR_STL_SHIFT |
 305                 s->dig_thr << MEM_CDR_THR_SHIFT |
 306                 s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
 307                 s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
 308         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
 309
 310         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
 311         val &= ~MEM_DLL_TRIM_SEL_MASK;
 312         val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
 313         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
 314
 315         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
 316         val &= ~MEM_DLL_PHINT_RATE_MASK;
 317         val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
 318         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
 319
 320         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
 321         val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
 322                  MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
 323         val |= s->eq_lev << MEM_EQLEV_SHIFT |
 324                 s->eq_ftc << MEM_EQFTC_SHIFT |
 325                 s->eq_ctl << MEM_EQCTL_SHIFT |
 326                 s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
 327                 s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
 328         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
 329
 330         if (phy->mode == PIPE3_MODE_SATA) {
 331                 val = omap_pipe3_readl(phy->phy_rx,
 332                                        SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
 333                 val &= ~MEM_CDR_LOS_SOURCE_MASK;
 334                 omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
 335                                   val);
 336         }
 337 }
 338
 339 static int pipe3_init(struct phy *phy)
 340 {
 341         int ret;
 342         u32 val;
 343         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 344
 345         /* Program the DPLL only if not locked */
 346         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
 347         if (!(val & PLL_LOCK)) {
 348                 ret = omap_pipe3_dpll_program(pipe3);
 349                 if (ret)
 350                         return ret;
 351
 352                 ti_pipe3_calibrate(pipe3);
 353         } else {
 354                 /* else just bring it out of IDLE mode */
 355                 val = omap_pipe3_readl(pipe3->pll_ctrl_base,
 356                                        PLL_CONFIGURATION2);
 357                 if (val & PLL_IDLE) {
 358                         val &= ~PLL_IDLE;
 359                         omap_pipe3_writel(pipe3->pll_ctrl_base,
 360                                           PLL_CONFIGURATION2, val);
 361                         ret = omap_pipe3_wait_lock(pipe3);
 362                         if (ret)
 363                                 return ret;
 364                 }
 365         }
 366         return 0;
 367 }
 368
 369 static int pipe3_power_on(struct phy *phy)
 370 {
 371         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 372
 373         /* Power up the PHY */
 374         omap_control_pipe3_power(pipe3, 1);
 375
 376         return 0;
 377 }
 378
 379 static int pipe3_power_off(struct phy *phy)
 380 {
 381         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 382
 383         /* Power down the PHY */
 384         omap_control_pipe3_power(pipe3, 0);
 385
 386         return 0;
 387 }
 388
 389 static int pipe3_exit(struct phy *phy)
 390 {
 391         u32 val;
 392         int timeout = PLL_IDLE_TIME;
 393         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 394
 395         pipe3_power_off(phy);
 396
 397         /* Put DPLL in IDLE mode */
 398         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
 399         val |= PLL_IDLE;
 400         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
 401
 402         /* wait for LDO and Oscillator to power down */
 403         do {
 404                 mdelay(1);
 405                 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
 406                 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 407                         break;
 408         } while (--timeout);
 409
 410         if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 411                 pr_err("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
 412                       __func__, val);
 413                 return -EBUSY;
 414         }
 415
 416         if (pipe3->pll_reset_reg) {
 417                 val = readl(pipe3->pll_reset_reg);
 418                 writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
 419                 mdelay(1);
 420                 writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
 421         }
 422
 423         return 0;
 424 }
 425
 426 static void *get_reg(struct udevice *dev, const char *name)
 427 {
 428         struct udevice *syscon;
 429         struct regmap *regmap;
 430         const fdt32_t *cell;
 431         int len, err;
 432         void *base;
 433
 434         err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
 435                                            name, &syscon);
 436         if (err) {
 437                 pr_err("unable to find syscon device for %s (%d)\n",
 438                       name, err);
 439                 return NULL;
 440         }
 441
 442         regmap = syscon_get_regmap(syscon);
 443         if (IS_ERR(regmap)) {
 444                 pr_err("unable to find regmap for %s (%ld)\n",
 445                       name, PTR_ERR(regmap));
 446                 return NULL;
 447         }
 448
 449         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,
 450                            &len);
 451         if (len < 2*sizeof(fdt32_t)) {
 452                 pr_err("offset not available for %s\n", name);
 453                 return NULL;
 454         }
 455
 456         base = regmap_get_range(regmap, 0);
 457         if (!base)
 458                 return NULL;
 459
 460         return fdtdec_get_number(cell + 1, 1) + base;
 461 }
 462
 463 static int pipe3_phy_probe(struct udevice *dev)
 464 {
 465         fdt_addr_t addr;
 466         fdt_size_t sz;
 467         struct omap_pipe3 *pipe3 = dev_get_priv(dev);
 468         struct pipe3_data *data;
 469
 470         /* PHY_RX */
 471         addr = devfdt_get_addr_size_index(dev, 0, &sz);
 472         if (addr == FDT_ADDR_T_NONE) {
 473                 pr_err("missing phy_rx address\n");
 474                 return -EINVAL;
 475         }
 476
 477         pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE);
 478         if (!pipe3->phy_rx) {
 479                 pr_err("unable to remap phy_rx\n");
 480                 return -EINVAL;
 481         }
 482
 483         /* PLLCTRL */
 484         addr = devfdt_get_addr_size_index(dev, 2, &sz);
 485         if (addr == FDT_ADDR_T_NONE) {
 486                 pr_err("missing pll ctrl address\n");
 487                 return -EINVAL;
 488         }
 489
 490         pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
 491         if (!pipe3->pll_ctrl_base) {
 492                 pr_err("unable to remap pll ctrl\n");
 493                 return -EINVAL;
 494         }
 495
 496         pipe3->power_reg = get_reg(dev, "syscon-phy-power");
 497         if (!pipe3->power_reg)
 498                 return -EINVAL;
 499
 500         data = (struct pipe3_data *)dev_get_driver_data(dev);
 501         pipe3->mode = data->mode;
 502         pipe3->dpll_map = data->dpll_map;
 503         pipe3->settings = data->settings;
 504
 505         if (pipe3->mode == PIPE3_MODE_SATA) {
 506                 pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
 507                 if (!pipe3->pll_reset_reg)
 508                         return -EINVAL;
 509         }
 510
 511         return 0;
 512 }
 513
 514 static struct pipe3_dpll_map dpll_map_sata[] = {
 515         {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
 516         {16800000, {625, 6, 4, 7, 0} },         /* 16.8 MHz */
 517         {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
 518         {20000000, {750, 9, 4, 6, 0} },         /* 20 MHz */
 519         {26000000, {750, 12, 4, 6, 0} },        /* 26 MHz */
 520         {38400000, {625, 15, 4, 6, 0} },        /* 38.4 MHz */
 521         { },                                    /* Terminator */
 522 };
 523
 524 static struct pipe3_dpll_map dpll_map_usb[] = {
 525         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
 526         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
 527         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
 528         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
 529         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
 530         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
 531         { },                                    /* Terminator */
 532 };
 533
 534 static struct pipe3_data data_usb = {
 535         .mode = PIPE3_MODE_USBSS,
 536         .dpll_map = dpll_map_usb,
 537         .settings = {
 538         /* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */
 539                 .ana_interface = INTERFACE_MODE_USBSS,
 540                 .ana_losd = 0xa,
 541                 .dig_fastlock = 1,
 542                 .dig_lbw = 3,
 543                 .dig_stepcnt = 0,
 544                 .dig_stl = 0x3,
 545                 .dig_thr = 1,
 546                 .dig_thr_mode = 1,
 547                 .dig_2ndo_sdm_mode = 0,
 548                 .dig_hs_rate = 0,
 549                 .dig_ovrd_hs_rate = 1,
 550                 .dll_trim_sel = 0x2,
 551                 .dll_phint_rate = 0x3,
 552                 .eq_lev = 0,
 553                 .eq_ftc = 0,
 554                 .eq_ctl = 0x9,
 555                 .eq_ovrd_lev = 0,
 556                 .eq_ovrd_ftc = 0,
 557         },
 558 };
 559
 560 static struct pipe3_data data_sata = {
 561         .mode = PIPE3_MODE_SATA,
 562         .dpll_map = dpll_map_sata,
 563         .settings = {
 564         /* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */
 565                 .ana_interface = INTERFACE_MODE_SATA_3P0,
 566                 .ana_losd = 0x5,
 567                 .dig_fastlock = 1,
 568                 .dig_lbw = 3,
 569                 .dig_stepcnt = 0,
 570                 .dig_stl = 0x3,
 571                 .dig_thr = 1,
 572                 .dig_thr_mode = 1,
 573                 .dig_2ndo_sdm_mode = 0,
 574                 .dig_hs_rate = 0,       /* Not in TRM preferred settings */
 575                 .dig_ovrd_hs_rate = 0,  /* Not in TRM preferred settings */
 576                 .dll_trim_sel = 0x1,
 577                 .dll_phint_rate = 0x2,  /* for 1.5 GHz DPLL clock */
 578                 .eq_lev = 0,
 579                 .eq_ftc = 0x1f,
 580                 .eq_ctl = 0,
 581                 .eq_ovrd_lev = 1,
 582                 .eq_ovrd_ftc = 1,
 583         },
 584 };
 585
 586 static const struct udevice_id pipe3_phy_ids[] = {
 587         { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
 588         { .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
 589         { }
 590 };
 591
 592 static struct phy_ops pipe3_phy_ops = {
 593         .init = pipe3_init,
 594         .power_on = pipe3_power_on,
 595         .power_off = pipe3_power_off,
 596         .exit = pipe3_exit,
 597 };
 598
 599 U_BOOT_DRIVER(pipe3_phy) = {
 600         .name   = "pipe3_phy",
 601         .id     = UCLASS_PHY,
 602         .of_match = pipe3_phy_ids,
 603         .ops = &pipe3_phy_ops,
 604         .probe = pipe3_phy_probe,
 605         .priv_auto_alloc_size = sizeof(struct omap_pipe3),
 606 };