drivers/phy/phy-stm32-usbphyc.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <generic-phy.h>
  12 #include <log.h>
  13 #include <reset.h>
  14 #include <syscon.h>
  15 #include <usb.h>
  16 #include <asm/io.h>
  17 #include <dm/device_compat.h>
  18 #include <linux/bitops.h>
  19 #include <power/regulator.h>
  20
  21 /* USBPHYC registers */
  22 #define STM32_USBPHYC_PLL       0x0
  23 #define STM32_USBPHYC_MISC      0x8
  24
  25 /* STM32_USBPHYC_PLL bit fields */
  26 #define PLLNDIV                 GENMASK(6, 0)
  27 #define PLLNDIV_SHIFT           0
  28 #define PLLFRACIN               GENMASK(25, 10)
  29 #define PLLFRACIN_SHIFT         10
  30 #define PLLEN                   BIT(26)
  31 #define PLLSTRB                 BIT(27)
  32 #define PLLSTRBYP               BIT(28)
  33 #define PLLFRACCTL              BIT(29)
  34 #define PLLDITHEN0              BIT(30)
  35 #define PLLDITHEN1              BIT(31)
  36
  37 /* STM32_USBPHYC_MISC bit fields */
  38 #define SWITHOST                BIT(0)
  39
  40 #define MAX_PHYS                2
  41
  42 /* max 100 us for PLL lock and 100 us for PHY init */
  43 #define PLL_INIT_TIME_US        200
  44 #define PLL_PWR_DOWN_TIME_US    5
  45 #define PLL_FVCO                2880     /* in MHz */
  46 #define PLL_INFF_MIN_RATE       19200000 /* in Hz */
  47 #define PLL_INFF_MAX_RATE       38400000 /* in Hz */
  48
  49 struct pll_params {
  50         u8 ndiv;
  51         u16 frac;
  52 };
  53
  54 struct stm32_usbphyc {
  55         fdt_addr_t base;
  56         struct clk clk;
  57         struct udevice *vdda1v1;
  58         struct udevice *vdda1v8;
  59         struct stm32_usbphyc_phy {
  60                 struct udevice *vdd;
  61                 bool init;
  62                 bool powered;
  63         } phys[MAX_PHYS];
  64 };
  65
  66 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
  67                                          struct pll_params *pll_params)
  68 {
  69         unsigned long long fvco, ndiv, frac;
  70
  71         /*
  72          *    | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
  73          *    | FVCO = 2880MHz
  74          *    | NDIV = integer part of input bits to set the LDF
  75          *    | FRACT = fractional part of input bits to set the LDF
  76          *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
  77          *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
  78          * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
  79          */
  80         fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
  81
  82         ndiv = fvco;
  83         do_div(ndiv, (clk_rate * 2));
  84         pll_params->ndiv = (u8)ndiv;
  85
  86         frac = fvco * (1 << 16);
  87         do_div(frac, (clk_rate * 2));
  88         frac = frac - (ndiv * (1 << 16));
  89         pll_params->frac = (u16)frac;
  90 }
  91
  92 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
  93 {
  94         struct pll_params pll_params;
  95         u32 clk_rate = clk_get_rate(&usbphyc->clk);
  96         u32 usbphyc_pll;
  97
  98         if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
  99                 pr_debug("%s: input clk freq (%dHz) out of range\n",
 100                          __func__, clk_rate);
 101                 return -EINVAL;
 102         }
 103
 104         stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
 105
 106         usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
 107         usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
 108
 109         if (pll_params.frac) {
 110                 usbphyc_pll |= PLLFRACCTL;
 111                 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
 112                                  & PLLFRACIN);
 113         }
 114
 115         writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
 116
 117         pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
 118                  clk_rate, pll_params.ndiv, pll_params.frac);
 119
 120         return 0;
 121 }
 122
 123 static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
 124 {
 125         int i;
 126
 127         for (i = 0; i < MAX_PHYS; i++) {
 128                 if (usbphyc->phys[i].init)
 129                         return true;
 130         }
 131
 132         return false;
 133 }
 134
 135 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
 136 {
 137         int i;
 138
 139         for (i = 0; i < MAX_PHYS; i++) {
 140                 if (usbphyc->phys[i].powered)
 141                         return true;
 142         }
 143
 144         return false;
 145 }
 146
 147 static int stm32_usbphyc_phy_init(struct phy *phy)
 148 {
 149         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 150         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 151         bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
 152                      true : false;
 153         int ret;
 154
 155         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 156         /* Check if one phy port has already configured the pll */
 157         if (pllen && stm32_usbphyc_is_init(usbphyc))
 158                 goto initialized;
 159
 160         if (usbphyc->vdda1v1) {
 161                 ret = regulator_set_enable(usbphyc->vdda1v1, true);
 162                 if (ret)
 163                         return ret;
 164         }
 165
 166         if (usbphyc->vdda1v8) {
 167                 ret = regulator_set_enable(usbphyc->vdda1v8, true);
 168                 if (ret)
 169                         return ret;
 170         }
 171
 172         if (pllen) {
 173                 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 174                 udelay(PLL_PWR_DOWN_TIME_US);
 175         }
 176
 177         ret = stm32_usbphyc_pll_init(usbphyc);
 178         if (ret)
 179                 return ret;
 180
 181         setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 182
 183         /* We must wait PLL_INIT_TIME_US before using PHY */
 184         udelay(PLL_INIT_TIME_US);
 185
 186         if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
 187                 return -EIO;
 188
 189 initialized:
 190         usbphyc_phy->init = true;
 191
 192         return 0;
 193 }
 194
 195 static int stm32_usbphyc_phy_exit(struct phy *phy)
 196 {
 197         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 198         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 199         int ret;
 200
 201         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 202         usbphyc_phy->init = false;
 203
 204         /* Check if other phy port requires pllen */
 205         if (stm32_usbphyc_is_init(usbphyc))
 206                 return 0;
 207
 208         clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 209
 210         /*
 211          * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
 212          * bit is still clear
 213          */
 214         udelay(PLL_PWR_DOWN_TIME_US);
 215
 216         if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
 217                 return -EIO;
 218
 219         if (usbphyc->vdda1v1) {
 220                 ret = regulator_set_enable(usbphyc->vdda1v1, false);
 221                 if (ret)
 222                         return ret;
 223         }
 224
 225         if (usbphyc->vdda1v8) {
 226                 ret = regulator_set_enable(usbphyc->vdda1v8, false);
 227                 if (ret)
 228                         return ret;
 229         }
 230
 231         return 0;
 232 }
 233
 234 static int stm32_usbphyc_phy_power_on(struct phy *phy)
 235 {
 236         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 237         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 238         int ret;
 239
 240         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 241         if (usbphyc_phy->vdd) {
 242                 ret = regulator_set_enable(usbphyc_phy->vdd, true);
 243                 if (ret)
 244                         return ret;
 245         }
 246
 247         usbphyc_phy->powered = true;
 248
 249         return 0;
 250 }
 251
 252 static int stm32_usbphyc_phy_power_off(struct phy *phy)
 253 {
 254         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 255         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 256         int ret;
 257
 258         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 259         usbphyc_phy->powered = false;
 260
 261         if (stm32_usbphyc_is_powered(usbphyc))
 262                 return 0;
 263
 264         if (usbphyc_phy->vdd) {
 265                 ret = regulator_set_enable(usbphyc_phy->vdd, false);
 266                 if (ret)
 267                         return ret;
 268         }
 269
 270         return 0;
 271 }
 272
 273 static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node,
 274                                        char *supply_name,
 275                                        struct udevice **regulator)
 276 {
 277         struct ofnode_phandle_args regulator_phandle;
 278         int ret;
 279
 280         ret = ofnode_parse_phandle_with_args(node, supply_name,
 281                                              NULL, 0, 0,
 282                                              &regulator_phandle);
 283         if (ret) {
 284                 dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret);
 285                 return ret;
 286         }
 287
 288         ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
 289                                           regulator_phandle.node,
 290                                           regulator);
 291
 292         if (ret) {
 293                 dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret);
 294                 return ret;
 295         }
 296
 297         return 0;
 298 }
 299
 300 static int stm32_usbphyc_of_xlate(struct phy *phy,
 301                                   struct ofnode_phandle_args *args)
 302 {
 303         if (args->args_count < 1)
 304                 return -ENODEV;
 305
 306         if (args->args[0] >= MAX_PHYS)
 307                 return -ENODEV;
 308
 309         phy->id = args->args[0];
 310
 311         if ((phy->id == 0 && args->args_count != 1) ||
 312             (phy->id == 1 && args->args_count != 2)) {
 313                 dev_err(dev, "invalid number of cells for phy port%ld\n",
 314                         phy->id);
 315                 return -EINVAL;
 316         }
 317
 318         return 0;
 319 }
 320
 321 static const struct phy_ops stm32_usbphyc_phy_ops = {
 322         .init = stm32_usbphyc_phy_init,
 323         .exit = stm32_usbphyc_phy_exit,
 324         .power_on = stm32_usbphyc_phy_power_on,
 325         .power_off = stm32_usbphyc_phy_power_off,
 326         .of_xlate = stm32_usbphyc_of_xlate,
 327 };
 328
 329 static int stm32_usbphyc_probe(struct udevice *dev)
 330 {
 331         struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
 332         struct reset_ctl reset;
 333         ofnode node;
 334         int i, ret;
 335
 336         usbphyc->base = dev_read_addr(dev);
 337         if (usbphyc->base == FDT_ADDR_T_NONE)
 338                 return -EINVAL;
 339
 340         /* Enable clock */
 341         ret = clk_get_by_index(dev, 0, &usbphyc->clk);
 342         if (ret)
 343                 return ret;
 344
 345         ret = clk_enable(&usbphyc->clk);
 346         if (ret)
 347                 return ret;
 348
 349         /* Reset */
 350         ret = reset_get_by_index(dev, 0, &reset);
 351         if (!ret) {
 352                 reset_assert(&reset);
 353                 udelay(2);
 354                 reset_deassert(&reset);
 355         }
 356
 357         /* get usbphyc regulator */
 358         ret = device_get_supply_regulator(dev, "vdda1v1-supply",
 359                                           &usbphyc->vdda1v1);
 360         if (ret) {
 361                 dev_err(dev, "Can't get vdda1v1-supply regulator\n");
 362                 return ret;
 363         }
 364
 365         ret = device_get_supply_regulator(dev, "vdda1v8-supply",
 366                                           &usbphyc->vdda1v8);
 367         if (ret) {
 368                 dev_err(dev, "Can't get vdda1v8-supply regulator\n");
 369                 return ret;
 370         }
 371
 372         /*
 373          * parse all PHY subnodes in order to populate regulator associated
 374          * to each PHY port
 375          */
 376         node = dev_read_first_subnode(dev);
 377         for (i = 0; i < MAX_PHYS; i++) {
 378                 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
 379
 380                 usbphyc_phy->init = false;
 381                 usbphyc_phy->powered = false;
 382                 ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
 383                                                   &usbphyc_phy->vdd);
 384                 if (ret)
 385                         return ret;
 386
 387                 node = dev_read_next_subnode(node);
 388         }
 389
 390         /* Check if second port has to be used for host controller */
 391         if (dev_read_bool(dev, "st,port2-switch-to-host"))
 392                 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
 393
 394         return 0;
 395 }
 396
 397 static const struct udevice_id stm32_usbphyc_of_match[] = {
 398         { .compatible = "st,stm32mp1-usbphyc", },
 399         { },
 400 };
 401
 402 U_BOOT_DRIVER(stm32_usb_phyc) = {
 403         .name = "stm32-usbphyc",
 404         .id = UCLASS_PHY,
 405         .of_match = stm32_usbphyc_of_match,
 406         .ops = &stm32_usbphyc_phy_ops,
 407         .probe = stm32_usbphyc_probe,
 408         .priv_auto_alloc_size = sizeof(struct stm32_usbphyc),
 409 };