drivers/phy/phy-mtk-tphy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 - 2019 MediaTek Inc.
   4  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
   5  *         Ryder Lee <ryder.lee@mediatek.com>
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <generic-phy.h>
  12 #include <malloc.h>
  13 #include <mapmem.h>
  14 #include <asm/io.h>
  15 #include <dm/device_compat.h>
  16 #include <dm/devres.h>
  17 #include <linux/delay.h>
  18
  19 #include <dt-bindings/phy/phy.h>
  20
  21 /* version V1 sub-banks offset base address */
  22 /* banks shared by multiple phys */
  23 #define SSUSB_SIFSLV_V1_SPLLC           0x000   /* shared by u3 phys */
  24 #define SSUSB_SIFSLV_V1_U2FREQ          0x100   /* shared by u2 phys */
  25 #define SSUSB_SIFSLV_V1_CHIP            0x300   /* shared by u3 phys */
  26 /* u2 phy bank */
  27 #define SSUSB_SIFSLV_V1_U2PHY_COM       0x000
  28 /* u3/pcie/sata phy banks */
  29 #define SSUSB_SIFSLV_V1_U3PHYD          0x000
  30 #define SSUSB_SIFSLV_V1_U3PHYA          0x200
  31
  32 /* version V2 sub-banks offset base address */
  33 /* u2 phy banks */
  34 #define SSUSB_SIFSLV_V2_MISC            0x000
  35 #define SSUSB_SIFSLV_V2_U2FREQ          0x100
  36 #define SSUSB_SIFSLV_V2_U2PHY_COM       0x300
  37 /* u3/pcie/sata phy banks */
  38 #define SSUSB_SIFSLV_V2_SPLLC           0x000
  39 #define SSUSB_SIFSLV_V2_CHIP            0x100
  40 #define SSUSB_SIFSLV_V2_U3PHYD          0x200
  41 #define SSUSB_SIFSLV_V2_U3PHYA          0x400
  42
  43 #define U3P_USBPHYACR0                  0x000
  44 #define PA0_RG_U2PLL_FORCE_ON           BIT(15)
  45 #define PA0_RG_USB20_INTR_EN            BIT(5)
  46
  47 #define U3P_USBPHYACR5                  0x014
  48 #define PA5_RG_U2_HSTX_SRCAL_EN         BIT(15)
  49 #define PA5_RG_U2_HSTX_SRCTRL           GENMASK(14, 12)
  50 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x)    ((0x7 & (x)) << 12)
  51 #define PA5_RG_U2_HS_100U_U3_EN         BIT(11)
  52
  53 #define U3P_USBPHYACR6                  0x018
  54 #define PA6_RG_U2_BC11_SW_EN            BIT(23)
  55 #define PA6_RG_U2_OTG_VBUSCMP_EN        BIT(20)
  56 #define PA6_RG_U2_SQTH                  GENMASK(3, 0)
  57 #define PA6_RG_U2_SQTH_VAL(x)           (0xf & (x))
  58
  59 #define U3P_U2PHYACR4                   0x020
  60 #define P2C_RG_USB20_GPIO_CTL           BIT(9)
  61 #define P2C_USB20_GPIO_MODE             BIT(8)
  62 #define P2C_U2_GPIO_CTR_MSK     \
  63                 (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
  64
  65 #define U3P_U2PHYDTM0                   0x068
  66 #define P2C_FORCE_UART_EN               BIT(26)
  67 #define P2C_FORCE_DATAIN                BIT(23)
  68 #define P2C_FORCE_DM_PULLDOWN           BIT(21)
  69 #define P2C_FORCE_DP_PULLDOWN           BIT(20)
  70 #define P2C_FORCE_XCVRSEL               BIT(19)
  71 #define P2C_FORCE_SUSPENDM              BIT(18)
  72 #define P2C_FORCE_TERMSEL               BIT(17)
  73 #define P2C_RG_DATAIN                   GENMASK(13, 10)
  74 #define P2C_RG_DATAIN_VAL(x)            ((0xf & (x)) << 10)
  75 #define P2C_RG_DMPULLDOWN               BIT(7)
  76 #define P2C_RG_DPPULLDOWN               BIT(6)
  77 #define P2C_RG_XCVRSEL                  GENMASK(5, 4)
  78 #define P2C_RG_XCVRSEL_VAL(x)           ((0x3 & (x)) << 4)
  79 #define P2C_RG_SUSPENDM                 BIT(3)
  80 #define P2C_RG_TERMSEL                  BIT(2)
  81 #define P2C_DTM0_PART_MASK      \
  82                 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
  83                 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
  84                 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
  85                 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
  86
  87 #define U3P_U2PHYDTM1                   0x06C
  88 #define P2C_RG_UART_EN                  BIT(16)
  89 #define P2C_FORCE_IDDIG                 BIT(9)
  90 #define P2C_RG_VBUSVALID                BIT(5)
  91 #define P2C_RG_SESSEND                  BIT(4)
  92 #define P2C_RG_AVALID                   BIT(2)
  93 #define P2C_RG_IDDIG                    BIT(1)
  94
  95 #define U3P_U3_CHIP_GPIO_CTLD           0x0c
  96 #define P3C_REG_IP_SW_RST               BIT(31)
  97 #define P3C_MCU_BUS_CK_GATE_EN          BIT(30)
  98 #define P3C_FORCE_IP_SW_RST             BIT(29)
  99
 100 #define U3P_U3_CHIP_GPIO_CTLE           0x10
 101 #define P3C_RG_SWRST_U3_PHYD            BIT(25)
 102 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN   BIT(24)
 103
 104 #define U3P_U3_PHYA_REG0                0x000
 105 #define P3A_RG_CLKDRV_OFF               GENMASK(3, 2)
 106 #define P3A_RG_CLKDRV_OFF_VAL(x)        ((0x3 & (x)) << 2)
 107
 108 #define U3P_U3_PHYA_REG1                0x004
 109 #define P3A_RG_CLKDRV_AMP               GENMASK(31, 29)
 110 #define P3A_RG_CLKDRV_AMP_VAL(x)        ((0x7 & (x)) << 29)
 111
 112 #define U3P_U3_PHYA_REG6                0x018
 113 #define P3A_RG_TX_EIDLE_CM              GENMASK(31, 28)
 114 #define P3A_RG_TX_EIDLE_CM_VAL(x)       ((0xf & (x)) << 28)
 115
 116 #define U3P_U3_PHYA_REG9                0x024
 117 #define P3A_RG_RX_DAC_MUX               GENMASK(5, 1)
 118 #define P3A_RG_RX_DAC_MUX_VAL(x)        ((0x1f & (x)) << 1)
 119
 120 #define U3P_U3_PHYA_DA_REG0             0x100
 121 #define P3A_RG_XTAL_EXT_PE2H            GENMASK(17, 16)
 122 #define P3A_RG_XTAL_EXT_PE2H_VAL(x)     ((0x3 & (x)) << 16)
 123 #define P3A_RG_XTAL_EXT_PE1H            GENMASK(13, 12)
 124 #define P3A_RG_XTAL_EXT_PE1H_VAL(x)     ((0x3 & (x)) << 12)
 125 #define P3A_RG_XTAL_EXT_EN_U3           GENMASK(11, 10)
 126 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)    ((0x3 & (x)) << 10)
 127
 128 #define U3P_U3_PHYA_DA_REG4             0x108
 129 #define P3A_RG_PLL_DIVEN_PE2H           GENMASK(21, 19)
 130 #define P3A_RG_PLL_BC_PE2H              GENMASK(7, 6)
 131 #define P3A_RG_PLL_BC_PE2H_VAL(x)       ((0x3 & (x)) << 6)
 132
 133 #define U3P_U3_PHYA_DA_REG5             0x10c
 134 #define P3A_RG_PLL_BR_PE2H              GENMASK(29, 28)
 135 #define P3A_RG_PLL_BR_PE2H_VAL(x)       ((0x3 & (x)) << 28)
 136 #define P3A_RG_PLL_IC_PE2H              GENMASK(15, 12)
 137 #define P3A_RG_PLL_IC_PE2H_VAL(x)       ((0xf & (x)) << 12)
 138
 139 #define U3P_U3_PHYA_DA_REG6             0x110
 140 #define P3A_RG_PLL_IR_PE2H              GENMASK(19, 16)
 141 #define P3A_RG_PLL_IR_PE2H_VAL(x)       ((0xf & (x)) << 16)
 142
 143 #define U3P_U3_PHYA_DA_REG7             0x114
 144 #define P3A_RG_PLL_BP_PE2H              GENMASK(19, 16)
 145 #define P3A_RG_PLL_BP_PE2H_VAL(x)       ((0xf & (x)) << 16)
 146
 147 #define U3P_U3_PHYA_DA_REG20            0x13c
 148 #define P3A_RG_PLL_DELTA1_PE2H          GENMASK(31, 16)
 149 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x)   ((0xffff & (x)) << 16)
 150
 151 #define U3P_U3_PHYA_DA_REG25            0x148
 152 #define P3A_RG_PLL_DELTA_PE2H           GENMASK(15, 0)
 153 #define P3A_RG_PLL_DELTA_PE2H_VAL(x)    (0xffff & (x))
 154
 155 #define U3P_U3_PHYD_LFPS1               0x00c
 156 #define P3D_RG_FWAKE_TH                 GENMASK(21, 16)
 157 #define P3D_RG_FWAKE_TH_VAL(x)          ((0x3f & (x)) << 16)
 158
 159 #define U3P_U3_PHYD_CDR1                0x05c
 160 #define P3D_RG_CDR_BIR_LTD1             GENMASK(28, 24)
 161 #define P3D_RG_CDR_BIR_LTD1_VAL(x)      ((0x1f & (x)) << 24)
 162 #define P3D_RG_CDR_BIR_LTD0             GENMASK(12, 8)
 163 #define P3D_RG_CDR_BIR_LTD0_VAL(x)      ((0x1f & (x)) << 8)
 164
 165 #define U3P_U3_PHYD_RXDET1              0x128
 166 #define P3D_RG_RXDET_STB2_SET           GENMASK(17, 9)
 167 #define P3D_RG_RXDET_STB2_SET_VAL(x)    ((0x1ff & (x)) << 9)
 168
 169 #define U3P_U3_PHYD_RXDET2              0x12c
 170 #define P3D_RG_RXDET_STB2_SET_P3        GENMASK(8, 0)
 171 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
 172
 173 #define U3P_SPLLC_XTALCTL3              0x018
 174 #define XC3_RG_U3_XTAL_RX_PWD           BIT(9)
 175 #define XC3_RG_U3_FRC_XTAL_RX_PWD       BIT(8)
 176
 177 enum mtk_phy_version {
 178         MTK_TPHY_V1 = 1,
 179         MTK_TPHY_V2,
 180 };
 181
 182 struct u2phy_banks {
 183         void __iomem *misc;
 184         void __iomem *fmreg;
 185         void __iomem *com;
 186 };
 187
 188 struct u3phy_banks {
 189         void __iomem *spllc;
 190         void __iomem *chip;
 191         void __iomem *phyd; /* include u3phyd_bank2 */
 192         void __iomem *phya; /* include u3phya_da */
 193 };
 194
 195 struct mtk_phy_instance {
 196         void __iomem *port_base;
 197         const struct device_node *np;
 198         union {
 199                 struct u2phy_banks u2_banks;
 200                 struct u3phy_banks u3_banks;
 201         };
 202
 203         struct clk ref_clk;     /* reference clock of (digital) phy */
 204         struct clk da_ref_clk;  /* reference clock of analog phy */
 205         u32 index;
 206         u32 type;
 207 };
 208
 209 struct mtk_tphy {
 210         struct udevice *dev;
 211         void __iomem *sif_base;
 212         enum mtk_phy_version version;
 213         struct mtk_phy_instance **phys;
 214         int nphys;
 215 };
 216
 217 static void u2_phy_instance_init(struct mtk_tphy *tphy,
 218                                  struct mtk_phy_instance *instance)
 219 {
 220         struct u2phy_banks *u2_banks = &instance->u2_banks;
 221
 222         /* switch to USB function, and enable usb pll */
 223         clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
 224                         P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM,
 225                         P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0));
 226
 227         clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
 228         setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
 229
 230         /* disable switch 100uA current to SSUSB */
 231         clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
 232
 233         clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
 234
 235         /* DP/DM BC1.1 path Disable */
 236         clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
 237                         PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH,
 238                         PA6_RG_U2_SQTH_VAL(2));
 239
 240         /* set HS slew rate */
 241         clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
 242                         PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
 243
 244         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 245 }
 246
 247 static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
 248                                      struct mtk_phy_instance *instance)
 249 {
 250         struct u2phy_banks *u2_banks = &instance->u2_banks;
 251
 252         clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
 253                      P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
 254
 255         /* OTG Enable */
 256         setbits_le32(u2_banks->com + U3P_USBPHYACR6,
 257                      PA6_RG_U2_OTG_VBUSCMP_EN);
 258
 259         clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
 260                         P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
 261
 262         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 263 }
 264
 265 static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
 266                                       struct mtk_phy_instance *instance)
 267 {
 268         struct u2phy_banks *u2_banks = &instance->u2_banks;
 269
 270         clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
 271                      P2C_RG_XCVRSEL | P2C_RG_DATAIN);
 272
 273         /* OTG Disable */
 274         clrbits_le32(u2_banks->com + U3P_USBPHYACR6,
 275                      PA6_RG_U2_OTG_VBUSCMP_EN);
 276
 277         clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
 278                         P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND);
 279
 280         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 281 }
 282
 283 static void u3_phy_instance_init(struct mtk_tphy *tphy,
 284                                  struct mtk_phy_instance *instance)
 285 {
 286         struct u3phy_banks *u3_banks = &instance->u3_banks;
 287
 288         /* gating PCIe Analog XTAL clock */
 289         setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
 290                      XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
 291
 292         /* gating XSQ */
 293         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
 294                         P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
 295
 296         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
 297                         P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
 298
 299         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6,
 300                         P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
 301
 302         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1,
 303                         P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
 304                         P3D_RG_CDR_BIR_LTD0_VAL(0xc) |
 305                         P3D_RG_CDR_BIR_LTD1_VAL(0x3));
 306
 307         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
 308                         P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));
 309
 310         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
 311                         P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
 312
 313         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
 314                         P3D_RG_RXDET_STB2_SET_P3,
 315                         P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
 316
 317         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 318 }
 319
 320 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
 321                                    struct mtk_phy_instance *instance)
 322 {
 323         struct u3phy_banks *u3_banks = &instance->u3_banks;
 324
 325         if (tphy->version != MTK_TPHY_V1)
 326                 return;
 327
 328         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
 329                         P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
 330                         P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
 331                         P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
 332
 333         /* ref clk drive */
 334         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
 335                         P3A_RG_CLKDRV_AMP_VAL(0x4));
 336         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
 337                         P3A_RG_CLKDRV_OFF_VAL(0x1));
 338
 339         /* SSC delta -5000ppm */
 340         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
 341                         P3A_RG_PLL_DELTA1_PE2H,
 342                         P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
 343
 344         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
 345                         P3A_RG_PLL_DELTA_PE2H,
 346                         P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
 347
 348         /* change pll BW 0.6M */
 349         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
 350                         P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
 351                         P3A_RG_PLL_BR_PE2H_VAL(0x1) |
 352                         P3A_RG_PLL_IC_PE2H_VAL(0x1));
 353         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
 354                         P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
 355                         P3A_RG_PLL_BC_PE2H_VAL(0x3));
 356
 357         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
 358                         P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
 359         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
 360                         P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));
 361
 362         /* Tx Detect Rx Timing: 10us -> 5us */
 363         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
 364                         P3D_RG_RXDET_STB2_SET,
 365                         P3D_RG_RXDET_STB2_SET_VAL(0x10));
 366         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
 367                         P3D_RG_RXDET_STB2_SET_P3,
 368                         P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
 369
 370         /* wait for PCIe subsys register to active */
 371         udelay(3000);
 372 }
 373
 374 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
 375                                        struct mtk_phy_instance *instance)
 376 {
 377         struct u3phy_banks *bank = &instance->u3_banks;
 378
 379         clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 380                      P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 381         clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 382                      P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 383 }
 384
 385 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
 386                                         struct mtk_phy_instance *instance)
 387
 388 {
 389         struct u3phy_banks *bank = &instance->u3_banks;
 390
 391         setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 392                      P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 393         setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 394                      P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 395 }
 396
 397 static void phy_v1_banks_init(struct mtk_tphy *tphy,
 398                               struct mtk_phy_instance *instance)
 399 {
 400         struct u2phy_banks *u2_banks = &instance->u2_banks;
 401         struct u3phy_banks *u3_banks = &instance->u3_banks;
 402
 403         switch (instance->type) {
 404         case PHY_TYPE_USB2:
 405                 u2_banks->misc = NULL;
 406                 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
 407                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
 408                 break;
 409         case PHY_TYPE_USB3:
 410         case PHY_TYPE_PCIE:
 411                 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
 412                 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
 413                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 414                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
 415                 break;
 416         default:
 417                 dev_err(tphy->dev, "incompatible PHY type\n");
 418                 return;
 419         }
 420 }
 421
 422 static void phy_v2_banks_init(struct mtk_tphy *tphy,
 423                               struct mtk_phy_instance *instance)
 424 {
 425         struct u2phy_banks *u2_banks = &instance->u2_banks;
 426         struct u3phy_banks *u3_banks = &instance->u3_banks;
 427
 428         switch (instance->type) {
 429         case PHY_TYPE_USB2:
 430                 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
 431                 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
 432                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
 433                 break;
 434         case PHY_TYPE_USB3:
 435         case PHY_TYPE_PCIE:
 436                 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
 437                 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
 438                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
 439                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
 440                 break;
 441         default:
 442                 dev_err(tphy->dev, "incompatible PHY type\n");
 443                 return;
 444         }
 445 }
 446
 447 static int mtk_phy_init(struct phy *phy)
 448 {
 449         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 450         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 451         int ret;
 452
 453         ret = clk_enable(&instance->ref_clk);
 454         if (ret < 0) {
 455                 dev_err(tphy->dev, "failed to enable ref_clk\n");
 456                 return ret;
 457         }
 458
 459         ret = clk_enable(&instance->da_ref_clk);
 460         if (ret < 0) {
 461                 dev_err(tphy->dev, "failed to enable da_ref_clk %d\n", ret);
 462                 clk_disable(&instance->ref_clk);
 463                 return ret;
 464         }
 465
 466         switch (instance->type) {
 467         case PHY_TYPE_USB2:
 468                 u2_phy_instance_init(tphy, instance);
 469                 break;
 470         case PHY_TYPE_USB3:
 471                 u3_phy_instance_init(tphy, instance);
 472                 break;
 473         case PHY_TYPE_PCIE:
 474                 pcie_phy_instance_init(tphy, instance);
 475                 break;
 476         default:
 477                 dev_err(tphy->dev, "incompatible PHY type\n");
 478                 return -EINVAL;
 479         }
 480
 481         return 0;
 482 }
 483
 484 static int mtk_phy_power_on(struct phy *phy)
 485 {
 486         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 487         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 488
 489         if (instance->type == PHY_TYPE_USB2)
 490                 u2_phy_instance_power_on(tphy, instance);
 491         else if (instance->type == PHY_TYPE_PCIE)
 492                 pcie_phy_instance_power_on(tphy, instance);
 493
 494         return 0;
 495 }
 496
 497 static int mtk_phy_power_off(struct phy *phy)
 498 {
 499         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 500         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 501
 502         if (instance->type == PHY_TYPE_USB2)
 503                 u2_phy_instance_power_off(tphy, instance);
 504         else if (instance->type == PHY_TYPE_PCIE)
 505                 pcie_phy_instance_power_off(tphy, instance);
 506
 507         return 0;
 508 }
 509
 510 static int mtk_phy_exit(struct phy *phy)
 511 {
 512         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 513         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 514
 515         clk_disable(&instance->da_ref_clk);
 516         clk_disable(&instance->ref_clk);
 517
 518         return 0;
 519 }
 520
 521 static int mtk_phy_xlate(struct phy *phy,
 522                          struct ofnode_phandle_args *args)
 523 {
 524         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 525         struct mtk_phy_instance *instance = NULL;
 526         const struct device_node *phy_np = ofnode_to_np(args->node);
 527         u32 index;
 528
 529         if (!phy_np) {
 530                 dev_err(phy->dev, "null pointer phy node\n");
 531                 return -EINVAL;
 532         }
 533
 534         if (args->args_count < 1) {
 535                 dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
 536                 return -EINVAL;
 537         }
 538
 539         for (index = 0; index < tphy->nphys; index++)
 540                 if (phy_np == tphy->phys[index]->np) {
 541                         instance = tphy->phys[index];
 542                         break;
 543                 }
 544
 545         if (!instance) {
 546                 dev_err(phy->dev, "failed to find appropriate phy\n");
 547                 return -EINVAL;
 548         }
 549
 550         phy->id = index;
 551         instance->type = args->args[1];
 552         if (!(instance->type == PHY_TYPE_USB2 ||
 553               instance->type == PHY_TYPE_USB3 ||
 554               instance->type == PHY_TYPE_PCIE)) {
 555                 dev_err(phy->dev, "unsupported device type\n");
 556                 return -EINVAL;
 557         }
 558
 559         if (tphy->version == MTK_TPHY_V1) {
 560                 phy_v1_banks_init(tphy, instance);
 561         } else if (tphy->version == MTK_TPHY_V2) {
 562                 phy_v2_banks_init(tphy, instance);
 563         } else {
 564                 dev_err(phy->dev, "phy version is not supported\n");
 565                 return -EINVAL;
 566         }
 567
 568         return 0;
 569 }
 570
 571 static const struct phy_ops mtk_tphy_ops = {
 572         .init           = mtk_phy_init,
 573         .exit           = mtk_phy_exit,
 574         .power_on       = mtk_phy_power_on,
 575         .power_off      = mtk_phy_power_off,
 576         .of_xlate       = mtk_phy_xlate,
 577 };
 578
 579 static int mtk_tphy_probe(struct udevice *dev)
 580 {
 581         struct mtk_tphy *tphy = dev_get_priv(dev);
 582         ofnode subnode;
 583         int index = 0;
 584
 585         tphy->nphys = dev_get_child_count(dev);
 586
 587         tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
 588                                   GFP_KERNEL);
 589         if (!tphy->phys)
 590                 return -ENOMEM;
 591
 592         tphy->dev = dev;
 593         tphy->version = dev_get_driver_data(dev);
 594
 595         /* v1 has shared banks */
 596         if (tphy->version == MTK_TPHY_V1) {
 597                 tphy->sif_base = dev_read_addr_ptr(dev);
 598                 if (!tphy->sif_base)
 599                         return -ENOENT;
 600         }
 601
 602         dev_for_each_subnode(subnode, dev) {
 603                 struct mtk_phy_instance *instance;
 604                 fdt_addr_t addr;
 605                 int err;
 606
 607                 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
 608                 if (!instance)
 609                         return -ENOMEM;
 610
 611                 addr = ofnode_get_addr(subnode);
 612                 if (addr == FDT_ADDR_T_NONE)
 613                         return -ENOMEM;
 614
 615                 instance->port_base = map_sysmem(addr, 0);
 616                 instance->index = index;
 617                 instance->np = ofnode_to_np(subnode);
 618                 tphy->phys[index] = instance;
 619                 index++;
 620
 621                 err = clk_get_optional_nodev(subnode, "ref",
 622                                              &instance->ref_clk);
 623                 if (err)
 624                         return err;
 625
 626                 err = clk_get_optional_nodev(subnode, "da_ref",
 627                                              &instance->da_ref_clk);
 628                 if (err)
 629                         return err;
 630         }
 631
 632         return 0;
 633 }
 634
 635 static const struct udevice_id mtk_tphy_id_table[] = {
 636         { .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, },
 637         { .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, },
 638         { }
 639 };
 640
 641 U_BOOT_DRIVER(mtk_tphy) = {
 642         .name           = "mtk-tphy",
 643         .id             = UCLASS_PHY,
 644         .of_match       = mtk_tphy_id_table,
 645         .ops            = &mtk_tphy_ops,
 646         .probe          = mtk_tphy_probe,
 647         .priv_auto_alloc_size = sizeof(struct mtk_tphy),
 648 };