drivers/phy/mt76x8-usb-phy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 Stefan Roese <sr@denx.de>
   4  *
   5  * Derived from linux/drivers/phy/ralink/phy-ralink-usb.c
   6  *     Copyright (C) 2017 John Crispin <john@phrozen.org>
   7  */
   8
   9 #include <clk.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <generic-phy.h>
  13 #include <log.h>
  14 #include <reset.h>
  15 #include <asm/io.h>
  16 #include <linux/bitops.h>
  17 #include <linux/delay.h>
  18
  19 #define OFS_U2_PHY_AC0                  0x800
  20 #define USBPLL_FBDIV_S                  16
  21 #define USBPLL_FBDIV_M                  GENMASK(22, 16)
  22 #define BG_TRIM_S                       8
  23 #define BG_TRIM_M                       GENMASK(11, 8)
  24 #define BG_RBSEL_S                      6
  25 #define BG_RBSEL_M                      GENMASK(7, 6)
  26 #define BG_RASEL_S                      4
  27 #define BG_RASEL_M                      GENMASK(5, 4)
  28 #define BGR_DIV_S                       2
  29 #define BGR_DIV_M                       GENMASK(3, 2)
  30 #define CHP_EN                          BIT(1)
  31
  32 #define OFS_U2_PHY_AC1                  0x804
  33 #define VRT_VREF_SEL_S                  28
  34 #define VRT_VREF_SEL_M                  GENMASK(30, 28)
  35 #define TERM_VREF_SEL_S                 24
  36 #define TERM_VREF_SEL_M                 GENMASK(26, 24)
  37 #define USBPLL_RSVD                     BIT(4)
  38 #define USBPLL_ACCEN                    BIT(3)
  39 #define USBPLL_LF                       BIT(2)
  40
  41 #define OFS_U2_PHY_AC2                  0x808
  42
  43 #define OFS_U2_PHY_ACR0                 0x810
  44 #define HSTX_SRCAL_EN                   BIT(23)
  45 #define HSTX_SRCTRL_S                   16
  46 #define HSTX_SRCTRL_M                   GENMASK(18, 16)
  47
  48 #define OFS_U2_PHY_ACR3                 0x81C
  49 #define HSTX_DBIST_S                    28
  50 #define HSTX_DBIST_M                    GENMASK(31, 28)
  51 #define HSRX_BIAS_EN_SEL_S              20
  52 #define HSRX_BIAS_EN_SEL_M              GENMASK(21, 20)
  53
  54 #define OFS_U2_PHY_DCR0                 0x860
  55 #define PHYD_RESERVE_S                  8
  56 #define PHYD_RESERVE_M                  GENMASK(23, 8)
  57 #define CDR_FILT_S                      0
  58 #define CDR_FILT_M                      GENMASK(3, 0)
  59
  60 #define OFS_U2_PHY_DTM0                 0x868
  61 #define FORCE_USB_CLKEN                 BIT(25)
  62
  63 #define OFS_FM_CR0                      0xf00
  64 #define FREQDET_EN                      BIT(24)
  65 #define CYCLECNT_S                      0
  66 #define CYCLECNT_M                      GENMASK(23, 0)
  67
  68 #define OFS_FM_MONR0                    0xf0c
  69
  70 #define OFS_FM_MONR1                    0xf10
  71 #define FRCK_EN                         BIT(8)
  72
  73 #define U2_SR_COEF_7628                 32
  74
  75 struct mt76x8_usb_phy {
  76         void __iomem            *base;
  77         struct clk              cg;     /* for clock gating */
  78         struct reset_ctl        rst_phy;
  79 };
  80
  81 static void phy_w32(struct mt76x8_usb_phy *phy, u32 reg, u32 val)
  82 {
  83         writel(val, phy->base + reg);
  84 }
  85
  86 static u32 phy_r32(struct mt76x8_usb_phy *phy, u32 reg)
  87 {
  88         return readl(phy->base + reg);
  89 }
  90
  91 static void phy_rmw32(struct mt76x8_usb_phy *phy, u32 reg, u32 clr, u32 set)
  92 {
  93         clrsetbits_32(phy->base + reg, clr, set);
  94 }
  95
  96 static void mt76x8_usb_phy_init(struct mt76x8_usb_phy *phy)
  97 {
  98         phy_r32(phy, OFS_U2_PHY_AC2);
  99         phy_r32(phy, OFS_U2_PHY_ACR0);
 100         phy_r32(phy, OFS_U2_PHY_DCR0);
 101
 102         phy_w32(phy, OFS_U2_PHY_DCR0,
 103                 (0xffff << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
 104         phy_r32(phy, OFS_U2_PHY_DCR0);
 105
 106         phy_w32(phy, OFS_U2_PHY_DCR0,
 107                 (0x5555 << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
 108         phy_r32(phy, OFS_U2_PHY_DCR0);
 109
 110         phy_w32(phy, OFS_U2_PHY_DCR0,
 111                 (0xaaaa << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
 112         phy_r32(phy, OFS_U2_PHY_DCR0);
 113
 114         phy_w32(phy, OFS_U2_PHY_DCR0,
 115                 (4 << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
 116         phy_r32(phy, OFS_U2_PHY_DCR0);
 117
 118         phy_w32(phy, OFS_U2_PHY_AC0,
 119                 (0x48 << USBPLL_FBDIV_S) | (8 << BG_TRIM_S) |
 120                 (1 << BG_RBSEL_S) | (2 << BG_RASEL_S) | (2 << BGR_DIV_S) |
 121                 CHP_EN);
 122
 123         phy_w32(phy, OFS_U2_PHY_AC1,
 124                 (4 << VRT_VREF_SEL_S) | (4 << TERM_VREF_SEL_S) | USBPLL_RSVD |
 125                 USBPLL_ACCEN | USBPLL_LF);
 126
 127         phy_w32(phy, OFS_U2_PHY_ACR3,
 128                 (12 << HSTX_DBIST_S) | (2 << HSRX_BIAS_EN_SEL_S));
 129
 130         phy_w32(phy, OFS_U2_PHY_DTM0, FORCE_USB_CLKEN);
 131 }
 132
 133 static void mt76x8_usb_phy_sr_calibrate(struct mt76x8_usb_phy *phy)
 134 {
 135         u32 fmout, tmp = 4;
 136         int i;
 137
 138         /* Enable HS TX SR calibration */
 139         phy_rmw32(phy, OFS_U2_PHY_ACR0, 0, HSTX_SRCAL_EN);
 140         mdelay(1);
 141
 142         /* Enable free run clock */
 143         phy_rmw32(phy, OFS_FM_MONR1, 0, FRCK_EN);
 144
 145         /* Set cycle count = 0x400 */
 146         phy_rmw32(phy, OFS_FM_CR0, CYCLECNT_M, 0x400 << CYCLECNT_S);
 147
 148         /* Enable frequency meter */
 149         phy_rmw32(phy, OFS_FM_CR0, 0, FREQDET_EN);
 150
 151         /* Wait for FM detection done, set timeout to 10ms */
 152         for (i = 0; i < 10; i++) {
 153                 fmout = phy_r32(phy, OFS_FM_MONR0);
 154
 155                 if (fmout)
 156                         break;
 157
 158                 mdelay(1);
 159         }
 160
 161         /* Disable frequency meter */
 162         phy_rmw32(phy, OFS_FM_CR0, FREQDET_EN, 0);
 163
 164         /* Disable free run clock */
 165         phy_rmw32(phy, OFS_FM_MONR1, FRCK_EN, 0);
 166
 167         /* Disable HS TX SR calibration */
 168         phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCAL_EN, 0);
 169         mdelay(1);
 170
 171         if (fmout) {
 172                 /*
 173                  * set reg = (1024 / FM_OUT) * 25 * 0.028
 174                  * (round to the nearest digits)
 175                  */
 176                 tmp = (((1024 * 25 * U2_SR_COEF_7628) / fmout) + 500) / 1000;
 177         }
 178
 179         phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCTRL_M,
 180                   (tmp << HSTX_SRCTRL_S) & HSTX_SRCTRL_M);
 181 }
 182
 183 static int mt76x8_usb_phy_power_on(struct phy *_phy)
 184 {
 185         struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev);
 186
 187         clk_enable(&phy->cg);
 188
 189         reset_deassert(&phy->rst_phy);
 190
 191         /*
 192          * The SDK kernel had a delay of 100ms. however on device
 193          * testing showed that 10ms is enough
 194          */
 195         mdelay(10);
 196
 197         mt76x8_usb_phy_init(phy);
 198         mt76x8_usb_phy_sr_calibrate(phy);
 199
 200         return 0;
 201 }
 202
 203 static int mt76x8_usb_phy_power_off(struct phy *_phy)
 204 {
 205         struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev);
 206
 207         clk_disable(&phy->cg);
 208
 209         reset_assert(&phy->rst_phy);
 210
 211         return 0;
 212 }
 213
 214 static int mt76x8_usb_phy_probe(struct udevice *dev)
 215 {
 216         struct mt76x8_usb_phy *phy = dev_get_priv(dev);
 217         int ret;
 218
 219         phy->base = dev_read_addr_ptr(dev);
 220         if (!phy->base)
 221                 return -EINVAL;
 222
 223         /* clock gate */
 224         ret = clk_get_by_name(dev, "cg", &phy->cg);
 225         if (ret)
 226                 return ret;
 227
 228         ret = reset_get_by_name(dev, "phy", &phy->rst_phy);
 229         if (ret)
 230                 return ret;
 231
 232         return 0;
 233 }
 234
 235 static struct phy_ops mt76x8_usb_phy_ops = {
 236         .power_on = mt76x8_usb_phy_power_on,
 237         .power_off = mt76x8_usb_phy_power_off,
 238 };
 239
 240 static const struct udevice_id mt76x8_usb_phy_ids[] = {
 241         { .compatible = "mediatek,mt7628-usbphy" },
 242         { }
 243 };
 244
 245 U_BOOT_DRIVER(mt76x8_usb_phy) = {
 246         .name           = "mt76x8_usb_phy",
 247         .id             = UCLASS_PHY,
 248         .of_match       = mt76x8_usb_phy_ids,
 249         .ops            = &mt76x8_usb_phy_ops,
 250         .probe          = mt76x8_usb_phy_probe,
 251         .priv_auto_alloc_size = sizeof(struct mt76x8_usb_phy),
 252 };