drivers/phy/meson-gxl-usb2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Meson GXL and GXM USB2 PHY driver
   4  *
   5  * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
   6  * Copyright (C) 2018 BayLibre, SAS
   7  * Author: Neil Armstrong <narmstron@baylibre.com>
   8  */
   9
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13 #include <bitfield.h>
  14 #include <dm.h>
  15 #include <errno.h>
  16 #include <generic-phy.h>
  17 #include <regmap.h>
  18 #include <power/regulator.h>
  19 #include <clk.h>
  20 #include <linux/usb/otg.h>
  21
  22 #include <asm/arch/usb-gx.h>
  23
  24 #include <linux/bitops.h>
  25 #include <linux/compat.h>
  26
  27 /* bits [31:27] are read-only */
  28 #define U2P_R0                                                  0x0
  29         #define U2P_R0_BYPASS_SEL                               BIT(0)
  30         #define U2P_R0_BYPASS_DM_EN                             BIT(1)
  31         #define U2P_R0_BYPASS_DP_EN                             BIT(2)
  32         #define U2P_R0_TXBITSTUFF_ENH                           BIT(3)
  33         #define U2P_R0_TXBITSTUFF_EN                            BIT(4)
  34         #define U2P_R0_DM_PULLDOWN                              BIT(5)
  35         #define U2P_R0_DP_PULLDOWN                              BIT(6)
  36         #define U2P_R0_DP_VBUS_VLD_EXT_SEL                      BIT(7)
  37         #define U2P_R0_DP_VBUS_VLD_EXT                          BIT(8)
  38         #define U2P_R0_ADP_PRB_EN                               BIT(9)
  39         #define U2P_R0_ADP_DISCHARGE                            BIT(10)
  40         #define U2P_R0_ADP_CHARGE                               BIT(11)
  41         #define U2P_R0_DRV_VBUS                                 BIT(12)
  42         #define U2P_R0_ID_PULLUP                                BIT(13)
  43         #define U2P_R0_LOOPBACK_EN_B                            BIT(14)
  44         #define U2P_R0_OTG_DISABLE                              BIT(15)
  45         #define U2P_R0_COMMON_ONN                               BIT(16)
  46         #define U2P_R0_FSEL_MASK                                GENMASK(19, 17)
  47         #define U2P_R0_REF_CLK_SEL_MASK                         GENMASK(21, 20)
  48         #define U2P_R0_POWER_ON_RESET                           BIT(22)
  49         #define U2P_R0_V_ATE_TEST_EN_B_MASK                     GENMASK(24, 23)
  50         #define U2P_R0_ID_SET_ID_DQ                             BIT(25)
  51         #define U2P_R0_ATE_RESET                                BIT(26)
  52         #define U2P_R0_FSV_MINUS                                BIT(27)
  53         #define U2P_R0_FSV_PLUS                                 BIT(28)
  54         #define U2P_R0_BYPASS_DM_DATA                           BIT(29)
  55         #define U2P_R0_BYPASS_DP_DATA                           BIT(30)
  56
  57 #define U2P_R1                                                  0x4
  58         #define U2P_R1_BURN_IN_TEST                             BIT(0)
  59         #define U2P_R1_ACA_ENABLE                               BIT(1)
  60         #define U2P_R1_DCD_ENABLE                               BIT(2)
  61         #define U2P_R1_VDAT_SRC_EN_B                            BIT(3)
  62         #define U2P_R1_VDAT_DET_EN_B                            BIT(4)
  63         #define U2P_R1_CHARGES_SEL                              BIT(5)
  64         #define U2P_R1_TX_PREEMP_PULSE_TUNE                     BIT(6)
  65         #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK                  GENMASK(8, 7)
  66         #define U2P_R1_TX_RES_TUNE_MASK                         GENMASK(10, 9)
  67         #define U2P_R1_TX_RISE_TUNE_MASK                        GENMASK(12, 11)
  68         #define U2P_R1_TX_VREF_TUNE_MASK                        GENMASK(16, 13)
  69         #define U2P_R1_TX_FSLS_TUNE_MASK                        GENMASK(20, 17)
  70         #define U2P_R1_TX_HSXV_TUNE_MASK                        GENMASK(22, 21)
  71         #define U2P_R1_OTG_TUNE_MASK                            GENMASK(25, 23)
  72         #define U2P_R1_SQRX_TUNE_MASK                           GENMASK(28, 26)
  73         #define U2P_R1_COMP_DIS_TUNE_MASK                       GENMASK(31, 29)
  74
  75 /* bits [31:14] are read-only */
  76 #define U2P_R2                                                  0x8
  77         #define U2P_R2_TESTDATA_IN_MASK                         GENMASK(7, 0)
  78         #define U2P_R2_TESTADDR_MASK                            GENMASK(11, 8)
  79         #define U2P_R2_TESTDATA_OUT_SEL                         BIT(12)
  80         #define U2P_R2_TESTCLK                                  BIT(13)
  81         #define U2P_R2_TESTDATA_OUT_MASK                        GENMASK(17, 14)
  82         #define U2P_R2_ACA_PIN_RANGE_C                          BIT(18)
  83         #define U2P_R2_ACA_PIN_RANGE_B                          BIT(19)
  84         #define U2P_R2_ACA_PIN_RANGE_A                          BIT(20)
  85         #define U2P_R2_ACA_PIN_GND                              BIT(21)
  86         #define U2P_R2_ACA_PIN_FLOAT                            BIT(22)
  87         #define U2P_R2_CHARGE_DETECT                            BIT(23)
  88         #define U2P_R2_DEVICE_SESSION_VALID                     BIT(24)
  89         #define U2P_R2_ADP_PROBE                                BIT(25)
  90         #define U2P_R2_ADP_SENSE                                BIT(26)
  91         #define U2P_R2_SESSION_END                              BIT(27)
  92         #define U2P_R2_VBUS_VALID                               BIT(28)
  93         #define U2P_R2_B_VALID                                  BIT(29)
  94         #define U2P_R2_A_VALID                                  BIT(30)
  95         #define U2P_R2_ID_DIG                                   BIT(31)
  96
  97 #define U2P_R3                                                  0xc
  98
  99 #define RESET_COMPLETE_TIME                             500
 100
 101 struct phy_meson_gxl_usb2_priv {
 102         struct regmap           *regmap;
 103 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 104         struct udevice          *phy_supply;
 105 #endif
 106 #if CONFIG_IS_ENABLED(CLK)
 107         struct clk              clk;
 108 #endif
 109 };
 110
 111 static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
 112 {
 113         uint val;
 114
 115         regmap_read(priv->regmap, U2P_R0, &val);
 116
 117         /* reset the PHY and wait until settings are stabilized */
 118         val |= U2P_R0_POWER_ON_RESET;
 119         regmap_write(priv->regmap, U2P_R0, val);
 120         udelay(RESET_COMPLETE_TIME);
 121
 122         val &= ~U2P_R0_POWER_ON_RESET;
 123         regmap_write(priv->regmap, U2P_R0, val);
 124         udelay(RESET_COMPLETE_TIME);
 125 }
 126
 127 void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode)
 128 {
 129         struct udevice *dev = phy->dev;
 130         struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
 131         uint val;
 132
 133         regmap_read(priv->regmap, U2P_R0, &val);
 134
 135         switch (mode) {
 136         case USB_DR_MODE_UNKNOWN:
 137         case USB_DR_MODE_HOST:
 138         case USB_DR_MODE_OTG:
 139                 val |= U2P_R0_DM_PULLDOWN;
 140                 val |= U2P_R0_DP_PULLDOWN;
 141                 val &= ~U2P_R0_ID_PULLUP;
 142                 break;
 143
 144         case USB_DR_MODE_PERIPHERAL:
 145                 val &= ~U2P_R0_DM_PULLDOWN;
 146                 val &= ~U2P_R0_DP_PULLDOWN;
 147                 val |= U2P_R0_ID_PULLUP;
 148                 break;
 149         }
 150
 151         regmap_write(priv->regmap, U2P_R0, val);
 152
 153         phy_meson_gxl_usb2_reset(priv);
 154 }
 155
 156 static int phy_meson_gxl_usb2_power_on(struct phy *phy)
 157 {
 158         struct udevice *dev = phy->dev;
 159         struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
 160         uint val;
 161
 162         regmap_read(priv->regmap, U2P_R0, &val);
 163         /* power on the PHY by taking it out of reset mode */
 164         val &= ~U2P_R0_POWER_ON_RESET;
 165         regmap_write(priv->regmap, U2P_R0, val);
 166
 167         phy_meson_gxl_usb2_set_mode(phy, USB_DR_MODE_HOST);
 168
 169 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 170         if (priv->phy_supply) {
 171                 int ret = regulator_set_enable(priv->phy_supply, true);
 172                 if (ret)
 173                         return ret;
 174         }
 175 #endif
 176
 177         return 0;
 178 }
 179
 180 static int phy_meson_gxl_usb2_power_off(struct phy *phy)
 181 {
 182         struct udevice *dev = phy->dev;
 183         struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
 184         uint val;
 185
 186         regmap_read(priv->regmap, U2P_R0, &val);
 187         /* power off the PHY by putting it into reset mode */
 188         val |= U2P_R0_POWER_ON_RESET;
 189         regmap_write(priv->regmap, U2P_R0, val);
 190
 191 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 192         if (priv->phy_supply) {
 193                 int ret = regulator_set_enable(priv->phy_supply, false);
 194                 if (ret) {
 195                         pr_err("Error disabling PHY supply\n");
 196                         return ret;
 197                 }
 198         }
 199 #endif
 200
 201         return 0;
 202 }
 203
 204 struct phy_ops meson_gxl_usb2_phy_ops = {
 205         .power_on = phy_meson_gxl_usb2_power_on,
 206         .power_off = phy_meson_gxl_usb2_power_off,
 207 };
 208
 209 int meson_gxl_usb2_phy_probe(struct udevice *dev)
 210 {
 211         struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
 212         int ret;
 213
 214         ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
 215         if (ret)
 216                 return ret;
 217
 218 #if CONFIG_IS_ENABLED(CLK)
 219         ret = clk_get_by_index(dev, 0, &priv->clk);
 220         if (ret < 0)
 221                 return ret;
 222
 223         ret = clk_enable(&priv->clk);
 224         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 225                 pr_err("failed to enable PHY clock\n");
 226                 clk_free(&priv->clk);
 227                 return ret;
 228         }
 229 #endif
 230
 231 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 232         ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
 233         if (ret && ret != -ENOENT) {
 234                 pr_err("Failed to get PHY regulator\n");
 235                 return ret;
 236         }
 237 #endif
 238
 239         return 0;
 240 }
 241
 242 static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
 243         { .compatible = "amlogic,meson-gxl-usb2-phy" },
 244         { }
 245 };
 246
 247 U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
 248         .name = "meson_gxl_usb2_phy",
 249         .id = UCLASS_PHY,
 250         .of_match = meson_gxl_usb2_phy_ids,
 251         .probe = meson_gxl_usb2_phy_probe,
 252         .ops = &meson_gxl_usb2_phy_ops,
 253         .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv),
 254 };