drivers/phy/allwinner/phy-sun4i-usb.c

   1 /*
   2  * Allwinner sun4i USB PHY driver
   3  *
   4  * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
   5  * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
   6  * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
   7  *
   8  * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <log.h>
  17 #include <dm/device.h>
  18 #include <generic-phy.h>
  19 #include <phy-sun4i-usb.h>
  20 #include <reset.h>
  21 #include <asm/gpio.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/cpu.h>
  25 #include <dm/device_compat.h>
  26 #include <linux/bitops.h>
  27 #include <linux/delay.h>
  28 #include <linux/err.h>
  29
  30 #define REG_ISCR                        0x00
  31 #define REG_PHYCTL_A10                  0x04
  32 #define REG_PHYBIST                     0x08
  33 #define REG_PHYTUNE                     0x0c
  34 #define REG_PHYCTL_A33                  0x10
  35 #define REG_PHY_OTGCTL                  0x20
  36 #define REG_PMU_UNK1                    0x10
  37
  38 /* Common Control Bits for Both PHYs */
  39 #define PHY_PLL_BW                      0x03
  40 #define PHY_RES45_CAL_EN                0x0c
  41
  42 /* Private Control Bits for Each PHY */
  43 #define PHY_TX_AMPLITUDE_TUNE           0x20
  44 #define PHY_TX_SLEWRATE_TUNE            0x22
  45 #define PHY_DISCON_TH_SEL               0x2a
  46 #define PHY_SQUELCH_DETECT              0x3c
  47
  48 #define PHYCTL_DATA                     BIT(7)
  49 #define OTGCTL_ROUTE_MUSB               BIT(0)
  50
  51 #define PHY_TX_RATE                     BIT(4)
  52 #define PHY_TX_MAGNITUDE                BIT(2)
  53 #define PHY_TX_AMPLITUDE_LEN            5
  54
  55 #define PHY_RES45_CAL_DATA              BIT(0)
  56 #define PHY_RES45_CAL_LEN               1
  57 #define PHY_DISCON_TH_LEN               2
  58
  59 #define SUNXI_AHB_ICHR8_EN              BIT(10)
  60 #define SUNXI_AHB_INCR4_BURST_EN        BIT(9)
  61 #define SUNXI_AHB_INCRX_ALIGN_EN        BIT(8)
  62 #define SUNXI_ULPI_BYPASS_EN            BIT(0)
  63
  64 /* A83T specific control bits for PHY0 */
  65 #define PHY_CTL_VBUSVLDEXT              BIT(5)
  66 #define PHY_CTL_SIDDQ                   BIT(3)
  67
  68 /* A83T specific control bits for PHY2 HSIC */
  69 #define SUNXI_EHCI_HS_FORCE             BIT(20)
  70 #define SUNXI_HSIC_CONNECT_INT          BIT(16)
  71 #define SUNXI_HSIC                      BIT(1)
  72
  73 #define MAX_PHYS                        4
  74
  75 enum sun4i_usb_phy_type {
  76         sun4i_a10_phy,
  77         sun6i_a31_phy,
  78         sun8i_a33_phy,
  79         sun8i_a83t_phy,
  80         sun8i_h3_phy,
  81         sun8i_r40_phy,
  82         sun8i_v3s_phy,
  83         sun50i_a64_phy,
  84         sun50i_h6_phy,
  85 };
  86
  87 struct sun4i_usb_phy_cfg {
  88         int num_phys;
  89         enum sun4i_usb_phy_type type;
  90         u32 disc_thresh;
  91         u8 phyctl_offset;
  92         bool dedicated_clocks;
  93         bool enable_pmu_unk1;
  94         bool phy0_dual_route;
  95         int missing_phys;
  96 };
  97
  98 struct sun4i_usb_phy_info {
  99         const char *gpio_vbus;
 100         const char *gpio_vbus_det;
 101         const char *gpio_id_det;
 102 } phy_info[] = {
 103         {
 104                 .gpio_vbus = CONFIG_USB0_VBUS_PIN,
 105                 .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
 106                 .gpio_id_det = CONFIG_USB0_ID_DET,
 107         },
 108         {
 109                 .gpio_vbus = CONFIG_USB1_VBUS_PIN,
 110                 .gpio_vbus_det = NULL,
 111                 .gpio_id_det = NULL,
 112         },
 113         {
 114                 .gpio_vbus = CONFIG_USB2_VBUS_PIN,
 115                 .gpio_vbus_det = NULL,
 116                 .gpio_id_det = NULL,
 117         },
 118         {
 119                 .gpio_vbus = CONFIG_USB3_VBUS_PIN,
 120                 .gpio_vbus_det = NULL,
 121                 .gpio_id_det = NULL,
 122         },
 123 };
 124
 125 struct sun4i_usb_phy_plat {
 126         void __iomem *pmu;
 127         int power_on_count;
 128         int gpio_vbus;
 129         int gpio_vbus_det;
 130         int gpio_id_det;
 131         struct clk clocks;
 132         struct reset_ctl resets;
 133         int id;
 134 };
 135
 136 struct sun4i_usb_phy_data {
 137         void __iomem *base;
 138         const struct sun4i_usb_phy_cfg *cfg;
 139         struct sun4i_usb_phy_plat *usb_phy;
 140 };
 141
 142 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
 143
 144 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
 145 {
 146         struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
 147         struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
 148         u32 temp, usbc_bit = BIT(usb_phy->id * 2);
 149         void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
 150         int i;
 151
 152         if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
 153                 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
 154                 writel(0, phyctl);
 155         }
 156
 157         for (i = 0; i < len; i++) {
 158                 temp = readl(phyctl);
 159
 160                 /* clear the address portion */
 161                 temp &= ~(0xff << 8);
 162
 163                 /* set the address */
 164                 temp |= ((addr + i) << 8);
 165                 writel(temp, phyctl);
 166
 167                 /* set the data bit and clear usbc bit*/
 168                 temp = readb(phyctl);
 169                 if (data & 0x1)
 170                         temp |= PHYCTL_DATA;
 171                 else
 172                         temp &= ~PHYCTL_DATA;
 173                 temp &= ~usbc_bit;
 174                 writeb(temp, phyctl);
 175
 176                 /* pulse usbc_bit */
 177                 temp = readb(phyctl);
 178                 temp |= usbc_bit;
 179                 writeb(temp, phyctl);
 180
 181                 temp = readb(phyctl);
 182                 temp &= ~usbc_bit;
 183                 writeb(temp, phyctl);
 184
 185                 data >>= 1;
 186         }
 187 }
 188
 189 static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
 190 {
 191         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 192         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 193         u32 bits, reg_value;
 194
 195         if (!usb_phy->pmu)
 196                 return;
 197
 198         bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 199                 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 200
 201         /* A83T USB2 is HSIC */
 202         if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
 203                 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
 204                         SUNXI_HSIC;
 205
 206         reg_value = readl(usb_phy->pmu);
 207
 208         if (enable)
 209                 reg_value |= bits;
 210         else
 211                 reg_value &= ~bits;
 212
 213         writel(reg_value, usb_phy->pmu);
 214 }
 215
 216 static int sun4i_usb_phy_power_on(struct phy *phy)
 217 {
 218         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 219         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 220
 221         if (initial_usb_scan_delay) {
 222                 mdelay(initial_usb_scan_delay);
 223                 initial_usb_scan_delay = 0;
 224         }
 225
 226         usb_phy->power_on_count++;
 227         if (usb_phy->power_on_count != 1)
 228                 return 0;
 229
 230         if (usb_phy->gpio_vbus >= 0)
 231                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
 232
 233         return 0;
 234 }
 235
 236 static int sun4i_usb_phy_power_off(struct phy *phy)
 237 {
 238         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 239         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 240
 241         usb_phy->power_on_count--;
 242         if (usb_phy->power_on_count != 0)
 243                 return 0;
 244
 245         if (usb_phy->gpio_vbus >= 0)
 246                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
 247
 248         return 0;
 249 }
 250
 251 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
 252 {
 253         u32 regval;
 254
 255         regval = readl(data->base + REG_PHY_OTGCTL);
 256         if (!id_det) {
 257                 /* Host mode. Route phy0 to EHCI/OHCI */
 258                 regval &= ~OTGCTL_ROUTE_MUSB;
 259         } else {
 260                 /* Peripheral mode. Route phy0 to MUSB */
 261                 regval |= OTGCTL_ROUTE_MUSB;
 262         }
 263         writel(regval, data->base + REG_PHY_OTGCTL);
 264 }
 265
 266 static int sun4i_usb_phy_init(struct phy *phy)
 267 {
 268         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 269         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 270         u32 val;
 271         int ret;
 272
 273         ret = clk_enable(&usb_phy->clocks);
 274         if (ret) {
 275                 dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id);
 276                 return ret;
 277         }
 278
 279         ret = reset_deassert(&usb_phy->resets);
 280         if (ret) {
 281                 dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id);
 282                 return ret;
 283         }
 284
 285         if (data->cfg->type == sun8i_a83t_phy ||
 286             data->cfg->type == sun50i_h6_phy) {
 287                 if (phy->id == 0) {
 288                         val = readl(data->base + data->cfg->phyctl_offset);
 289                         val |= PHY_CTL_VBUSVLDEXT;
 290                         val &= ~PHY_CTL_SIDDQ;
 291                         writel(val, data->base + data->cfg->phyctl_offset);
 292                 }
 293         } else {
 294                 if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
 295                         val = readl(usb_phy->pmu + REG_PMU_UNK1);
 296                         writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
 297                 }
 298
 299                 if (usb_phy->id == 0)
 300                         sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
 301                                             PHY_RES45_CAL_DATA,
 302                                             PHY_RES45_CAL_LEN);
 303
 304                 /* Adjust PHY's magnitude and rate */
 305                 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
 306                                     PHY_TX_MAGNITUDE | PHY_TX_RATE,
 307                                     PHY_TX_AMPLITUDE_LEN);
 308
 309                 /* Disconnect threshold adjustment */
 310                 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
 311                                     data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
 312         }
 313
 314         sun4i_usb_phy_passby(phy, true);
 315
 316         sun4i_usb_phy0_reroute(data, true);
 317
 318         return 0;
 319 }
 320
 321 static int sun4i_usb_phy_exit(struct phy *phy)
 322 {
 323         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 324         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 325         int ret;
 326
 327         if (phy->id == 0) {
 328                 if (data->cfg->type == sun8i_a83t_phy ||
 329                     data->cfg->type == sun50i_h6_phy) {
 330                         void __iomem *phyctl = data->base +
 331                                 data->cfg->phyctl_offset;
 332
 333                         writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
 334                 }
 335         }
 336
 337         sun4i_usb_phy_passby(phy, false);
 338
 339         ret = clk_disable(&usb_phy->clocks);
 340         if (ret) {
 341                 dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id);
 342                 return ret;
 343         }
 344
 345         ret = reset_assert(&usb_phy->resets);
 346         if (ret) {
 347                 dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id);
 348                 return ret;
 349         }
 350
 351         return 0;
 352 }
 353
 354 static int sun4i_usb_phy_xlate(struct phy *phy,
 355                                struct ofnode_phandle_args *args)
 356 {
 357         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 358
 359         if (args->args_count >= data->cfg->num_phys)
 360                 return -EINVAL;
 361
 362         if (data->cfg->missing_phys & BIT(args->args[0]))
 363                 return -ENODEV;
 364
 365         if (args->args_count)
 366                 phy->id = args->args[0];
 367         else
 368                 phy->id = 0;
 369
 370         debug("%s: phy_id = %ld\n", __func__, phy->id);
 371         return 0;
 372 }
 373
 374 int sun4i_usb_phy_vbus_detect(struct phy *phy)
 375 {
 376         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 377         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 378         int err, retries = 3;
 379
 380         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 381
 382         if (usb_phy->gpio_vbus_det < 0)
 383                 return usb_phy->gpio_vbus_det;
 384
 385         err = gpio_get_value(usb_phy->gpio_vbus_det);
 386         /*
 387          * Vbus may have been provided by the board and just been turned of
 388          * some milliseconds ago on reset, what we're measuring then is a
 389          * residual charge on Vbus, sleep a bit and try again.
 390          */
 391         while (err > 0 && retries--) {
 392                 mdelay(100);
 393                 err = gpio_get_value(usb_phy->gpio_vbus_det);
 394         }
 395
 396         return err;
 397 }
 398
 399 int sun4i_usb_phy_id_detect(struct phy *phy)
 400 {
 401         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 402         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 403
 404         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 405
 406         if (usb_phy->gpio_id_det < 0)
 407                 return usb_phy->gpio_id_det;
 408
 409         return gpio_get_value(usb_phy->gpio_id_det);
 410 }
 411
 412 void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
 413 {
 414         sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
 415 }
 416
 417 static struct phy_ops sun4i_usb_phy_ops = {
 418         .of_xlate = sun4i_usb_phy_xlate,
 419         .init = sun4i_usb_phy_init,
 420         .power_on = sun4i_usb_phy_power_on,
 421         .power_off = sun4i_usb_phy_power_off,
 422         .exit = sun4i_usb_phy_exit,
 423 };
 424
 425 static int sun4i_usb_phy_probe(struct udevice *dev)
 426 {
 427         struct sun4i_usb_phy_plat *plat = dev_get_platdata(dev);
 428         struct sun4i_usb_phy_data *data = dev_get_priv(dev);
 429         int i, ret;
 430
 431         data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
 432         if (!data->cfg)
 433                 return -EINVAL;
 434
 435         data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
 436         if (IS_ERR(data->base))
 437                 return PTR_ERR(data->base);
 438
 439         data->usb_phy = plat;
 440         for (i = 0; i < data->cfg->num_phys; i++) {
 441                 struct sun4i_usb_phy_plat *phy = &plat[i];
 442                 struct sun4i_usb_phy_info *info = &phy_info[i];
 443                 char name[16];
 444
 445                 if (data->cfg->missing_phys & BIT(i))
 446                         continue;
 447
 448                 phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
 449                 if (phy->gpio_vbus >= 0) {
 450                         ret = gpio_request(phy->gpio_vbus, "usb_vbus");
 451                         if (ret)
 452                                 return ret;
 453                         ret = gpio_direction_output(phy->gpio_vbus, 0);
 454                         if (ret)
 455                                 return ret;
 456                 }
 457
 458                 phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
 459                 if (phy->gpio_vbus_det >= 0) {
 460                         ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
 461                         if (ret)
 462                                 return ret;
 463                         ret = gpio_direction_input(phy->gpio_vbus_det);
 464                         if (ret)
 465                                 return ret;
 466                 }
 467
 468                 phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
 469                 if (phy->gpio_id_det >= 0) {
 470                         ret = gpio_request(phy->gpio_id_det, "usb_id_det");
 471                         if (ret)
 472                                 return ret;
 473                         ret = gpio_direction_input(phy->gpio_id_det);
 474                         if (ret)
 475                                 return ret;
 476                         sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 477                 }
 478
 479                 if (data->cfg->dedicated_clocks)
 480                         snprintf(name, sizeof(name), "usb%d_phy", i);
 481                 else
 482                         strlcpy(name, "usb_phy", sizeof(name));
 483
 484                 ret = clk_get_by_name(dev, name, &phy->clocks);
 485                 if (ret) {
 486                         dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
 487                         return ret;
 488                 }
 489
 490                 snprintf(name, sizeof(name), "usb%d_reset", i);
 491                 ret = reset_get_by_name(dev, name, &phy->resets);
 492                 if (ret) {
 493                         dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
 494                         return ret;
 495                 }
 496
 497                 if (i || data->cfg->phy0_dual_route) {
 498                         snprintf(name, sizeof(name), "pmu%d", i);
 499                         phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
 500                         if (IS_ERR(phy->pmu))
 501                                 return PTR_ERR(phy->pmu);
 502                 }
 503
 504                 phy->id = i;
 505         };
 506
 507         debug("Allwinner Sun4I USB PHY driver loaded\n");
 508         return 0;
 509 }
 510
 511 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 512         .num_phys = 3,
 513         .type = sun4i_a10_phy,
 514         .disc_thresh = 3,
 515         .phyctl_offset = REG_PHYCTL_A10,
 516         .dedicated_clocks = false,
 517         .enable_pmu_unk1 = false,
 518 };
 519
 520 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 521         .num_phys = 2,
 522         .type = sun4i_a10_phy,
 523         .disc_thresh = 2,
 524         .phyctl_offset = REG_PHYCTL_A10,
 525         .dedicated_clocks = false,
 526         .enable_pmu_unk1 = false,
 527 };
 528
 529 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 530         .num_phys = 3,
 531         .type = sun6i_a31_phy,
 532         .disc_thresh = 3,
 533         .phyctl_offset = REG_PHYCTL_A10,
 534         .dedicated_clocks = true,
 535         .enable_pmu_unk1 = false,
 536 };
 537
 538 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 539         .num_phys = 3,
 540         .type = sun4i_a10_phy,
 541         .disc_thresh = 2,
 542         .phyctl_offset = REG_PHYCTL_A10,
 543         .dedicated_clocks = false,
 544         .enable_pmu_unk1 = false,
 545 };
 546
 547 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 548         .num_phys = 2,
 549         .type = sun4i_a10_phy,
 550         .disc_thresh = 3,
 551         .phyctl_offset = REG_PHYCTL_A10,
 552         .dedicated_clocks = true,
 553         .enable_pmu_unk1 = false,
 554 };
 555
 556 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 557         .num_phys = 2,
 558         .type = sun8i_a33_phy,
 559         .disc_thresh = 3,
 560         .phyctl_offset = REG_PHYCTL_A33,
 561         .dedicated_clocks = true,
 562         .enable_pmu_unk1 = false,
 563 };
 564
 565 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 566         .num_phys = 3,
 567         .type = sun8i_a83t_phy,
 568         .phyctl_offset = REG_PHYCTL_A33,
 569         .dedicated_clocks = true,
 570 };
 571
 572 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 573         .num_phys = 4,
 574         .type = sun8i_h3_phy,
 575         .disc_thresh = 3,
 576         .phyctl_offset = REG_PHYCTL_A33,
 577         .dedicated_clocks = true,
 578         .enable_pmu_unk1 = true,
 579         .phy0_dual_route = true,
 580 };
 581
 582 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
 583         .num_phys = 3,
 584         .type = sun8i_r40_phy,
 585         .disc_thresh = 3,
 586         .phyctl_offset = REG_PHYCTL_A33,
 587         .dedicated_clocks = true,
 588         .enable_pmu_unk1 = true,
 589         .phy0_dual_route = true,
 590 };
 591
 592 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 593         .num_phys = 1,
 594         .type = sun8i_v3s_phy,
 595         .disc_thresh = 3,
 596         .phyctl_offset = REG_PHYCTL_A33,
 597         .dedicated_clocks = true,
 598         .enable_pmu_unk1 = true,
 599         .phy0_dual_route = true,
 600 };
 601
 602 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 603         .num_phys = 2,
 604         .type = sun50i_a64_phy,
 605         .disc_thresh = 3,
 606         .phyctl_offset = REG_PHYCTL_A33,
 607         .dedicated_clocks = true,
 608         .enable_pmu_unk1 = true,
 609         .phy0_dual_route = true,
 610 };
 611
 612 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 613         .num_phys = 4,
 614         .type = sun50i_h6_phy,
 615         .disc_thresh = 3,
 616         .phyctl_offset = REG_PHYCTL_A33,
 617         .dedicated_clocks = true,
 618         .enable_pmu_unk1 = true,
 619         .phy0_dual_route = true,
 620         .missing_phys = BIT(1) | BIT(2),
 621 };
 622
 623 static const struct udevice_id sun4i_usb_phy_ids[] = {
 624         { .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
 625         { .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
 626         { .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
 627         { .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
 628         { .compatible = "allwinner,sun8i-a23-usb-phy", .data = (ulong)&sun8i_a23_cfg },
 629         { .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
 630         { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 631         { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 632         { .compatible = "allwinner,sun8i-r40-usb-phy", .data = (ulong)&sun8i_r40_cfg },
 633         { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
 634         { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 635         { .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
 636         { }
 637 };
 638
 639 U_BOOT_DRIVER(sun4i_usb_phy) = {
 640         .name   = "sun4i_usb_phy",
 641         .id     = UCLASS_PHY,
 642         .of_match = sun4i_usb_phy_ids,
 643         .ops = &sun4i_usb_phy_ops,
 644         .probe = sun4i_usb_phy_probe,
 645         .platdata_auto_alloc_size = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
 646         .priv_auto_alloc_size = sizeof(struct sun4i_usb_phy_data),
 647 };