drivers/phy/allwinner/phy-sun4i-usb.c

   1 /*
   2  * Allwinner sun4i USB PHY driver
   3  *
   4  * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
   5  * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
   6  * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
   7  *
   8  * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <log.h>
  17 #include <dm/device.h>
  18 #include <generic-phy.h>
  19 #include <phy-sun4i-usb.h>
  20 #include <reset.h>
  21 #include <asm/gpio.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/cpu.h>
  25 #include <dm/device_compat.h>
  26 #include <linux/delay.h>
  27 #include <linux/err.h>
  28
  29 #define REG_ISCR                        0x00
  30 #define REG_PHYCTL_A10                  0x04
  31 #define REG_PHYBIST                     0x08
  32 #define REG_PHYTUNE                     0x0c
  33 #define REG_PHYCTL_A33                  0x10
  34 #define REG_PHY_OTGCTL                  0x20
  35 #define REG_PMU_UNK1                    0x10
  36
  37 /* Common Control Bits for Both PHYs */
  38 #define PHY_PLL_BW                      0x03
  39 #define PHY_RES45_CAL_EN                0x0c
  40
  41 /* Private Control Bits for Each PHY */
  42 #define PHY_TX_AMPLITUDE_TUNE           0x20
  43 #define PHY_TX_SLEWRATE_TUNE            0x22
  44 #define PHY_DISCON_TH_SEL               0x2a
  45 #define PHY_SQUELCH_DETECT              0x3c
  46
  47 #define PHYCTL_DATA                     BIT(7)
  48 #define OTGCTL_ROUTE_MUSB               BIT(0)
  49
  50 #define PHY_TX_RATE                     BIT(4)
  51 #define PHY_TX_MAGNITUDE                BIT(2)
  52 #define PHY_TX_AMPLITUDE_LEN            5
  53
  54 #define PHY_RES45_CAL_DATA              BIT(0)
  55 #define PHY_RES45_CAL_LEN               1
  56 #define PHY_DISCON_TH_LEN               2
  57
  58 #define SUNXI_AHB_ICHR8_EN              BIT(10)
  59 #define SUNXI_AHB_INCR4_BURST_EN        BIT(9)
  60 #define SUNXI_AHB_INCRX_ALIGN_EN        BIT(8)
  61 #define SUNXI_ULPI_BYPASS_EN            BIT(0)
  62
  63 /* A83T specific control bits for PHY0 */
  64 #define PHY_CTL_VBUSVLDEXT              BIT(5)
  65 #define PHY_CTL_SIDDQ                   BIT(3)
  66
  67 /* A83T specific control bits for PHY2 HSIC */
  68 #define SUNXI_EHCI_HS_FORCE             BIT(20)
  69 #define SUNXI_HSIC_CONNECT_INT          BIT(16)
  70 #define SUNXI_HSIC                      BIT(1)
  71
  72 #define MAX_PHYS                        4
  73
  74 enum sun4i_usb_phy_type {
  75         sun4i_a10_phy,
  76         sun6i_a31_phy,
  77         sun8i_a33_phy,
  78         sun8i_a83t_phy,
  79         sun8i_h3_phy,
  80         sun8i_r40_phy,
  81         sun8i_v3s_phy,
  82         sun50i_a64_phy,
  83         sun50i_h6_phy,
  84 };
  85
  86 struct sun4i_usb_phy_cfg {
  87         int num_phys;
  88         enum sun4i_usb_phy_type type;
  89         u32 disc_thresh;
  90         u8 phyctl_offset;
  91         bool dedicated_clocks;
  92         bool enable_pmu_unk1;
  93         bool phy0_dual_route;
  94         int missing_phys;
  95 };
  96
  97 struct sun4i_usb_phy_info {
  98         const char *gpio_vbus;
  99         const char *gpio_vbus_det;
 100         const char *gpio_id_det;
 101 } phy_info[] = {
 102         {
 103                 .gpio_vbus = CONFIG_USB0_VBUS_PIN,
 104                 .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
 105                 .gpio_id_det = CONFIG_USB0_ID_DET,
 106         },
 107         {
 108                 .gpio_vbus = CONFIG_USB1_VBUS_PIN,
 109                 .gpio_vbus_det = NULL,
 110                 .gpio_id_det = NULL,
 111         },
 112         {
 113                 .gpio_vbus = CONFIG_USB2_VBUS_PIN,
 114                 .gpio_vbus_det = NULL,
 115                 .gpio_id_det = NULL,
 116         },
 117         {
 118                 .gpio_vbus = CONFIG_USB3_VBUS_PIN,
 119                 .gpio_vbus_det = NULL,
 120                 .gpio_id_det = NULL,
 121         },
 122 };
 123
 124 struct sun4i_usb_phy_plat {
 125         void __iomem *pmu;
 126         int power_on_count;
 127         int gpio_vbus;
 128         int gpio_vbus_det;
 129         int gpio_id_det;
 130         struct clk clocks;
 131         struct reset_ctl resets;
 132         int id;
 133 };
 134
 135 struct sun4i_usb_phy_data {
 136         void __iomem *base;
 137         const struct sun4i_usb_phy_cfg *cfg;
 138         struct sun4i_usb_phy_plat *usb_phy;
 139 };
 140
 141 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
 142
 143 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
 144 {
 145         struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
 146         struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
 147         u32 temp, usbc_bit = BIT(usb_phy->id * 2);
 148         void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
 149         int i;
 150
 151         if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
 152                 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
 153                 writel(0, phyctl);
 154         }
 155
 156         for (i = 0; i < len; i++) {
 157                 temp = readl(phyctl);
 158
 159                 /* clear the address portion */
 160                 temp &= ~(0xff << 8);
 161
 162                 /* set the address */
 163                 temp |= ((addr + i) << 8);
 164                 writel(temp, phyctl);
 165
 166                 /* set the data bit and clear usbc bit*/
 167                 temp = readb(phyctl);
 168                 if (data & 0x1)
 169                         temp |= PHYCTL_DATA;
 170                 else
 171                         temp &= ~PHYCTL_DATA;
 172                 temp &= ~usbc_bit;
 173                 writeb(temp, phyctl);
 174
 175                 /* pulse usbc_bit */
 176                 temp = readb(phyctl);
 177                 temp |= usbc_bit;
 178                 writeb(temp, phyctl);
 179
 180                 temp = readb(phyctl);
 181                 temp &= ~usbc_bit;
 182                 writeb(temp, phyctl);
 183
 184                 data >>= 1;
 185         }
 186 }
 187
 188 static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
 189 {
 190         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 191         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 192         u32 bits, reg_value;
 193
 194         if (!usb_phy->pmu)
 195                 return;
 196
 197         bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 198                 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 199
 200         /* A83T USB2 is HSIC */
 201         if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
 202                 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
 203                         SUNXI_HSIC;
 204
 205         reg_value = readl(usb_phy->pmu);
 206
 207         if (enable)
 208                 reg_value |= bits;
 209         else
 210                 reg_value &= ~bits;
 211
 212         writel(reg_value, usb_phy->pmu);
 213 }
 214
 215 static int sun4i_usb_phy_power_on(struct phy *phy)
 216 {
 217         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 218         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 219
 220         if (initial_usb_scan_delay) {
 221                 mdelay(initial_usb_scan_delay);
 222                 initial_usb_scan_delay = 0;
 223         }
 224
 225         usb_phy->power_on_count++;
 226         if (usb_phy->power_on_count != 1)
 227                 return 0;
 228
 229         if (usb_phy->gpio_vbus >= 0)
 230                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
 231
 232         return 0;
 233 }
 234
 235 static int sun4i_usb_phy_power_off(struct phy *phy)
 236 {
 237         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 238         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 239
 240         usb_phy->power_on_count--;
 241         if (usb_phy->power_on_count != 0)
 242                 return 0;
 243
 244         if (usb_phy->gpio_vbus >= 0)
 245                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
 246
 247         return 0;
 248 }
 249
 250 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
 251 {
 252         u32 regval;
 253
 254         regval = readl(data->base + REG_PHY_OTGCTL);
 255         if (!id_det) {
 256                 /* Host mode. Route phy0 to EHCI/OHCI */
 257                 regval &= ~OTGCTL_ROUTE_MUSB;
 258         } else {
 259                 /* Peripheral mode. Route phy0 to MUSB */
 260                 regval |= OTGCTL_ROUTE_MUSB;
 261         }
 262         writel(regval, data->base + REG_PHY_OTGCTL);
 263 }
 264
 265 static int sun4i_usb_phy_init(struct phy *phy)
 266 {
 267         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 268         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 269         u32 val;
 270         int ret;
 271
 272         ret = clk_enable(&usb_phy->clocks);
 273         if (ret) {
 274                 dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id);
 275                 return ret;
 276         }
 277
 278         ret = reset_deassert(&usb_phy->resets);
 279         if (ret) {
 280                 dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id);
 281                 return ret;
 282         }
 283
 284         if (data->cfg->type == sun8i_a83t_phy) {
 285                 if (phy->id == 0) {
 286                         val = readl(data->base + data->cfg->phyctl_offset);
 287                         val |= PHY_CTL_VBUSVLDEXT;
 288                         val &= ~PHY_CTL_SIDDQ;
 289                         writel(val, data->base + data->cfg->phyctl_offset);
 290                 }
 291         } else {
 292                 if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
 293                         val = readl(usb_phy->pmu + REG_PMU_UNK1);
 294                         writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
 295                 }
 296
 297                 if (usb_phy->id == 0)
 298                         sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
 299                                             PHY_RES45_CAL_DATA,
 300                                             PHY_RES45_CAL_LEN);
 301
 302                 /* Adjust PHY's magnitude and rate */
 303                 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
 304                                     PHY_TX_MAGNITUDE | PHY_TX_RATE,
 305                                     PHY_TX_AMPLITUDE_LEN);
 306
 307                 /* Disconnect threshold adjustment */
 308                 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
 309                                     data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
 310         }
 311
 312         sun4i_usb_phy_passby(phy, true);
 313
 314         sun4i_usb_phy0_reroute(data, true);
 315
 316         return 0;
 317 }
 318
 319 static int sun4i_usb_phy_exit(struct phy *phy)
 320 {
 321         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 322         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 323         int ret;
 324
 325         if (phy->id == 0) {
 326                 if (data->cfg->type == sun8i_a83t_phy) {
 327                         void __iomem *phyctl = data->base +
 328                                 data->cfg->phyctl_offset;
 329
 330                         writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
 331                 }
 332         }
 333
 334         sun4i_usb_phy_passby(phy, false);
 335
 336         ret = clk_disable(&usb_phy->clocks);
 337         if (ret) {
 338                 dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id);
 339                 return ret;
 340         }
 341
 342         ret = reset_assert(&usb_phy->resets);
 343         if (ret) {
 344                 dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id);
 345                 return ret;
 346         }
 347
 348         return 0;
 349 }
 350
 351 static int sun4i_usb_phy_xlate(struct phy *phy,
 352                                struct ofnode_phandle_args *args)
 353 {
 354         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 355
 356         if (args->args_count >= data->cfg->num_phys)
 357                 return -EINVAL;
 358
 359         if (data->cfg->missing_phys & BIT(args->args[0]))
 360                 return -ENODEV;
 361
 362         if (args->args_count)
 363                 phy->id = args->args[0];
 364         else
 365                 phy->id = 0;
 366
 367         debug("%s: phy_id = %ld\n", __func__, phy->id);
 368         return 0;
 369 }
 370
 371 int sun4i_usb_phy_vbus_detect(struct phy *phy)
 372 {
 373         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 374         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 375         int err, retries = 3;
 376
 377         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 378
 379         if (usb_phy->gpio_vbus_det < 0)
 380                 return usb_phy->gpio_vbus_det;
 381
 382         err = gpio_get_value(usb_phy->gpio_vbus_det);
 383         /*
 384          * Vbus may have been provided by the board and just been turned of
 385          * some milliseconds ago on reset, what we're measuring then is a
 386          * residual charge on Vbus, sleep a bit and try again.
 387          */
 388         while (err > 0 && retries--) {
 389                 mdelay(100);
 390                 err = gpio_get_value(usb_phy->gpio_vbus_det);
 391         }
 392
 393         return err;
 394 }
 395
 396 int sun4i_usb_phy_id_detect(struct phy *phy)
 397 {
 398         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 399         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 400
 401         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 402
 403         if (usb_phy->gpio_id_det < 0)
 404                 return usb_phy->gpio_id_det;
 405
 406         return gpio_get_value(usb_phy->gpio_id_det);
 407 }
 408
 409 void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
 410 {
 411         sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
 412 }
 413
 414 static struct phy_ops sun4i_usb_phy_ops = {
 415         .of_xlate = sun4i_usb_phy_xlate,
 416         .init = sun4i_usb_phy_init,
 417         .power_on = sun4i_usb_phy_power_on,
 418         .power_off = sun4i_usb_phy_power_off,
 419         .exit = sun4i_usb_phy_exit,
 420 };
 421
 422 static int sun4i_usb_phy_probe(struct udevice *dev)
 423 {
 424         struct sun4i_usb_phy_plat *plat = dev_get_platdata(dev);
 425         struct sun4i_usb_phy_data *data = dev_get_priv(dev);
 426         int i, ret;
 427
 428         data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
 429         if (!data->cfg)
 430                 return -EINVAL;
 431
 432         data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
 433         if (IS_ERR(data->base))
 434                 return PTR_ERR(data->base);
 435
 436         data->usb_phy = plat;
 437         for (i = 0; i < data->cfg->num_phys; i++) {
 438                 struct sun4i_usb_phy_plat *phy = &plat[i];
 439                 struct sun4i_usb_phy_info *info = &phy_info[i];
 440                 char name[16];
 441
 442                 if (data->cfg->missing_phys & BIT(i))
 443                         continue;
 444
 445                 phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
 446                 if (phy->gpio_vbus >= 0) {
 447                         ret = gpio_request(phy->gpio_vbus, "usb_vbus");
 448                         if (ret)
 449                                 return ret;
 450                         ret = gpio_direction_output(phy->gpio_vbus, 0);
 451                         if (ret)
 452                                 return ret;
 453                 }
 454
 455                 phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
 456                 if (phy->gpio_vbus_det >= 0) {
 457                         ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
 458                         if (ret)
 459                                 return ret;
 460                         ret = gpio_direction_input(phy->gpio_vbus_det);
 461                         if (ret)
 462                                 return ret;
 463                 }
 464
 465                 phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
 466                 if (phy->gpio_id_det >= 0) {
 467                         ret = gpio_request(phy->gpio_id_det, "usb_id_det");
 468                         if (ret)
 469                                 return ret;
 470                         ret = gpio_direction_input(phy->gpio_id_det);
 471                         if (ret)
 472                                 return ret;
 473                         sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 474                 }
 475
 476                 if (data->cfg->dedicated_clocks)
 477                         snprintf(name, sizeof(name), "usb%d_phy", i);
 478                 else
 479                         strlcpy(name, "usb_phy", sizeof(name));
 480
 481                 ret = clk_get_by_name(dev, name, &phy->clocks);
 482                 if (ret) {
 483                         dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
 484                         return ret;
 485                 }
 486
 487                 snprintf(name, sizeof(name), "usb%d_reset", i);
 488                 ret = reset_get_by_name(dev, name, &phy->resets);
 489                 if (ret) {
 490                         dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
 491                         return ret;
 492                 }
 493
 494                 if (i || data->cfg->phy0_dual_route) {
 495                         snprintf(name, sizeof(name), "pmu%d", i);
 496                         phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
 497                         if (IS_ERR(phy->pmu))
 498                                 return PTR_ERR(phy->pmu);
 499                 }
 500
 501                 phy->id = i;
 502         };
 503
 504         debug("Allwinner Sun4I USB PHY driver loaded\n");
 505         return 0;
 506 }
 507
 508 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 509         .num_phys = 3,
 510         .type = sun4i_a10_phy,
 511         .disc_thresh = 3,
 512         .phyctl_offset = REG_PHYCTL_A10,
 513         .dedicated_clocks = false,
 514         .enable_pmu_unk1 = false,
 515 };
 516
 517 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 518         .num_phys = 2,
 519         .type = sun4i_a10_phy,
 520         .disc_thresh = 2,
 521         .phyctl_offset = REG_PHYCTL_A10,
 522         .dedicated_clocks = false,
 523         .enable_pmu_unk1 = false,
 524 };
 525
 526 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 527         .num_phys = 3,
 528         .type = sun6i_a31_phy,
 529         .disc_thresh = 3,
 530         .phyctl_offset = REG_PHYCTL_A10,
 531         .dedicated_clocks = true,
 532         .enable_pmu_unk1 = false,
 533 };
 534
 535 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 536         .num_phys = 3,
 537         .type = sun4i_a10_phy,
 538         .disc_thresh = 2,
 539         .phyctl_offset = REG_PHYCTL_A10,
 540         .dedicated_clocks = false,
 541         .enable_pmu_unk1 = false,
 542 };
 543
 544 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 545         .num_phys = 2,
 546         .type = sun4i_a10_phy,
 547         .disc_thresh = 3,
 548         .phyctl_offset = REG_PHYCTL_A10,
 549         .dedicated_clocks = true,
 550         .enable_pmu_unk1 = false,
 551 };
 552
 553 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 554         .num_phys = 2,
 555         .type = sun8i_a33_phy,
 556         .disc_thresh = 3,
 557         .phyctl_offset = REG_PHYCTL_A33,
 558         .dedicated_clocks = true,
 559         .enable_pmu_unk1 = false,
 560 };
 561
 562 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 563         .num_phys = 3,
 564         .type = sun8i_a83t_phy,
 565         .phyctl_offset = REG_PHYCTL_A33,
 566         .dedicated_clocks = true,
 567 };
 568
 569 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 570         .num_phys = 4,
 571         .type = sun8i_h3_phy,
 572         .disc_thresh = 3,
 573         .phyctl_offset = REG_PHYCTL_A33,
 574         .dedicated_clocks = true,
 575         .enable_pmu_unk1 = true,
 576         .phy0_dual_route = true,
 577 };
 578
 579 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
 580         .num_phys = 3,
 581         .type = sun8i_r40_phy,
 582         .disc_thresh = 3,
 583         .phyctl_offset = REG_PHYCTL_A33,
 584         .dedicated_clocks = true,
 585         .enable_pmu_unk1 = true,
 586         .phy0_dual_route = true,
 587 };
 588
 589 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 590         .num_phys = 1,
 591         .type = sun8i_v3s_phy,
 592         .disc_thresh = 3,
 593         .phyctl_offset = REG_PHYCTL_A33,
 594         .dedicated_clocks = true,
 595         .enable_pmu_unk1 = true,
 596         .phy0_dual_route = true,
 597 };
 598
 599 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 600         .num_phys = 2,
 601         .type = sun50i_a64_phy,
 602         .disc_thresh = 3,
 603         .phyctl_offset = REG_PHYCTL_A33,
 604         .dedicated_clocks = true,
 605         .enable_pmu_unk1 = true,
 606         .phy0_dual_route = true,
 607 };
 608
 609 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 610         .num_phys = 4,
 611         .type = sun50i_h6_phy,
 612         .disc_thresh = 3,
 613         .phyctl_offset = REG_PHYCTL_A33,
 614         .dedicated_clocks = true,
 615         .enable_pmu_unk1 = true,
 616         .phy0_dual_route = true,
 617         .missing_phys = BIT(1) | BIT(2),
 618 };
 619
 620 static const struct udevice_id sun4i_usb_phy_ids[] = {
 621         { .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
 622         { .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
 623         { .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
 624         { .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
 625         { .compatible = "allwinner,sun8i-a23-usb-phy", .data = (ulong)&sun8i_a23_cfg },
 626         { .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
 627         { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 628         { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 629         { .compatible = "allwinner,sun8i-r40-usb-phy", .data = (ulong)&sun8i_r40_cfg },
 630         { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
 631         { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 632         { .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
 633         { }
 634 };
 635
 636 U_BOOT_DRIVER(sun4i_usb_phy) = {
 637         .name   = "sun4i_usb_phy",
 638         .id     = UCLASS_PHY,
 639         .of_match = sun4i_usb_phy_ids,
 640         .ops = &sun4i_usb_phy_ops,
 641         .probe = sun4i_usb_phy_probe,
 642         .platdata_auto_alloc_size = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
 643         .priv_auto_alloc_size = sizeof(struct sun4i_usb_phy_data),
 644 };