drivers/phy/allwinner/phy-sun4i-usb.c

   1 /*
   2  * Allwinner sun4i USB PHY driver
   3  *
   4  * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
   5  * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
   6  * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
   7  *
   8  * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <log.h>
  17 #include <dm/device.h>
  18 #include <generic-phy.h>
  19 #include <phy-sun4i-usb.h>
  20 #include <reset.h>
  21 #include <asm/gpio.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/cpu.h>
  25 #include <dm/device_compat.h>
  26 #include <linux/err.h>
  27
  28 #define REG_ISCR                        0x00
  29 #define REG_PHYCTL_A10                  0x04
  30 #define REG_PHYBIST                     0x08
  31 #define REG_PHYTUNE                     0x0c
  32 #define REG_PHYCTL_A33                  0x10
  33 #define REG_PHY_OTGCTL                  0x20
  34 #define REG_PMU_UNK1                    0x10
  35
  36 /* Common Control Bits for Both PHYs */
  37 #define PHY_PLL_BW                      0x03
  38 #define PHY_RES45_CAL_EN                0x0c
  39
  40 /* Private Control Bits for Each PHY */
  41 #define PHY_TX_AMPLITUDE_TUNE           0x20
  42 #define PHY_TX_SLEWRATE_TUNE            0x22
  43 #define PHY_DISCON_TH_SEL               0x2a
  44 #define PHY_SQUELCH_DETECT              0x3c
  45
  46 #define PHYCTL_DATA                     BIT(7)
  47 #define OTGCTL_ROUTE_MUSB               BIT(0)
  48
  49 #define PHY_TX_RATE                     BIT(4)
  50 #define PHY_TX_MAGNITUDE                BIT(2)
  51 #define PHY_TX_AMPLITUDE_LEN            5
  52
  53 #define PHY_RES45_CAL_DATA              BIT(0)
  54 #define PHY_RES45_CAL_LEN               1
  55 #define PHY_DISCON_TH_LEN               2
  56
  57 #define SUNXI_AHB_ICHR8_EN              BIT(10)
  58 #define SUNXI_AHB_INCR4_BURST_EN        BIT(9)
  59 #define SUNXI_AHB_INCRX_ALIGN_EN        BIT(8)
  60 #define SUNXI_ULPI_BYPASS_EN            BIT(0)
  61
  62 /* A83T specific control bits for PHY0 */
  63 #define PHY_CTL_VBUSVLDEXT              BIT(5)
  64 #define PHY_CTL_SIDDQ                   BIT(3)
  65
  66 /* A83T specific control bits for PHY2 HSIC */
  67 #define SUNXI_EHCI_HS_FORCE             BIT(20)
  68 #define SUNXI_HSIC_CONNECT_INT          BIT(16)
  69 #define SUNXI_HSIC                      BIT(1)
  70
  71 #define MAX_PHYS                        4
  72
  73 enum sun4i_usb_phy_type {
  74         sun4i_a10_phy,
  75         sun6i_a31_phy,
  76         sun8i_a33_phy,
  77         sun8i_a83t_phy,
  78         sun8i_h3_phy,
  79         sun8i_r40_phy,
  80         sun8i_v3s_phy,
  81         sun50i_a64_phy,
  82         sun50i_h6_phy,
  83 };
  84
  85 struct sun4i_usb_phy_cfg {
  86         int num_phys;
  87         enum sun4i_usb_phy_type type;
  88         u32 disc_thresh;
  89         u8 phyctl_offset;
  90         bool dedicated_clocks;
  91         bool enable_pmu_unk1;
  92         bool phy0_dual_route;
  93         int missing_phys;
  94 };
  95
  96 struct sun4i_usb_phy_info {
  97         const char *gpio_vbus;
  98         const char *gpio_vbus_det;
  99         const char *gpio_id_det;
 100 } phy_info[] = {
 101         {
 102                 .gpio_vbus = CONFIG_USB0_VBUS_PIN,
 103                 .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
 104                 .gpio_id_det = CONFIG_USB0_ID_DET,
 105         },
 106         {
 107                 .gpio_vbus = CONFIG_USB1_VBUS_PIN,
 108                 .gpio_vbus_det = NULL,
 109                 .gpio_id_det = NULL,
 110         },
 111         {
 112                 .gpio_vbus = CONFIG_USB2_VBUS_PIN,
 113                 .gpio_vbus_det = NULL,
 114                 .gpio_id_det = NULL,
 115         },
 116         {
 117                 .gpio_vbus = CONFIG_USB3_VBUS_PIN,
 118                 .gpio_vbus_det = NULL,
 119                 .gpio_id_det = NULL,
 120         },
 121 };
 122
 123 struct sun4i_usb_phy_plat {
 124         void __iomem *pmu;
 125         int power_on_count;
 126         int gpio_vbus;
 127         int gpio_vbus_det;
 128         int gpio_id_det;
 129         struct clk clocks;
 130         struct reset_ctl resets;
 131         int id;
 132 };
 133
 134 struct sun4i_usb_phy_data {
 135         void __iomem *base;
 136         const struct sun4i_usb_phy_cfg *cfg;
 137         struct sun4i_usb_phy_plat *usb_phy;
 138 };
 139
 140 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
 141
 142 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
 143 {
 144         struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
 145         struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
 146         u32 temp, usbc_bit = BIT(usb_phy->id * 2);
 147         void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
 148         int i;
 149
 150         if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
 151                 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
 152                 writel(0, phyctl);
 153         }
 154
 155         for (i = 0; i < len; i++) {
 156                 temp = readl(phyctl);
 157
 158                 /* clear the address portion */
 159                 temp &= ~(0xff << 8);
 160
 161                 /* set the address */
 162                 temp |= ((addr + i) << 8);
 163                 writel(temp, phyctl);
 164
 165                 /* set the data bit and clear usbc bit*/
 166                 temp = readb(phyctl);
 167                 if (data & 0x1)
 168                         temp |= PHYCTL_DATA;
 169                 else
 170                         temp &= ~PHYCTL_DATA;
 171                 temp &= ~usbc_bit;
 172                 writeb(temp, phyctl);
 173
 174                 /* pulse usbc_bit */
 175                 temp = readb(phyctl);
 176                 temp |= usbc_bit;
 177                 writeb(temp, phyctl);
 178
 179                 temp = readb(phyctl);
 180                 temp &= ~usbc_bit;
 181                 writeb(temp, phyctl);
 182
 183                 data >>= 1;
 184         }
 185 }
 186
 187 static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
 188 {
 189         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 190         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 191         u32 bits, reg_value;
 192
 193         if (!usb_phy->pmu)
 194                 return;
 195
 196         bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 197                 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 198
 199         /* A83T USB2 is HSIC */
 200         if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
 201                 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
 202                         SUNXI_HSIC;
 203
 204         reg_value = readl(usb_phy->pmu);
 205
 206         if (enable)
 207                 reg_value |= bits;
 208         else
 209                 reg_value &= ~bits;
 210
 211         writel(reg_value, usb_phy->pmu);
 212 }
 213
 214 static int sun4i_usb_phy_power_on(struct phy *phy)
 215 {
 216         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 217         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 218
 219         if (initial_usb_scan_delay) {
 220                 mdelay(initial_usb_scan_delay);
 221                 initial_usb_scan_delay = 0;
 222         }
 223
 224         usb_phy->power_on_count++;
 225         if (usb_phy->power_on_count != 1)
 226                 return 0;
 227
 228         if (usb_phy->gpio_vbus >= 0)
 229                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
 230
 231         return 0;
 232 }
 233
 234 static int sun4i_usb_phy_power_off(struct phy *phy)
 235 {
 236         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 237         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 238
 239         usb_phy->power_on_count--;
 240         if (usb_phy->power_on_count != 0)
 241                 return 0;
 242
 243         if (usb_phy->gpio_vbus >= 0)
 244                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
 245
 246         return 0;
 247 }
 248
 249 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
 250 {
 251         u32 regval;
 252
 253         regval = readl(data->base + REG_PHY_OTGCTL);
 254         if (!id_det) {
 255                 /* Host mode. Route phy0 to EHCI/OHCI */
 256                 regval &= ~OTGCTL_ROUTE_MUSB;
 257         } else {
 258                 /* Peripheral mode. Route phy0 to MUSB */
 259                 regval |= OTGCTL_ROUTE_MUSB;
 260         }
 261         writel(regval, data->base + REG_PHY_OTGCTL);
 262 }
 263
 264 static int sun4i_usb_phy_init(struct phy *phy)
 265 {
 266         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 267         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 268         u32 val;
 269         int ret;
 270
 271         ret = clk_enable(&usb_phy->clocks);
 272         if (ret) {
 273                 dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id);
 274                 return ret;
 275         }
 276
 277         ret = reset_deassert(&usb_phy->resets);
 278         if (ret) {
 279                 dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id);
 280                 return ret;
 281         }
 282
 283         if (data->cfg->type == sun8i_a83t_phy) {
 284                 if (phy->id == 0) {
 285                         val = readl(data->base + data->cfg->phyctl_offset);
 286                         val |= PHY_CTL_VBUSVLDEXT;
 287                         val &= ~PHY_CTL_SIDDQ;
 288                         writel(val, data->base + data->cfg->phyctl_offset);
 289                 }
 290         } else {
 291                 if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
 292                         val = readl(usb_phy->pmu + REG_PMU_UNK1);
 293                         writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
 294                 }
 295
 296                 if (usb_phy->id == 0)
 297                         sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
 298                                             PHY_RES45_CAL_DATA,
 299                                             PHY_RES45_CAL_LEN);
 300
 301                 /* Adjust PHY's magnitude and rate */
 302                 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
 303                                     PHY_TX_MAGNITUDE | PHY_TX_RATE,
 304                                     PHY_TX_AMPLITUDE_LEN);
 305
 306                 /* Disconnect threshold adjustment */
 307                 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
 308                                     data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
 309         }
 310
 311         sun4i_usb_phy_passby(phy, true);
 312
 313         sun4i_usb_phy0_reroute(data, true);
 314
 315         return 0;
 316 }
 317
 318 static int sun4i_usb_phy_exit(struct phy *phy)
 319 {
 320         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 321         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 322         int ret;
 323
 324         if (phy->id == 0) {
 325                 if (data->cfg->type == sun8i_a83t_phy) {
 326                         void __iomem *phyctl = data->base +
 327                                 data->cfg->phyctl_offset;
 328
 329                         writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
 330                 }
 331         }
 332
 333         sun4i_usb_phy_passby(phy, false);
 334
 335         ret = clk_disable(&usb_phy->clocks);
 336         if (ret) {
 337                 dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id);
 338                 return ret;
 339         }
 340
 341         ret = reset_assert(&usb_phy->resets);
 342         if (ret) {
 343                 dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id);
 344                 return ret;
 345         }
 346
 347         return 0;
 348 }
 349
 350 static int sun4i_usb_phy_xlate(struct phy *phy,
 351                                struct ofnode_phandle_args *args)
 352 {
 353         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 354
 355         if (args->args_count >= data->cfg->num_phys)
 356                 return -EINVAL;
 357
 358         if (data->cfg->missing_phys & BIT(args->args[0]))
 359                 return -ENODEV;
 360
 361         if (args->args_count)
 362                 phy->id = args->args[0];
 363         else
 364                 phy->id = 0;
 365
 366         debug("%s: phy_id = %ld\n", __func__, phy->id);
 367         return 0;
 368 }
 369
 370 int sun4i_usb_phy_vbus_detect(struct phy *phy)
 371 {
 372         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 373         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 374         int err, retries = 3;
 375
 376         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 377
 378         if (usb_phy->gpio_vbus_det < 0)
 379                 return usb_phy->gpio_vbus_det;
 380
 381         err = gpio_get_value(usb_phy->gpio_vbus_det);
 382         /*
 383          * Vbus may have been provided by the board and just been turned of
 384          * some milliseconds ago on reset, what we're measuring then is a
 385          * residual charge on Vbus, sleep a bit and try again.
 386          */
 387         while (err > 0 && retries--) {
 388                 mdelay(100);
 389                 err = gpio_get_value(usb_phy->gpio_vbus_det);
 390         }
 391
 392         return err;
 393 }
 394
 395 int sun4i_usb_phy_id_detect(struct phy *phy)
 396 {
 397         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 398         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 399
 400         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 401
 402         if (usb_phy->gpio_id_det < 0)
 403                 return usb_phy->gpio_id_det;
 404
 405         return gpio_get_value(usb_phy->gpio_id_det);
 406 }
 407
 408 void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
 409 {
 410         sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
 411 }
 412
 413 static struct phy_ops sun4i_usb_phy_ops = {
 414         .of_xlate = sun4i_usb_phy_xlate,
 415         .init = sun4i_usb_phy_init,
 416         .power_on = sun4i_usb_phy_power_on,
 417         .power_off = sun4i_usb_phy_power_off,
 418         .exit = sun4i_usb_phy_exit,
 419 };
 420
 421 static int sun4i_usb_phy_probe(struct udevice *dev)
 422 {
 423         struct sun4i_usb_phy_plat *plat = dev_get_platdata(dev);
 424         struct sun4i_usb_phy_data *data = dev_get_priv(dev);
 425         int i, ret;
 426
 427         data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
 428         if (!data->cfg)
 429                 return -EINVAL;
 430
 431         data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
 432         if (IS_ERR(data->base))
 433                 return PTR_ERR(data->base);
 434
 435         data->usb_phy = plat;
 436         for (i = 0; i < data->cfg->num_phys; i++) {
 437                 struct sun4i_usb_phy_plat *phy = &plat[i];
 438                 struct sun4i_usb_phy_info *info = &phy_info[i];
 439                 char name[16];
 440
 441                 if (data->cfg->missing_phys & BIT(i))
 442                         continue;
 443
 444                 phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
 445                 if (phy->gpio_vbus >= 0) {
 446                         ret = gpio_request(phy->gpio_vbus, "usb_vbus");
 447                         if (ret)
 448                                 return ret;
 449                         ret = gpio_direction_output(phy->gpio_vbus, 0);
 450                         if (ret)
 451                                 return ret;
 452                 }
 453
 454                 phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
 455                 if (phy->gpio_vbus_det >= 0) {
 456                         ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
 457                         if (ret)
 458                                 return ret;
 459                         ret = gpio_direction_input(phy->gpio_vbus_det);
 460                         if (ret)
 461                                 return ret;
 462                 }
 463
 464                 phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
 465                 if (phy->gpio_id_det >= 0) {
 466                         ret = gpio_request(phy->gpio_id_det, "usb_id_det");
 467                         if (ret)
 468                                 return ret;
 469                         ret = gpio_direction_input(phy->gpio_id_det);
 470                         if (ret)
 471                                 return ret;
 472                         sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 473                 }
 474
 475                 if (data->cfg->dedicated_clocks)
 476                         snprintf(name, sizeof(name), "usb%d_phy", i);
 477                 else
 478                         strlcpy(name, "usb_phy", sizeof(name));
 479
 480                 ret = clk_get_by_name(dev, name, &phy->clocks);
 481                 if (ret) {
 482                         dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
 483                         return ret;
 484                 }
 485
 486                 snprintf(name, sizeof(name), "usb%d_reset", i);
 487                 ret = reset_get_by_name(dev, name, &phy->resets);
 488                 if (ret) {
 489                         dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
 490                         return ret;
 491                 }
 492
 493                 if (i || data->cfg->phy0_dual_route) {
 494                         snprintf(name, sizeof(name), "pmu%d", i);
 495                         phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
 496                         if (IS_ERR(phy->pmu))
 497                                 return PTR_ERR(phy->pmu);
 498                 }
 499
 500                 phy->id = i;
 501         };
 502
 503         debug("Allwinner Sun4I USB PHY driver loaded\n");
 504         return 0;
 505 }
 506
 507 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 508         .num_phys = 3,
 509         .type = sun4i_a10_phy,
 510         .disc_thresh = 3,
 511         .phyctl_offset = REG_PHYCTL_A10,
 512         .dedicated_clocks = false,
 513         .enable_pmu_unk1 = false,
 514 };
 515
 516 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 517         .num_phys = 2,
 518         .type = sun4i_a10_phy,
 519         .disc_thresh = 2,
 520         .phyctl_offset = REG_PHYCTL_A10,
 521         .dedicated_clocks = false,
 522         .enable_pmu_unk1 = false,
 523 };
 524
 525 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 526         .num_phys = 3,
 527         .type = sun6i_a31_phy,
 528         .disc_thresh = 3,
 529         .phyctl_offset = REG_PHYCTL_A10,
 530         .dedicated_clocks = true,
 531         .enable_pmu_unk1 = false,
 532 };
 533
 534 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 535         .num_phys = 3,
 536         .type = sun4i_a10_phy,
 537         .disc_thresh = 2,
 538         .phyctl_offset = REG_PHYCTL_A10,
 539         .dedicated_clocks = false,
 540         .enable_pmu_unk1 = false,
 541 };
 542
 543 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 544         .num_phys = 2,
 545         .type = sun4i_a10_phy,
 546         .disc_thresh = 3,
 547         .phyctl_offset = REG_PHYCTL_A10,
 548         .dedicated_clocks = true,
 549         .enable_pmu_unk1 = false,
 550 };
 551
 552 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 553         .num_phys = 2,
 554         .type = sun8i_a33_phy,
 555         .disc_thresh = 3,
 556         .phyctl_offset = REG_PHYCTL_A33,
 557         .dedicated_clocks = true,
 558         .enable_pmu_unk1 = false,
 559 };
 560
 561 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 562         .num_phys = 3,
 563         .type = sun8i_a83t_phy,
 564         .phyctl_offset = REG_PHYCTL_A33,
 565         .dedicated_clocks = true,
 566 };
 567
 568 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 569         .num_phys = 4,
 570         .type = sun8i_h3_phy,
 571         .disc_thresh = 3,
 572         .phyctl_offset = REG_PHYCTL_A33,
 573         .dedicated_clocks = true,
 574         .enable_pmu_unk1 = true,
 575         .phy0_dual_route = true,
 576 };
 577
 578 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
 579         .num_phys = 3,
 580         .type = sun8i_r40_phy,
 581         .disc_thresh = 3,
 582         .phyctl_offset = REG_PHYCTL_A33,
 583         .dedicated_clocks = true,
 584         .enable_pmu_unk1 = true,
 585         .phy0_dual_route = true,
 586 };
 587
 588 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 589         .num_phys = 1,
 590         .type = sun8i_v3s_phy,
 591         .disc_thresh = 3,
 592         .phyctl_offset = REG_PHYCTL_A33,
 593         .dedicated_clocks = true,
 594         .enable_pmu_unk1 = true,
 595         .phy0_dual_route = true,
 596 };
 597
 598 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 599         .num_phys = 2,
 600         .type = sun50i_a64_phy,
 601         .disc_thresh = 3,
 602         .phyctl_offset = REG_PHYCTL_A33,
 603         .dedicated_clocks = true,
 604         .enable_pmu_unk1 = true,
 605         .phy0_dual_route = true,
 606 };
 607
 608 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 609         .num_phys = 4,
 610         .type = sun50i_h6_phy,
 611         .disc_thresh = 3,
 612         .phyctl_offset = REG_PHYCTL_A33,
 613         .dedicated_clocks = true,
 614         .enable_pmu_unk1 = true,
 615         .phy0_dual_route = true,
 616         .missing_phys = BIT(1) | BIT(2),
 617 };
 618
 619 static const struct udevice_id sun4i_usb_phy_ids[] = {
 620         { .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
 621         { .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
 622         { .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
 623         { .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
 624         { .compatible = "allwinner,sun8i-a23-usb-phy", .data = (ulong)&sun8i_a23_cfg },
 625         { .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
 626         { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 627         { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 628         { .compatible = "allwinner,sun8i-r40-usb-phy", .data = (ulong)&sun8i_r40_cfg },
 629         { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
 630         { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 631         { .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
 632         { }
 633 };
 634
 635 U_BOOT_DRIVER(sun4i_usb_phy) = {
 636         .name   = "sun4i_usb_phy",
 637         .id     = UCLASS_PHY,
 638         .of_match = sun4i_usb_phy_ids,
 639         .ops = &sun4i_usb_phy_ops,
 640         .probe = sun4i_usb_phy_probe,
 641         .platdata_auto_alloc_size = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
 642         .priv_auto_alloc_size = sizeof(struct sun4i_usb_phy_data),
 643 };