drivers/phy/allwinner/phy-sun4i-usb.c

   1 /*
   2  * Allwinner sun4i USB PHY driver
   3  *
   4  * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
   5  * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
   6  * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
   7  *
   8  * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <dm/device.h>
  17 #include <generic-phy.h>
  18 #include <phy-sun4i-usb.h>
  19 #include <reset.h>
  20 #include <asm/gpio.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/arch/cpu.h>
  24 #include <dm/device_compat.h>
  25 #include <linux/err.h>
  26
  27 #define REG_ISCR                        0x00
  28 #define REG_PHYCTL_A10                  0x04
  29 #define REG_PHYBIST                     0x08
  30 #define REG_PHYTUNE                     0x0c
  31 #define REG_PHYCTL_A33                  0x10
  32 #define REG_PHY_OTGCTL                  0x20
  33 #define REG_PMU_UNK1                    0x10
  34
  35 /* Common Control Bits for Both PHYs */
  36 #define PHY_PLL_BW                      0x03
  37 #define PHY_RES45_CAL_EN                0x0c
  38
  39 /* Private Control Bits for Each PHY */
  40 #define PHY_TX_AMPLITUDE_TUNE           0x20
  41 #define PHY_TX_SLEWRATE_TUNE            0x22
  42 #define PHY_DISCON_TH_SEL               0x2a
  43 #define PHY_SQUELCH_DETECT              0x3c
  44
  45 #define PHYCTL_DATA                     BIT(7)
  46 #define OTGCTL_ROUTE_MUSB               BIT(0)
  47
  48 #define PHY_TX_RATE                     BIT(4)
  49 #define PHY_TX_MAGNITUDE                BIT(2)
  50 #define PHY_TX_AMPLITUDE_LEN            5
  51
  52 #define PHY_RES45_CAL_DATA              BIT(0)
  53 #define PHY_RES45_CAL_LEN               1
  54 #define PHY_DISCON_TH_LEN               2
  55
  56 #define SUNXI_AHB_ICHR8_EN              BIT(10)
  57 #define SUNXI_AHB_INCR4_BURST_EN        BIT(9)
  58 #define SUNXI_AHB_INCRX_ALIGN_EN        BIT(8)
  59 #define SUNXI_ULPI_BYPASS_EN            BIT(0)
  60
  61 /* A83T specific control bits for PHY0 */
  62 #define PHY_CTL_VBUSVLDEXT              BIT(5)
  63 #define PHY_CTL_SIDDQ                   BIT(3)
  64
  65 /* A83T specific control bits for PHY2 HSIC */
  66 #define SUNXI_EHCI_HS_FORCE             BIT(20)
  67 #define SUNXI_HSIC_CONNECT_INT          BIT(16)
  68 #define SUNXI_HSIC                      BIT(1)
  69
  70 #define MAX_PHYS                        4
  71
  72 enum sun4i_usb_phy_type {
  73         sun4i_a10_phy,
  74         sun6i_a31_phy,
  75         sun8i_a33_phy,
  76         sun8i_a83t_phy,
  77         sun8i_h3_phy,
  78         sun8i_r40_phy,
  79         sun8i_v3s_phy,
  80         sun50i_a64_phy,
  81         sun50i_h6_phy,
  82 };
  83
  84 struct sun4i_usb_phy_cfg {
  85         int num_phys;
  86         enum sun4i_usb_phy_type type;
  87         u32 disc_thresh;
  88         u8 phyctl_offset;
  89         bool dedicated_clocks;
  90         bool enable_pmu_unk1;
  91         bool phy0_dual_route;
  92         int missing_phys;
  93 };
  94
  95 struct sun4i_usb_phy_info {
  96         const char *gpio_vbus;
  97         const char *gpio_vbus_det;
  98         const char *gpio_id_det;
  99 } phy_info[] = {
 100         {
 101                 .gpio_vbus = CONFIG_USB0_VBUS_PIN,
 102                 .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
 103                 .gpio_id_det = CONFIG_USB0_ID_DET,
 104         },
 105         {
 106                 .gpio_vbus = CONFIG_USB1_VBUS_PIN,
 107                 .gpio_vbus_det = NULL,
 108                 .gpio_id_det = NULL,
 109         },
 110         {
 111                 .gpio_vbus = CONFIG_USB2_VBUS_PIN,
 112                 .gpio_vbus_det = NULL,
 113                 .gpio_id_det = NULL,
 114         },
 115         {
 116                 .gpio_vbus = CONFIG_USB3_VBUS_PIN,
 117                 .gpio_vbus_det = NULL,
 118                 .gpio_id_det = NULL,
 119         },
 120 };
 121
 122 struct sun4i_usb_phy_plat {
 123         void __iomem *pmu;
 124         int power_on_count;
 125         int gpio_vbus;
 126         int gpio_vbus_det;
 127         int gpio_id_det;
 128         struct clk clocks;
 129         struct reset_ctl resets;
 130         int id;
 131 };
 132
 133 struct sun4i_usb_phy_data {
 134         void __iomem *base;
 135         const struct sun4i_usb_phy_cfg *cfg;
 136         struct sun4i_usb_phy_plat *usb_phy;
 137 };
 138
 139 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
 140
 141 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
 142 {
 143         struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
 144         struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
 145         u32 temp, usbc_bit = BIT(usb_phy->id * 2);
 146         void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
 147         int i;
 148
 149         if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
 150                 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
 151                 writel(0, phyctl);
 152         }
 153
 154         for (i = 0; i < len; i++) {
 155                 temp = readl(phyctl);
 156
 157                 /* clear the address portion */
 158                 temp &= ~(0xff << 8);
 159
 160                 /* set the address */
 161                 temp |= ((addr + i) << 8);
 162                 writel(temp, phyctl);
 163
 164                 /* set the data bit and clear usbc bit*/
 165                 temp = readb(phyctl);
 166                 if (data & 0x1)
 167                         temp |= PHYCTL_DATA;
 168                 else
 169                         temp &= ~PHYCTL_DATA;
 170                 temp &= ~usbc_bit;
 171                 writeb(temp, phyctl);
 172
 173                 /* pulse usbc_bit */
 174                 temp = readb(phyctl);
 175                 temp |= usbc_bit;
 176                 writeb(temp, phyctl);
 177
 178                 temp = readb(phyctl);
 179                 temp &= ~usbc_bit;
 180                 writeb(temp, phyctl);
 181
 182                 data >>= 1;
 183         }
 184 }
 185
 186 static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
 187 {
 188         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 189         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 190         u32 bits, reg_value;
 191
 192         if (!usb_phy->pmu)
 193                 return;
 194
 195         bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 196                 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 197
 198         /* A83T USB2 is HSIC */
 199         if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
 200                 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
 201                         SUNXI_HSIC;
 202
 203         reg_value = readl(usb_phy->pmu);
 204
 205         if (enable)
 206                 reg_value |= bits;
 207         else
 208                 reg_value &= ~bits;
 209
 210         writel(reg_value, usb_phy->pmu);
 211 }
 212
 213 static int sun4i_usb_phy_power_on(struct phy *phy)
 214 {
 215         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 216         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 217
 218         if (initial_usb_scan_delay) {
 219                 mdelay(initial_usb_scan_delay);
 220                 initial_usb_scan_delay = 0;
 221         }
 222
 223         usb_phy->power_on_count++;
 224         if (usb_phy->power_on_count != 1)
 225                 return 0;
 226
 227         if (usb_phy->gpio_vbus >= 0)
 228                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
 229
 230         return 0;
 231 }
 232
 233 static int sun4i_usb_phy_power_off(struct phy *phy)
 234 {
 235         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 236         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 237
 238         usb_phy->power_on_count--;
 239         if (usb_phy->power_on_count != 0)
 240                 return 0;
 241
 242         if (usb_phy->gpio_vbus >= 0)
 243                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
 244
 245         return 0;
 246 }
 247
 248 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
 249 {
 250         u32 regval;
 251
 252         regval = readl(data->base + REG_PHY_OTGCTL);
 253         if (!id_det) {
 254                 /* Host mode. Route phy0 to EHCI/OHCI */
 255                 regval &= ~OTGCTL_ROUTE_MUSB;
 256         } else {
 257                 /* Peripheral mode. Route phy0 to MUSB */
 258                 regval |= OTGCTL_ROUTE_MUSB;
 259         }
 260         writel(regval, data->base + REG_PHY_OTGCTL);
 261 }
 262
 263 static int sun4i_usb_phy_init(struct phy *phy)
 264 {
 265         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 266         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 267         u32 val;
 268         int ret;
 269
 270         ret = clk_enable(&usb_phy->clocks);
 271         if (ret) {
 272                 dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id);
 273                 return ret;
 274         }
 275
 276         ret = reset_deassert(&usb_phy->resets);
 277         if (ret) {
 278                 dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id);
 279                 return ret;
 280         }
 281
 282         if (data->cfg->type == sun8i_a83t_phy) {
 283                 if (phy->id == 0) {
 284                         val = readl(data->base + data->cfg->phyctl_offset);
 285                         val |= PHY_CTL_VBUSVLDEXT;
 286                         val &= ~PHY_CTL_SIDDQ;
 287                         writel(val, data->base + data->cfg->phyctl_offset);
 288                 }
 289         } else {
 290                 if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
 291                         val = readl(usb_phy->pmu + REG_PMU_UNK1);
 292                         writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
 293                 }
 294
 295                 if (usb_phy->id == 0)
 296                         sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
 297                                             PHY_RES45_CAL_DATA,
 298                                             PHY_RES45_CAL_LEN);
 299
 300                 /* Adjust PHY's magnitude and rate */
 301                 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
 302                                     PHY_TX_MAGNITUDE | PHY_TX_RATE,
 303                                     PHY_TX_AMPLITUDE_LEN);
 304
 305                 /* Disconnect threshold adjustment */
 306                 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
 307                                     data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
 308         }
 309
 310         sun4i_usb_phy_passby(phy, true);
 311
 312         sun4i_usb_phy0_reroute(data, true);
 313
 314         return 0;
 315 }
 316
 317 static int sun4i_usb_phy_exit(struct phy *phy)
 318 {
 319         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 320         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 321         int ret;
 322
 323         if (phy->id == 0) {
 324                 if (data->cfg->type == sun8i_a83t_phy) {
 325                         void __iomem *phyctl = data->base +
 326                                 data->cfg->phyctl_offset;
 327
 328                         writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
 329                 }
 330         }
 331
 332         sun4i_usb_phy_passby(phy, false);
 333
 334         ret = clk_disable(&usb_phy->clocks);
 335         if (ret) {
 336                 dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id);
 337                 return ret;
 338         }
 339
 340         ret = reset_assert(&usb_phy->resets);
 341         if (ret) {
 342                 dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id);
 343                 return ret;
 344         }
 345
 346         return 0;
 347 }
 348
 349 static int sun4i_usb_phy_xlate(struct phy *phy,
 350                                struct ofnode_phandle_args *args)
 351 {
 352         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 353
 354         if (args->args_count >= data->cfg->num_phys)
 355                 return -EINVAL;
 356
 357         if (data->cfg->missing_phys & BIT(args->args[0]))
 358                 return -ENODEV;
 359
 360         if (args->args_count)
 361                 phy->id = args->args[0];
 362         else
 363                 phy->id = 0;
 364
 365         debug("%s: phy_id = %ld\n", __func__, phy->id);
 366         return 0;
 367 }
 368
 369 int sun4i_usb_phy_vbus_detect(struct phy *phy)
 370 {
 371         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 372         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 373         int err, retries = 3;
 374
 375         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 376
 377         if (usb_phy->gpio_vbus_det < 0)
 378                 return usb_phy->gpio_vbus_det;
 379
 380         err = gpio_get_value(usb_phy->gpio_vbus_det);
 381         /*
 382          * Vbus may have been provided by the board and just been turned of
 383          * some milliseconds ago on reset, what we're measuring then is a
 384          * residual charge on Vbus, sleep a bit and try again.
 385          */
 386         while (err > 0 && retries--) {
 387                 mdelay(100);
 388                 err = gpio_get_value(usb_phy->gpio_vbus_det);
 389         }
 390
 391         return err;
 392 }
 393
 394 int sun4i_usb_phy_id_detect(struct phy *phy)
 395 {
 396         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 397         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 398
 399         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 400
 401         if (usb_phy->gpio_id_det < 0)
 402                 return usb_phy->gpio_id_det;
 403
 404         return gpio_get_value(usb_phy->gpio_id_det);
 405 }
 406
 407 void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
 408 {
 409         sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
 410 }
 411
 412 static struct phy_ops sun4i_usb_phy_ops = {
 413         .of_xlate = sun4i_usb_phy_xlate,
 414         .init = sun4i_usb_phy_init,
 415         .power_on = sun4i_usb_phy_power_on,
 416         .power_off = sun4i_usb_phy_power_off,
 417         .exit = sun4i_usb_phy_exit,
 418 };
 419
 420 static int sun4i_usb_phy_probe(struct udevice *dev)
 421 {
 422         struct sun4i_usb_phy_plat *plat = dev_get_platdata(dev);
 423         struct sun4i_usb_phy_data *data = dev_get_priv(dev);
 424         int i, ret;
 425
 426         data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
 427         if (!data->cfg)
 428                 return -EINVAL;
 429
 430         data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
 431         if (IS_ERR(data->base))
 432                 return PTR_ERR(data->base);
 433
 434         data->usb_phy = plat;
 435         for (i = 0; i < data->cfg->num_phys; i++) {
 436                 struct sun4i_usb_phy_plat *phy = &plat[i];
 437                 struct sun4i_usb_phy_info *info = &phy_info[i];
 438                 char name[16];
 439
 440                 if (data->cfg->missing_phys & BIT(i))
 441                         continue;
 442
 443                 phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
 444                 if (phy->gpio_vbus >= 0) {
 445                         ret = gpio_request(phy->gpio_vbus, "usb_vbus");
 446                         if (ret)
 447                                 return ret;
 448                         ret = gpio_direction_output(phy->gpio_vbus, 0);
 449                         if (ret)
 450                                 return ret;
 451                 }
 452
 453                 phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
 454                 if (phy->gpio_vbus_det >= 0) {
 455                         ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
 456                         if (ret)
 457                                 return ret;
 458                         ret = gpio_direction_input(phy->gpio_vbus_det);
 459                         if (ret)
 460                                 return ret;
 461                 }
 462
 463                 phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
 464                 if (phy->gpio_id_det >= 0) {
 465                         ret = gpio_request(phy->gpio_id_det, "usb_id_det");
 466                         if (ret)
 467                                 return ret;
 468                         ret = gpio_direction_input(phy->gpio_id_det);
 469                         if (ret)
 470                                 return ret;
 471                         sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 472                 }
 473
 474                 if (data->cfg->dedicated_clocks)
 475                         snprintf(name, sizeof(name), "usb%d_phy", i);
 476                 else
 477                         strlcpy(name, "usb_phy", sizeof(name));
 478
 479                 ret = clk_get_by_name(dev, name, &phy->clocks);
 480                 if (ret) {
 481                         dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
 482                         return ret;
 483                 }
 484
 485                 snprintf(name, sizeof(name), "usb%d_reset", i);
 486                 ret = reset_get_by_name(dev, name, &phy->resets);
 487                 if (ret) {
 488                         dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
 489                         return ret;
 490                 }
 491
 492                 if (i || data->cfg->phy0_dual_route) {
 493                         snprintf(name, sizeof(name), "pmu%d", i);
 494                         phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
 495                         if (IS_ERR(phy->pmu))
 496                                 return PTR_ERR(phy->pmu);
 497                 }
 498
 499                 phy->id = i;
 500         };
 501
 502         debug("Allwinner Sun4I USB PHY driver loaded\n");
 503         return 0;
 504 }
 505
 506 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 507         .num_phys = 3,
 508         .type = sun4i_a10_phy,
 509         .disc_thresh = 3,
 510         .phyctl_offset = REG_PHYCTL_A10,
 511         .dedicated_clocks = false,
 512         .enable_pmu_unk1 = false,
 513 };
 514
 515 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 516         .num_phys = 2,
 517         .type = sun4i_a10_phy,
 518         .disc_thresh = 2,
 519         .phyctl_offset = REG_PHYCTL_A10,
 520         .dedicated_clocks = false,
 521         .enable_pmu_unk1 = false,
 522 };
 523
 524 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 525         .num_phys = 3,
 526         .type = sun6i_a31_phy,
 527         .disc_thresh = 3,
 528         .phyctl_offset = REG_PHYCTL_A10,
 529         .dedicated_clocks = true,
 530         .enable_pmu_unk1 = false,
 531 };
 532
 533 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 534         .num_phys = 3,
 535         .type = sun4i_a10_phy,
 536         .disc_thresh = 2,
 537         .phyctl_offset = REG_PHYCTL_A10,
 538         .dedicated_clocks = false,
 539         .enable_pmu_unk1 = false,
 540 };
 541
 542 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 543         .num_phys = 2,
 544         .type = sun4i_a10_phy,
 545         .disc_thresh = 3,
 546         .phyctl_offset = REG_PHYCTL_A10,
 547         .dedicated_clocks = true,
 548         .enable_pmu_unk1 = false,
 549 };
 550
 551 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 552         .num_phys = 2,
 553         .type = sun8i_a33_phy,
 554         .disc_thresh = 3,
 555         .phyctl_offset = REG_PHYCTL_A33,
 556         .dedicated_clocks = true,
 557         .enable_pmu_unk1 = false,
 558 };
 559
 560 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 561         .num_phys = 3,
 562         .type = sun8i_a83t_phy,
 563         .phyctl_offset = REG_PHYCTL_A33,
 564         .dedicated_clocks = true,
 565 };
 566
 567 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 568         .num_phys = 4,
 569         .type = sun8i_h3_phy,
 570         .disc_thresh = 3,
 571         .phyctl_offset = REG_PHYCTL_A33,
 572         .dedicated_clocks = true,
 573         .enable_pmu_unk1 = true,
 574         .phy0_dual_route = true,
 575 };
 576
 577 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
 578         .num_phys = 3,
 579         .type = sun8i_r40_phy,
 580         .disc_thresh = 3,
 581         .phyctl_offset = REG_PHYCTL_A33,
 582         .dedicated_clocks = true,
 583         .enable_pmu_unk1 = true,
 584         .phy0_dual_route = true,
 585 };
 586
 587 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 588         .num_phys = 1,
 589         .type = sun8i_v3s_phy,
 590         .disc_thresh = 3,
 591         .phyctl_offset = REG_PHYCTL_A33,
 592         .dedicated_clocks = true,
 593         .enable_pmu_unk1 = true,
 594         .phy0_dual_route = true,
 595 };
 596
 597 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 598         .num_phys = 2,
 599         .type = sun50i_a64_phy,
 600         .disc_thresh = 3,
 601         .phyctl_offset = REG_PHYCTL_A33,
 602         .dedicated_clocks = true,
 603         .enable_pmu_unk1 = true,
 604         .phy0_dual_route = true,
 605 };
 606
 607 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 608         .num_phys = 4,
 609         .type = sun50i_h6_phy,
 610         .disc_thresh = 3,
 611         .phyctl_offset = REG_PHYCTL_A33,
 612         .dedicated_clocks = true,
 613         .enable_pmu_unk1 = true,
 614         .phy0_dual_route = true,
 615         .missing_phys = BIT(1) | BIT(2),
 616 };
 617
 618 static const struct udevice_id sun4i_usb_phy_ids[] = {
 619         { .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
 620         { .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
 621         { .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
 622         { .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
 623         { .compatible = "allwinner,sun8i-a23-usb-phy", .data = (ulong)&sun8i_a23_cfg },
 624         { .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
 625         { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 626         { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 627         { .compatible = "allwinner,sun8i-r40-usb-phy", .data = (ulong)&sun8i_r40_cfg },
 628         { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
 629         { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 630         { .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
 631         { }
 632 };
 633
 634 U_BOOT_DRIVER(sun4i_usb_phy) = {
 635         .name   = "sun4i_usb_phy",
 636         .id     = UCLASS_PHY,
 637         .of_match = sun4i_usb_phy_ids,
 638         .ops = &sun4i_usb_phy_ops,
 639         .probe = sun4i_usb_phy_probe,
 640         .platdata_auto_alloc_size = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
 641         .priv_auto_alloc_size = sizeof(struct sun4i_usb_phy_data),
 642 };