1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2020 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
12 #include <asm/arch/fsl_serdes.h>
15 #ifdef CONFIG_OF_BOARD_SETUP
16 #include <linux/libfdt.h>
17 #include <fdt_support.h>
19 #include <asm/arch/clock.h>
21 #include "pcie_layerscape.h"
22 #include "pcie_layerscape_fixup_common.h"
24 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
26 * Return next available LUT index.
28 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
30 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
31 return pcie->next_lut_index++;
33 return -ENOSPC; /* LUT is full */
36 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
40 out_be32(pcie->lut + offset, value);
42 out_le32(pcie->lut + offset, value);
46 * Program a single LUT entry
48 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
51 /* leave mask as all zeroes, want to match all bits */
52 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
53 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
57 * An msi-map is a property to be added to the pci controller
58 * node. It is a table, where each entry consists of 4 fields
61 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
62 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
64 static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
65 u32 devid, u32 streamid)
73 /* find pci controller node */
74 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
77 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
78 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
79 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
80 svr == SVR_LS2048A || svr == SVR_LS2044A ||
81 svr == SVR_LS2081A || svr == SVR_LS2041A)
82 compat = "fsl,ls2088a-pcie";
84 compat = CONFIG_FSL_PCIE_COMPAT;
86 nodeoffset = fdt_node_offset_by_compat_reg(blob,
87 compat, pcie->dbi_res.start);
93 /* get phandle to MSI controller */
94 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
96 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
100 phandle = fdt32_to_cpu(*prop);
102 /* set one msi-map row */
103 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
104 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
105 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
106 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
110 * An iommu-map is a property to be added to the pci controller
111 * node. It is a table, where each entry consists of 4 fields
114 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
115 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
117 static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
118 u32 devid, u32 streamid)
127 /* find pci controller node */
128 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
129 pcie->dbi_res.start);
130 if (nodeoffset < 0) {
131 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
132 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
133 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
134 svr == SVR_LS2048A || svr == SVR_LS2044A ||
135 svr == SVR_LS2081A || svr == SVR_LS2041A)
136 compat = "fsl,ls2088a-pcie";
138 compat = CONFIG_FSL_PCIE_COMPAT;
141 nodeoffset = fdt_node_offset_by_compat_reg(blob,
142 compat, pcie->dbi_res.start);
148 /* get phandle to iommu controller */
149 prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
151 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
152 __func__, pcie->idx);
156 /* set iommu-map row */
157 iommu_map[0] = cpu_to_fdt32(devid);
158 iommu_map[1] = *++prop;
159 iommu_map[2] = cpu_to_fdt32(streamid);
160 iommu_map[3] = cpu_to_fdt32(1);
163 fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
166 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
170 static void fdt_fixup_pcie_ls(void *blob)
172 struct udevice *dev, *bus;
173 struct ls_pcie *pcie;
178 /* Scan all known buses */
179 for (pci_find_first_device(&dev);
181 pci_find_next_device(&dev)) {
182 for (bus = dev; device_is_on_pci_bus(bus);)
184 pcie = dev_get_priv(bus);
186 streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
188 debug("ERROR: no stream ids free\n");
191 pcie->stream_id_cur++;
194 index = ls_pcie_next_lut_index(pcie);
196 debug("ERROR: no LUT indexes free\n");
200 /* the DT fixup must be relative to the hose first_busno */
201 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
202 /* map PCI b.d.f to streamID in LUT */
203 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
205 /* update msi-map in device tree */
206 fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
208 /* update iommu-map in device tree */
209 fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
212 pcie_board_fix_fdt(blob);
216 static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
222 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
223 pcie->dbi_res.start);
225 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
226 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
227 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
228 svr == SVR_LS2048A || svr == SVR_LS2044A ||
229 svr == SVR_LS2081A || svr == SVR_LS2041A)
230 compat = "fsl,ls2088a-pcie";
232 compat = CONFIG_FSL_PCIE_COMPAT;
234 off = fdt_node_offset_by_compat_reg(blob,
235 compat, pcie->dbi_res.start);
241 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
242 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
244 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
247 static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
251 off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
252 pcie->dbi_res.start);
256 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
257 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
259 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
262 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
264 ft_pcie_ep_fix(blob, pcie);
265 ft_pcie_rc_fix(blob, pcie);
268 /* Fixup Kernel DT for PCIe */
269 void ft_pci_setup_ls(void *blob, bd_t *bd)
271 struct ls_pcie *pcie;
273 list_for_each_entry(pcie, &ls_pcie_list, list)
274 ft_pcie_ls_setup(blob, pcie);
276 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
277 fdt_fixup_pcie_ls(blob);
281 #else /* !CONFIG_OF_BOARD_SETUP */
282 void ft_pci_setup_ls(void *blob, bd_t *bd)