drivers/pci/pci_auto_old.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * PCI autoconfiguration library (legacy version, do not change)
   4  *
   5  * Author: Matt Porter <mporter@mvista.com>
   6  *
   7  * Copyright 2000 MontaVista Software Inc.
   8  */
   9
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <pci.h>
  13
  14 /*
  15  * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
  16  * and change pci_auto.c.
  17  */
  18
  19 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  20 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  21 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  22 #endif
  23
  24 /*
  25  *
  26  */
  27
  28 void pciauto_setup_device(struct pci_controller *hose,
  29                           pci_dev_t dev, int bars_num,
  30                           struct pci_region *mem,
  31                           struct pci_region *prefetch,
  32                           struct pci_region *io)
  33 {
  34         u32 bar_response;
  35         pci_size_t bar_size;
  36         u16 cmdstat = 0;
  37         int bar, bar_nr = 0;
  38 #ifndef CONFIG_PCI_ENUM_ONLY
  39         u8 header_type;
  40         int rom_addr;
  41         pci_addr_t bar_value;
  42         struct pci_region *bar_res;
  43         int found_mem64 = 0;
  44 #endif
  45         u16 class;
  46
  47         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  48         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
  49
  50         for (bar = PCI_BASE_ADDRESS_0;
  51                 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  52                 /* Tickle the BAR and get the response */
  53 #ifndef CONFIG_PCI_ENUM_ONLY
  54                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
  55 #endif
  56                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
  57
  58                 /* If BAR is not implemented go to the next BAR */
  59                 if (!bar_response)
  60                         continue;
  61
  62 #ifndef CONFIG_PCI_ENUM_ONLY
  63                 found_mem64 = 0;
  64 #endif
  65
  66                 /* Check the BAR type and set our address mask */
  67                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  68                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
  69                                    & 0xffff) + 1;
  70 #ifndef CONFIG_PCI_ENUM_ONLY
  71                         bar_res = io;
  72 #endif
  73
  74                         debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
  75                               bar_nr, (unsigned long long)bar_size);
  76                 } else {
  77                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  78                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
  79                                 u32 bar_response_upper;
  80                                 u64 bar64;
  81
  82 #ifndef CONFIG_PCI_ENUM_ONLY
  83                                 pci_hose_write_config_dword(hose, dev, bar + 4,
  84                                         0xffffffff);
  85 #endif
  86                                 pci_hose_read_config_dword(hose, dev, bar + 4,
  87                                         &bar_response_upper);
  88
  89                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
  90
  91                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
  92 #ifndef CONFIG_PCI_ENUM_ONLY
  93                                 found_mem64 = 1;
  94 #endif
  95                         } else {
  96                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
  97                         }
  98 #ifndef CONFIG_PCI_ENUM_ONLY
  99                         if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
 100                                 bar_res = prefetch;
 101                         else
 102                                 bar_res = mem;
 103
 104                         debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
 105                               bar_nr, bar_res == prefetch ? "Prf" : "Mem",
 106                               (unsigned long long)bar_size);
 107 #endif
 108                 }
 109
 110 #ifndef CONFIG_PCI_ENUM_ONLY
 111                 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
 112                         /* Write it out and update our limit */
 113                         pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
 114
 115                         if (found_mem64) {
 116                                 bar += 4;
 117 #ifdef CONFIG_SYS_PCI_64BIT
 118                                 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 119 #else
 120                                 /*
 121                                  * If we are a 64-bit decoder then increment to the
 122                                  * upper 32 bits of the bar and force it to locate
 123                                  * in the lower 4GB of memory.
 124                                  */
 125                                 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 126 #endif
 127                         }
 128
 129                 }
 130 #endif
 131                 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 132                         PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 133
 134                 debug("\n");
 135
 136                 bar_nr++;
 137         }
 138
 139 #ifndef CONFIG_PCI_ENUM_ONLY
 140         /* Configure the expansion ROM address */
 141         pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 142         header_type &= 0x7f;
 143         if (header_type != PCI_HEADER_TYPE_CARDBUS) {
 144                 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
 145                            PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
 146                 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
 147                 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
 148                 if (bar_response) {
 149                         bar_size = -(bar_response & ~1);
 150                         debug("PCI Autoconfig: ROM, size=%#x, ",
 151                               (unsigned int)bar_size);
 152                         if (pciauto_region_allocate(mem, bar_size,
 153                                                     &bar_value) == 0) {
 154                                 pci_hose_write_config_dword(hose, dev, rom_addr,
 155                                                             bar_value);
 156                         }
 157                         cmdstat |= PCI_COMMAND_MEMORY;
 158                         debug("\n");
 159                 }
 160         }
 161 #endif
 162
 163         /* PCI_COMMAND_IO must be set for VGA device */
 164         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 165         if (class == PCI_CLASS_DISPLAY_VGA)
 166                 cmdstat |= PCI_COMMAND_IO;
 167
 168         pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 169         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 170                 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 171         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 172 }
 173
 174 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 175                                          pci_dev_t dev, int sub_bus)
 176 {
 177         struct pci_region *pci_mem;
 178         struct pci_region *pci_prefetch;
 179         struct pci_region *pci_io;
 180         u16 cmdstat, prefechable_64;
 181
 182         pci_mem = hose->pci_mem;
 183         pci_prefetch = hose->pci_prefetch;
 184         pci_io = hose->pci_io;
 185
 186         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 187         pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 188                                 &prefechable_64);
 189         prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 190
 191         /* Configure bus number registers */
 192         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
 193                                    PCI_BUS(dev) - hose->first_busno);
 194         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
 195                                    sub_bus - hose->first_busno);
 196         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 197
 198         if (pci_mem) {
 199                 /* Round memory allocator to 1MB boundary */
 200                 pciauto_region_align(pci_mem, 0x100000);
 201
 202                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 203                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
 204                                         (pci_mem->bus_lower & 0xfff00000) >> 16);
 205
 206                 cmdstat |= PCI_COMMAND_MEMORY;
 207         }
 208
 209         if (pci_prefetch) {
 210                 /* Round memory allocator to 1MB boundary */
 211                 pciauto_region_align(pci_prefetch, 0x100000);
 212
 213                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 214                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 215                                         (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 216                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 217 #ifdef CONFIG_SYS_PCI_64BIT
 218                         pci_hose_write_config_dword(hose, dev,
 219                                         PCI_PREF_BASE_UPPER32,
 220                                         pci_prefetch->bus_lower >> 32);
 221 #else
 222                         pci_hose_write_config_dword(hose, dev,
 223                                         PCI_PREF_BASE_UPPER32,
 224                                         0x0);
 225 #endif
 226
 227                 cmdstat |= PCI_COMMAND_MEMORY;
 228         } else {
 229                 /* We don't support prefetchable memory for now, so disable */
 230                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
 231                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 232                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
 233                         pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
 234                         pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
 235                 }
 236         }
 237
 238         if (pci_io) {
 239                 /* Round I/O allocator to 4KB boundary */
 240                 pciauto_region_align(pci_io, 0x1000);
 241
 242                 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
 243                                         (pci_io->bus_lower & 0x0000f000) >> 8);
 244                 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
 245                                         (pci_io->bus_lower & 0xffff0000) >> 16);
 246
 247                 cmdstat |= PCI_COMMAND_IO;
 248         }
 249
 250         /* Enable memory and I/O accesses, enable bus master */
 251         pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 252                                         cmdstat | PCI_COMMAND_MASTER);
 253 }
 254
 255 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 256                                           pci_dev_t dev, int sub_bus)
 257 {
 258         struct pci_region *pci_mem;
 259         struct pci_region *pci_prefetch;
 260         struct pci_region *pci_io;
 261
 262         pci_mem = hose->pci_mem;
 263         pci_prefetch = hose->pci_prefetch;
 264         pci_io = hose->pci_io;
 265
 266         /* Configure bus number registers */
 267         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
 268                                    sub_bus - hose->first_busno);
 269
 270         if (pci_mem) {
 271                 /* Round memory allocator to 1MB boundary */
 272                 pciauto_region_align(pci_mem, 0x100000);
 273
 274                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
 275                                 (pci_mem->bus_lower - 1) >> 16);
 276         }
 277
 278         if (pci_prefetch) {
 279                 u16 prefechable_64;
 280
 281                 pci_hose_read_config_word(hose, dev,
 282                                         PCI_PREF_MEMORY_LIMIT,
 283                                         &prefechable_64);
 284                 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 285
 286                 /* Round memory allocator to 1MB boundary */
 287                 pciauto_region_align(pci_prefetch, 0x100000);
 288
 289                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
 290                                 (pci_prefetch->bus_lower - 1) >> 16);
 291                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 292 #ifdef CONFIG_SYS_PCI_64BIT
 293                         pci_hose_write_config_dword(hose, dev,
 294                                         PCI_PREF_LIMIT_UPPER32,
 295                                         (pci_prefetch->bus_lower - 1) >> 32);
 296 #else
 297                         pci_hose_write_config_dword(hose, dev,
 298                                         PCI_PREF_LIMIT_UPPER32,
 299                                         0x0);
 300 #endif
 301         }
 302
 303         if (pci_io) {
 304                 /* Round I/O allocator to 4KB boundary */
 305                 pciauto_region_align(pci_io, 0x1000);
 306
 307                 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
 308                                 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
 309                 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
 310                                 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
 311         }
 312 }
 313
 314
 315 /*
 316  * HJF: Changed this to return int. I think this is required
 317  * to get the correct result when scanning bridges
 318  */
 319 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 320 {
 321         struct pci_region *pci_mem;
 322         struct pci_region *pci_prefetch;
 323         struct pci_region *pci_io;
 324         unsigned int sub_bus = PCI_BUS(dev);
 325         unsigned short class;
 326         int n;
 327
 328         pci_mem = hose->pci_mem;
 329         pci_prefetch = hose->pci_prefetch;
 330         pci_io = hose->pci_io;
 331
 332         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 333
 334         switch (class) {
 335         case PCI_CLASS_BRIDGE_PCI:
 336                 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
 337                       PCI_DEV(dev));
 338
 339                 pciauto_setup_device(hose, dev, 2, pci_mem,
 340                                      pci_prefetch, pci_io);
 341
 342                 /* Passing in current_busno allows for sibling P2P bridges */
 343                 hose->current_busno++;
 344                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 345                 /*
 346                  * need to figure out if this is a subordinate bridge on the bus
 347                  * to be able to properly set the pri/sec/sub bridge registers.
 348                  */
 349                 n = pci_hose_scan_bus(hose, hose->current_busno);
 350
 351                 /* figure out the deepest we've gone for this leg */
 352                 sub_bus = max((unsigned int)n, sub_bus);
 353                 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 354
 355                 sub_bus = hose->current_busno;
 356                 break;
 357
 358         case PCI_CLASS_BRIDGE_CARDBUS:
 359                 /*
 360                  * just do a minimal setup of the bridge,
 361                  * let the OS take care of the rest
 362                  */
 363                 pciauto_setup_device(hose, dev, 0, pci_mem,
 364                                      pci_prefetch, pci_io);
 365
 366                 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 367                       PCI_DEV(dev));
 368
 369                 hose->current_busno++;
 370                 break;
 371
 372 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 373         case PCI_CLASS_BRIDGE_OTHER:
 374                 debug("PCI Autoconfig: Skipping bridge device %d\n",
 375                       PCI_DEV(dev));
 376                 break;
 377 #endif
 378 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
 379         case PCI_CLASS_BRIDGE_OTHER:
 380                 /*
 381                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 382                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 383                  * device claiming resources io/mem/irq.. we only allow for
 384                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 385                  */
 386                 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
 387                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 388                         hose->pci_prefetch, hose->pci_io);
 389                 break;
 390 #endif
 391
 392         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 393                 debug("PCI AutoConfig: Found PowerPC device\n");
 394
 395         default:
 396                 pciauto_setup_device(hose, dev, 6, pci_mem,
 397                                      pci_prefetch, pci_io);
 398                 break;
 399         }
 400
 401         return sub_bus;
 402 }