drivers/pci/pci_auto.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * PCI autoconfiguration library
   4  *
   5  * Author: Matt Porter <mporter@mvista.com>
   6  *
   7  * Copyright 2000 MontaVista Software Inc.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <pci.h>
  15
  16 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  17 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  18 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  19 #endif
  20
  21 void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
  22                              struct pci_region *mem,
  23                              struct pci_region *prefetch, struct pci_region *io,
  24                              bool enum_only)
  25 {
  26         u32 bar_response;
  27         pci_size_t bar_size;
  28         u16 cmdstat = 0;
  29         int bar, bar_nr = 0;
  30         u8 header_type;
  31         int rom_addr;
  32         pci_addr_t bar_value;
  33         struct pci_region *bar_res = NULL;
  34         int found_mem64 = 0;
  35         u16 class;
  36
  37         dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
  38         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
  39                         PCI_COMMAND_MASTER;
  40
  41         for (bar = PCI_BASE_ADDRESS_0;
  42              bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  43                 int ret = 0;
  44
  45                 /* Tickle the BAR and get the response */
  46                 if (!enum_only)
  47                         dm_pci_write_config32(dev, bar, 0xffffffff);
  48                 dm_pci_read_config32(dev, bar, &bar_response);
  49
  50                 /* If BAR is not implemented go to the next BAR */
  51                 if (!bar_response)
  52                         continue;
  53
  54                 found_mem64 = 0;
  55
  56                 /* Check the BAR type and set our address mask */
  57                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  58                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
  59                                    & 0xffff) + 1;
  60                         if (!enum_only)
  61                                 bar_res = io;
  62
  63                         debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
  64                               bar_nr, (unsigned long long)bar_size);
  65                 } else {
  66                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  67                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
  68                                 u32 bar_response_upper;
  69                                 u64 bar64;
  70
  71                                 if (!enum_only) {
  72                                         dm_pci_write_config32(dev, bar + 4,
  73                                                               0xffffffff);
  74                                 }
  75                                 dm_pci_read_config32(dev, bar + 4,
  76                                                      &bar_response_upper);
  77
  78                                 bar64 = ((u64)bar_response_upper << 32) |
  79                                                 bar_response;
  80
  81                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
  82                                                 + 1;
  83                                 if (!enum_only)
  84                                         found_mem64 = 1;
  85                         } else {
  86                                 bar_size = (u32)(~(bar_response &
  87                                                 PCI_BASE_ADDRESS_MEM_MASK) + 1);
  88                         }
  89                         if (!enum_only) {
  90                                 if (prefetch && (bar_response &
  91                                             PCI_BASE_ADDRESS_MEM_PREFETCH)) {
  92                                         bar_res = prefetch;
  93                                 } else {
  94                                         bar_res = mem;
  95                                 }
  96                         }
  97
  98                         debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
  99                               bar_nr, bar_res == prefetch ? "Prf" : "Mem",
 100                               (unsigned long long)bar_size);
 101                 }
 102
 103                 if (!enum_only) {
 104                         ret = pciauto_region_allocate(bar_res, bar_size,
 105                                                       &bar_value, found_mem64);
 106                         if (ret)
 107                                 printf("PCI: Failed autoconfig bar %x\n", bar);
 108                 }
 109                 if (!enum_only && !ret) {
 110                         /* Write it out and update our limit */
 111                         dm_pci_write_config32(dev, bar, (u32)bar_value);
 112
 113                         if (found_mem64) {
 114                                 bar += 4;
 115 #ifdef CONFIG_SYS_PCI_64BIT
 116                                 dm_pci_write_config32(dev, bar,
 117                                                       (u32)(bar_value >> 32));
 118 #else
 119                                 /*
 120                                  * If we are a 64-bit decoder then increment to
 121                                  * the upper 32 bits of the bar and force it to
 122                                  * locate in the lower 4GB of memory.
 123                                  */
 124                                 dm_pci_write_config32(dev, bar, 0x00000000);
 125 #endif
 126                         }
 127                 }
 128
 129                 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 130                         PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 131
 132                 debug("\n");
 133
 134                 bar_nr++;
 135         }
 136
 137         if (!enum_only) {
 138                 /* Configure the expansion ROM address */
 139                 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
 140                 header_type &= 0x7f;
 141                 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
 142                         rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
 143                                 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
 144                         dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
 145                         dm_pci_read_config32(dev, rom_addr, &bar_response);
 146                         if (bar_response) {
 147                                 bar_size = -(bar_response & ~1);
 148                                 debug("PCI Autoconfig: ROM, size=%#x, ",
 149                                       (unsigned int)bar_size);
 150                                 if (pciauto_region_allocate(mem, bar_size,
 151                                                             &bar_value,
 152                                                             false) == 0) {
 153                                         dm_pci_write_config32(dev, rom_addr,
 154                                                               bar_value);
 155                                 }
 156                                 cmdstat |= PCI_COMMAND_MEMORY;
 157                                 debug("\n");
 158                         }
 159                 }
 160         }
 161
 162         /* PCI_COMMAND_IO must be set for VGA device */
 163         dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
 164         if (class == PCI_CLASS_DISPLAY_VGA)
 165                 cmdstat |= PCI_COMMAND_IO;
 166
 167         dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
 168         dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
 169                              CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 170         dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
 171 }
 172
 173 void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
 174 {
 175         struct pci_region *pci_mem;
 176         struct pci_region *pci_prefetch;
 177         struct pci_region *pci_io;
 178         u16 cmdstat, prefechable_64;
 179         struct udevice *ctlr = pci_get_controller(dev);
 180         struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
 181
 182         pci_mem = ctlr_hose->pci_mem;
 183         pci_prefetch = ctlr_hose->pci_prefetch;
 184         pci_io = ctlr_hose->pci_io;
 185
 186         dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
 187         dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
 188         prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 189
 190         /* Configure bus number registers */
 191         dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
 192                              PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq);
 193         dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq);
 194         dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
 195
 196         if (pci_mem) {
 197                 /* Round memory allocator to 1MB boundary */
 198                 pciauto_region_align(pci_mem, 0x100000);
 199
 200                 /*
 201                  * Set up memory and I/O filter limits, assume 32-bit
 202                  * I/O space
 203                  */
 204                 dm_pci_write_config16(dev, PCI_MEMORY_BASE,
 205                                       (pci_mem->bus_lower & 0xfff00000) >> 16);
 206
 207                 cmdstat |= PCI_COMMAND_MEMORY;
 208         }
 209
 210         if (pci_prefetch) {
 211                 /* Round memory allocator to 1MB boundary */
 212                 pciauto_region_align(pci_prefetch, 0x100000);
 213
 214                 /*
 215                  * Set up memory and I/O filter limits, assume 32-bit
 216                  * I/O space
 217                  */
 218                 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
 219                                 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 220                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 221 #ifdef CONFIG_SYS_PCI_64BIT
 222                         dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
 223                                               pci_prefetch->bus_lower >> 32);
 224 #else
 225                         dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
 226 #endif
 227
 228                 cmdstat |= PCI_COMMAND_MEMORY;
 229         } else {
 230                 /* We don't support prefetchable memory for now, so disable */
 231                 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
 232                 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 233                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
 234                         dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
 235                         dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
 236                 }
 237         }
 238
 239         if (pci_io) {
 240                 /* Round I/O allocator to 4KB boundary */
 241                 pciauto_region_align(pci_io, 0x1000);
 242
 243                 dm_pci_write_config8(dev, PCI_IO_BASE,
 244                                      (pci_io->bus_lower & 0x0000f000) >> 8);
 245                 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
 246                                       (pci_io->bus_lower & 0xffff0000) >> 16);
 247
 248                 cmdstat |= PCI_COMMAND_IO;
 249         }
 250
 251         /* Enable memory and I/O accesses, enable bus master */
 252         dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
 253 }
 254
 255 void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
 256 {
 257         struct pci_region *pci_mem;
 258         struct pci_region *pci_prefetch;
 259         struct pci_region *pci_io;
 260         struct udevice *ctlr = pci_get_controller(dev);
 261         struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
 262
 263         pci_mem = ctlr_hose->pci_mem;
 264         pci_prefetch = ctlr_hose->pci_prefetch;
 265         pci_io = ctlr_hose->pci_io;
 266
 267         /* Configure bus number registers */
 268         dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq);
 269
 270         if (pci_mem) {
 271                 /* Round memory allocator to 1MB boundary */
 272                 pciauto_region_align(pci_mem, 0x100000);
 273
 274                 dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
 275                                       (pci_mem->bus_lower - 1) >> 16);
 276         }
 277
 278         if (pci_prefetch) {
 279                 u16 prefechable_64;
 280
 281                 dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
 282                                      &prefechable_64);
 283                 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 284
 285                 /* Round memory allocator to 1MB boundary */
 286                 pciauto_region_align(pci_prefetch, 0x100000);
 287
 288                 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
 289                                       (pci_prefetch->bus_lower - 1) >> 16);
 290                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 291 #ifdef CONFIG_SYS_PCI_64BIT
 292                         dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
 293                                         (pci_prefetch->bus_lower - 1) >> 32);
 294 #else
 295                         dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
 296 #endif
 297         }
 298
 299         if (pci_io) {
 300                 /* Round I/O allocator to 4KB boundary */
 301                 pciauto_region_align(pci_io, 0x1000);
 302
 303                 dm_pci_write_config8(dev, PCI_IO_LIMIT,
 304                                 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
 305                 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
 306                                 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
 307         }
 308 }
 309
 310 /*
 311  * HJF: Changed this to return int. I think this is required
 312  * to get the correct result when scanning bridges
 313  */
 314 int dm_pciauto_config_device(struct udevice *dev)
 315 {
 316         struct pci_region *pci_mem;
 317         struct pci_region *pci_prefetch;
 318         struct pci_region *pci_io;
 319         unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
 320         unsigned short class;
 321         bool enum_only = false;
 322         struct udevice *ctlr = pci_get_controller(dev);
 323         struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
 324         int n;
 325
 326 #ifdef CONFIG_PCI_ENUM_ONLY
 327         enum_only = true;
 328 #endif
 329
 330         pci_mem = ctlr_hose->pci_mem;
 331         pci_prefetch = ctlr_hose->pci_prefetch;
 332         pci_io = ctlr_hose->pci_io;
 333
 334         dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
 335
 336         switch (class) {
 337         case PCI_CLASS_BRIDGE_PCI:
 338                 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
 339                       PCI_DEV(dm_pci_get_bdf(dev)));
 340
 341                 dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io,
 342                                         enum_only);
 343
 344                 n = dm_pci_hose_probe_bus(dev);
 345                 if (n < 0)
 346                         return n;
 347                 sub_bus = (unsigned int)n;
 348                 break;
 349
 350         case PCI_CLASS_BRIDGE_CARDBUS:
 351                 /*
 352                  * just do a minimal setup of the bridge,
 353                  * let the OS take care of the rest
 354                  */
 355                 dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io,
 356                                         enum_only);
 357
 358                 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 359                       PCI_DEV(dm_pci_get_bdf(dev)));
 360
 361                 break;
 362
 363 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 364         case PCI_CLASS_BRIDGE_OTHER:
 365                 debug("PCI Autoconfig: Skipping bridge device %d\n",
 366                       PCI_DEV(dm_pci_get_bdf(dev)));
 367                 break;
 368 #endif
 369 #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
 370                 !defined(CONFIG_TARGET_CADDY2)
 371         case PCI_CLASS_BRIDGE_OTHER:
 372                 /*
 373                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 374                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 375                  * device claiming resources io/mem/irq.. we only allow for
 376                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 377                  */
 378                 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
 379                 dm_pciauto_setup_device(dev, 0, hose->pci_mem,
 380                                         hose->pci_prefetch, hose->pci_io,
 381                                         enum_only);
 382                 break;
 383 #endif
 384
 385         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 386                 debug("PCI AutoConfig: Found PowerPC device\n");
 387                 /* fall through */
 388
 389         default:
 390                 dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
 391                                         enum_only);
 392                 break;
 393         }
 394
 395         return sub_bus;
 396 }