drivers/net/ti/keystone_net.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Ethernet driver for TI K2HK EVM.
   4  *
   5  * (C) Copyright 2012-2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8 #include <common.h>
   9 #include <command.h>
  10 #include <console.h>
  11
  12 #include <dm.h>
  13 #include <dm/lists.h>
  14
  15 #include <net.h>
  16 #include <phy.h>
  17 #include <errno.h>
  18 #include <miiphy.h>
  19 #include <malloc.h>
  20 #include <asm/ti-common/keystone_nav.h>
  21 #include <asm/ti-common/keystone_net.h>
  22 #include <asm/ti-common/keystone_serdes.h>
  23 #include <asm/arch/psc_defs.h>
  24 #include <linux/libfdt.h>
  25
  26 #include "cpsw_mdio.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
  31 #define emac_gigabit_enable(x)  keystone2_eth_gigabit_enable(x)
  32 #else
  33 #define emac_gigabit_enable(x)  /* no gigabit to enable */
  34 #endif
  35
  36 #define RX_BUFF_NUMS    24
  37 #define RX_BUFF_LEN     1520
  38 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
  39 #define SGMII_ANEG_TIMEOUT              4000
  40
  41 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
  42
  43 enum link_type {
  44         LINK_TYPE_SGMII_MAC_TO_MAC_AUTO         = 0,
  45         LINK_TYPE_SGMII_MAC_TO_PHY_MODE         = 1,
  46         LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE  = 2,
  47         LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE       = 3,
  48         LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
  49         LINK_TYPE_RGMII_LINK_MAC_PHY            = 5,
  50         LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED     = 6,
  51         LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO    = 7,
  52         LINK_TYPE_10G_MAC_TO_PHY_MODE           = 10,
  53         LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE    = 11,
  54 };
  55
  56 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
  57                          ((mac)[2] << 16) | ((mac)[3] << 24))
  58 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
  59
  60 #ifdef CONFIG_KSNET_NETCP_V1_0
  61
  62 #define EMAC_EMACSW_BASE_OFS            0x90800
  63 #define EMAC_EMACSW_PORT_BASE_OFS       (EMAC_EMACSW_BASE_OFS + 0x60)
  64
  65 /* CPSW Switch slave registers */
  66 #define CPGMACSL_REG_SA_LO              0x10
  67 #define CPGMACSL_REG_SA_HI              0x14
  68
  69 #define DEVICE_EMACSW_BASE(base, x)     ((base) + EMAC_EMACSW_PORT_BASE_OFS +  \
  70                                          (x) * 0x30)
  71
  72 #elif defined(CONFIG_KSNET_NETCP_V1_5)
  73
  74 #define EMAC_EMACSW_PORT_BASE_OFS       0x222000
  75
  76 /* CPSW Switch slave registers */
  77 #define CPGMACSL_REG_SA_LO              0x308
  78 #define CPGMACSL_REG_SA_HI              0x30c
  79
  80 #define DEVICE_EMACSW_BASE(base, x)     ((base) + EMAC_EMACSW_PORT_BASE_OFS +  \
  81                                          (x) * 0x1000)
  82
  83 #endif
  84
  85
  86 struct ks2_eth_priv {
  87         struct udevice                  *dev;
  88         struct phy_device               *phydev;
  89         struct mii_dev                  *mdio_bus;
  90         int                             phy_addr;
  91         phy_interface_t                 phy_if;
  92         int                             phy_of_handle;
  93         int                             sgmii_link_type;
  94         void                            *mdio_base;
  95         struct rx_buff_desc             net_rx_buffs;
  96         struct pktdma_cfg               *netcp_pktdma;
  97         void                            *hd;
  98         int                             slave_port;
  99         enum link_type                  link_type;
 100         bool                            emac_open;
 101         bool                            has_mdio;
 102 };
 103
 104 static void  __attribute__((unused))
 105         keystone2_eth_gigabit_enable(struct udevice *dev)
 106 {
 107         struct ks2_eth_priv *priv = dev_get_priv(dev);
 108
 109         /*
 110          * Check if link detected is giga-bit
 111          * If Gigabit mode detected, enable gigbit in MAC
 112          */
 113         if (priv->has_mdio) {
 114                 if (priv->phydev->speed != 1000)
 115                         return;
 116         }
 117
 118         writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
 119                      CPGMACSL_REG_CTL) |
 120                EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
 121                DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
 122 }
 123
 124 #ifdef CONFIG_SOC_K2G
 125 int keystone_rgmii_config(struct phy_device *phy_dev)
 126 {
 127         unsigned int i, status;
 128
 129         i = 0;
 130         do {
 131                 if (i > SGMII_ANEG_TIMEOUT) {
 132                         puts(" TIMEOUT !\n");
 133                         phy_dev->link = 0;
 134                         return 0;
 135                 }
 136
 137                 if (ctrlc()) {
 138                         puts("user interrupt!\n");
 139                         phy_dev->link = 0;
 140                         return -EINTR;
 141                 }
 142
 143                 if ((i++ % 500) == 0)
 144                         printf(".");
 145
 146                 udelay(1000);   /* 1 ms */
 147                 status = readl(RGMII_STATUS_REG);
 148         } while (!(status & RGMII_REG_STATUS_LINK));
 149
 150         puts(" done\n");
 151
 152         return 0;
 153 }
 154 #else
 155 int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
 156 {
 157         unsigned int i, status, mask;
 158         unsigned int mr_adv_ability, control;
 159
 160         switch (interface) {
 161         case SGMII_LINK_MAC_MAC_AUTONEG:
 162                 mr_adv_ability  = (SGMII_REG_MR_ADV_ENABLE |
 163                                    SGMII_REG_MR_ADV_LINK |
 164                                    SGMII_REG_MR_ADV_FULL_DUPLEX |
 165                                    SGMII_REG_MR_ADV_GIG_MODE);
 166                 control         = (SGMII_REG_CONTROL_MASTER |
 167                                    SGMII_REG_CONTROL_AUTONEG);
 168
 169                 break;
 170         case SGMII_LINK_MAC_PHY:
 171         case SGMII_LINK_MAC_PHY_FORCED:
 172                 mr_adv_ability  = SGMII_REG_MR_ADV_ENABLE;
 173                 control         = SGMII_REG_CONTROL_AUTONEG;
 174
 175                 break;
 176         case SGMII_LINK_MAC_MAC_FORCED:
 177                 mr_adv_ability  = (SGMII_REG_MR_ADV_ENABLE |
 178                                    SGMII_REG_MR_ADV_LINK |
 179                                    SGMII_REG_MR_ADV_FULL_DUPLEX |
 180                                    SGMII_REG_MR_ADV_GIG_MODE);
 181                 control         = SGMII_REG_CONTROL_MASTER;
 182
 183                 break;
 184         case SGMII_LINK_MAC_FIBER:
 185                 mr_adv_ability  = 0x20;
 186                 control         = SGMII_REG_CONTROL_AUTONEG;
 187
 188                 break;
 189         default:
 190                 mr_adv_ability  = SGMII_REG_MR_ADV_ENABLE;
 191                 control         = SGMII_REG_CONTROL_AUTONEG;
 192         }
 193
 194         __raw_writel(0, SGMII_CTL_REG(port));
 195
 196         /*
 197          * Wait for the SerDes pll to lock,
 198          * but don't trap if lock is never read
 199          */
 200         for (i = 0; i < 1000; i++)  {
 201                 udelay(2000);
 202                 status = __raw_readl(SGMII_STATUS_REG(port));
 203                 if ((status & SGMII_REG_STATUS_LOCK) != 0)
 204                         break;
 205         }
 206
 207         __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
 208         __raw_writel(control, SGMII_CTL_REG(port));
 209
 210
 211         mask = SGMII_REG_STATUS_LINK;
 212
 213         if (control & SGMII_REG_CONTROL_AUTONEG)
 214                 mask |= SGMII_REG_STATUS_AUTONEG;
 215
 216         status = __raw_readl(SGMII_STATUS_REG(port));
 217         if ((status & mask) == mask)
 218                 return 0;
 219
 220         printf("\n%s Waiting for SGMII auto negotiation to complete",
 221                phy_dev->dev->name);
 222         while ((status & mask) != mask) {
 223                 /*
 224                  * Timeout reached ?
 225                  */
 226                 if (i > SGMII_ANEG_TIMEOUT) {
 227                         puts(" TIMEOUT !\n");
 228                         phy_dev->link = 0;
 229                         return 0;
 230                 }
 231
 232                 if (ctrlc()) {
 233                         puts("user interrupt!\n");
 234                         phy_dev->link = 0;
 235                         return -EINTR;
 236                 }
 237
 238                 if ((i++ % 500) == 0)
 239                         printf(".");
 240
 241                 udelay(1000);   /* 1 ms */
 242                 status = __raw_readl(SGMII_STATUS_REG(port));
 243         }
 244         puts(" done\n");
 245
 246         return 0;
 247 }
 248 #endif
 249
 250 int mac_sl_reset(u32 port)
 251 {
 252         u32 i, v;
 253
 254         if (port >= DEVICE_N_GMACSL_PORTS)
 255                 return GMACSL_RET_INVALID_PORT;
 256
 257         /* Set the soft reset bit */
 258         writel(CPGMAC_REG_RESET_VAL_RESET,
 259                DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
 260
 261         /* Wait for the bit to clear */
 262         for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
 263                 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
 264                 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
 265                     CPGMAC_REG_RESET_VAL_RESET)
 266                         return GMACSL_RET_OK;
 267         }
 268
 269         /* Timeout on the reset */
 270         return GMACSL_RET_WARN_RESET_INCOMPLETE;
 271 }
 272
 273 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
 274 {
 275         u32 v, i;
 276         int ret = GMACSL_RET_OK;
 277
 278         if (port >= DEVICE_N_GMACSL_PORTS)
 279                 return GMACSL_RET_INVALID_PORT;
 280
 281         if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
 282                 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
 283                 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
 284         }
 285
 286         /* Must wait if the device is undergoing reset */
 287         for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
 288                 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
 289                 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
 290                     CPGMAC_REG_RESET_VAL_RESET)
 291                         break;
 292         }
 293
 294         if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
 295                 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
 296
 297         writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
 298         writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
 299
 300 #ifndef CONFIG_SOC_K2HK
 301         /* Map RX packet flow priority to 0 */
 302         writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
 303 #endif
 304
 305         return ret;
 306 }
 307
 308 int ethss_config(u32 ctl, u32 max_pkt_size)
 309 {
 310         u32 i;
 311
 312         /* Max length register */
 313         writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
 314
 315         /* Control register */
 316         writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
 317
 318         /* All statistics enabled by default */
 319         writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
 320                DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
 321
 322         /* Reset and enable the ALE */
 323         writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
 324                CPSW_REG_VAL_ALE_CTL_BYPASS,
 325                DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
 326
 327         /* All ports put into forward mode */
 328         for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
 329                 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
 330                        DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
 331
 332         return 0;
 333 }
 334
 335 int ethss_start(void)
 336 {
 337         int i;
 338         struct mac_sl_cfg cfg;
 339
 340         cfg.max_rx_len  = MAX_SIZE_STREAM_BUFFER;
 341         cfg.ctl         = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
 342
 343         for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
 344                 mac_sl_reset(i);
 345                 mac_sl_config(i, &cfg);
 346         }
 347
 348         return 0;
 349 }
 350
 351 int ethss_stop(void)
 352 {
 353         int i;
 354
 355         for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
 356                 mac_sl_reset(i);
 357
 358         return 0;
 359 }
 360
 361 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
 362         .clk = SERDES_CLOCK_156P25M,
 363         .rate = SERDES_RATE_5G,
 364         .rate_mode = SERDES_QUARTER_RATE,
 365         .intf = SERDES_PHY_SGMII,
 366         .loopback = 0,
 367 };
 368
 369 #ifndef CONFIG_SOC_K2G
 370 static void keystone2_net_serdes_setup(void)
 371 {
 372         ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
 373                         &ks2_serdes_sgmii_156p25mhz,
 374                         CONFIG_KSNET_SERDES_LANES_PER_SGMII);
 375
 376 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
 377         ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
 378                         &ks2_serdes_sgmii_156p25mhz,
 379                         CONFIG_KSNET_SERDES_LANES_PER_SGMII);
 380 #endif
 381
 382         /* wait till setup */
 383         udelay(5000);
 384 }
 385 #endif
 386
 387 static int ks2_eth_start(struct udevice *dev)
 388 {
 389         struct ks2_eth_priv *priv = dev_get_priv(dev);
 390
 391 #ifdef CONFIG_SOC_K2G
 392         keystone_rgmii_config(priv->phydev);
 393 #else
 394         keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
 395                               priv->sgmii_link_type);
 396 #endif
 397
 398         udelay(10000);
 399
 400         /* On chip switch configuration */
 401         ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
 402
 403         qm_init();
 404
 405         if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
 406                 pr_err("ksnav_init failed\n");
 407                 goto err_knav_init;
 408         }
 409
 410         /*
 411          * Streaming switch configuration. If not present this
 412          * statement is defined to void in target.h.
 413          * If present this is usually defined to a series of register writes
 414          */
 415         hw_config_streaming_switch();
 416
 417         if (priv->has_mdio) {
 418                 phy_startup(priv->phydev);
 419                 if (priv->phydev->link == 0) {
 420                         pr_err("phy startup failed\n");
 421                         goto err_phy_start;
 422                 }
 423         }
 424
 425         emac_gigabit_enable(dev);
 426
 427         ethss_start();
 428
 429         priv->emac_open = true;
 430
 431         return 0;
 432
 433 err_phy_start:
 434         ksnav_close(priv->netcp_pktdma);
 435 err_knav_init:
 436         qm_close();
 437
 438         return -EFAULT;
 439 }
 440
 441 static int ks2_eth_send(struct udevice *dev, void *packet, int length)
 442 {
 443         struct ks2_eth_priv *priv = dev_get_priv(dev);
 444
 445         genphy_update_link(priv->phydev);
 446         if (priv->phydev->link == 0)
 447                 return -1;
 448
 449         if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
 450                 length = EMAC_MIN_ETHERNET_PKT_SIZE;
 451
 452         return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
 453                           length, (priv->slave_port) << 16);
 454 }
 455
 456 static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 457 {
 458         struct ks2_eth_priv *priv = dev_get_priv(dev);
 459         int  pkt_size;
 460         u32 *pkt = NULL;
 461
 462         priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
 463         if (priv->hd == NULL)
 464                 return -EAGAIN;
 465
 466         *packetp = (uchar *)pkt;
 467
 468         return pkt_size;
 469 }
 470
 471 static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
 472                                    int length)
 473 {
 474         struct ks2_eth_priv *priv = dev_get_priv(dev);
 475
 476         ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
 477
 478         return 0;
 479 }
 480
 481 static void ks2_eth_stop(struct udevice *dev)
 482 {
 483         struct ks2_eth_priv *priv = dev_get_priv(dev);
 484
 485         if (!priv->emac_open)
 486                 return;
 487         ethss_stop();
 488
 489         ksnav_close(priv->netcp_pktdma);
 490         qm_close();
 491         phy_shutdown(priv->phydev);
 492         priv->emac_open = false;
 493 }
 494
 495 int ks2_eth_read_rom_hwaddr(struct udevice *dev)
 496 {
 497         struct ks2_eth_priv *priv = dev_get_priv(dev);
 498         struct eth_pdata *pdata = dev_get_platdata(dev);
 499         u32 maca = 0;
 500         u32 macb = 0;
 501
 502         /* Read the e-fuse mac address */
 503         if (priv->slave_port == 1) {
 504                 maca = __raw_readl(MAC_ID_BASE_ADDR);
 505                 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
 506         }
 507
 508         pdata->enetaddr[0] = (macb >>  8) & 0xff;
 509         pdata->enetaddr[1] = (macb >>  0) & 0xff;
 510         pdata->enetaddr[2] = (maca >> 24) & 0xff;
 511         pdata->enetaddr[3] = (maca >> 16) & 0xff;
 512         pdata->enetaddr[4] = (maca >>  8) & 0xff;
 513         pdata->enetaddr[5] = (maca >>  0) & 0xff;
 514
 515         return 0;
 516 }
 517
 518 int ks2_eth_write_hwaddr(struct udevice *dev)
 519 {
 520         struct ks2_eth_priv *priv = dev_get_priv(dev);
 521         struct eth_pdata *pdata = dev_get_platdata(dev);
 522
 523         writel(mac_hi(pdata->enetaddr),
 524                DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
 525                                   CPGMACSL_REG_SA_HI);
 526         writel(mac_lo(pdata->enetaddr),
 527                DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
 528                                   CPGMACSL_REG_SA_LO);
 529
 530         return 0;
 531 }
 532
 533 static int ks2_eth_probe(struct udevice *dev)
 534 {
 535         struct ks2_eth_priv *priv = dev_get_priv(dev);
 536         struct mii_dev *mdio_bus;
 537
 538         priv->dev = dev;
 539         priv->emac_open = false;
 540
 541         /* These clock enables has to be moved to common location */
 542         if (cpu_is_k2g())
 543                 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
 544
 545         /* By default, select PA PLL clock as PA clock source */
 546 #ifndef CONFIG_SOC_K2G
 547         if (psc_enable_module(KS2_LPSC_PA))
 548                 return -EACCES;
 549 #endif
 550         if (psc_enable_module(KS2_LPSC_CPGMAC))
 551                 return -EACCES;
 552         if (psc_enable_module(KS2_LPSC_CRYPTO))
 553                 return -EACCES;
 554
 555         if (cpu_is_k2e() || cpu_is_k2l())
 556                 pll_pa_clk_sel();
 557
 558         priv->net_rx_buffs.buff_ptr = rx_buffs;
 559         priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
 560         priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
 561
 562         if (priv->slave_port == 1) {
 563 #ifndef CONFIG_SOC_K2G
 564                 keystone2_net_serdes_setup();
 565 #endif
 566                 /*
 567                  * Register MDIO bus for slave 0 only, other slave have
 568                  * to re-use the same
 569                  */
 570                 mdio_bus = cpsw_mdio_init("ethernet-mdio",
 571                                           (u32)priv->mdio_base,
 572                                           EMAC_MDIO_CLOCK_FREQ,
 573                                           EMAC_MDIO_BUS_FREQ);
 574                 if (!mdio_bus) {
 575                         pr_err("MDIO alloc failed\n");
 576                         return -ENOMEM;
 577                 }
 578                 priv->mdio_bus = mdio_bus;
 579         } else {
 580                 /* Get the MDIO bus from slave 0 device */
 581                 struct ks2_eth_priv *parent_priv;
 582
 583                 parent_priv = dev_get_priv(dev->parent);
 584                 priv->mdio_bus = parent_priv->mdio_bus;
 585                 priv->mdio_base = parent_priv->mdio_base;
 586         }
 587
 588         priv->netcp_pktdma = &netcp_pktdma;
 589
 590         if (priv->has_mdio) {
 591                 priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
 592                                            dev, priv->phy_if);
 593 #ifdef CONFIG_DM_ETH
 594         if (priv->phy_of_handle)
 595                 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
 596 #endif
 597                 phy_config(priv->phydev);
 598         }
 599
 600         return 0;
 601 }
 602
 603 int ks2_eth_remove(struct udevice *dev)
 604 {
 605         struct ks2_eth_priv *priv = dev_get_priv(dev);
 606
 607         cpsw_mdio_free(priv->mdio_bus);
 608
 609         return 0;
 610 }
 611
 612 static const struct eth_ops ks2_eth_ops = {
 613         .start                  = ks2_eth_start,
 614         .send                   = ks2_eth_send,
 615         .recv                   = ks2_eth_recv,
 616         .free_pkt               = ks2_eth_free_pkt,
 617         .stop                   = ks2_eth_stop,
 618         .read_rom_hwaddr        = ks2_eth_read_rom_hwaddr,
 619         .write_hwaddr           = ks2_eth_write_hwaddr,
 620 };
 621
 622 static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
 623 {
 624         const void *fdt = gd->fdt_blob;
 625         struct udevice *sl_dev;
 626         int interfaces;
 627         int sec_slave;
 628         int slave;
 629         int ret;
 630         char *slave_name;
 631
 632         interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
 633         fdt_for_each_subnode(slave, fdt, interfaces) {
 634                 int slave_no;
 635
 636                 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
 637                 if (slave_no == -ENOENT)
 638                         continue;
 639
 640                 if (slave_no == 0) {
 641                         /* This is the current eth device */
 642                         *gbe_0 = slave;
 643                 } else {
 644                         /* Slave devices to be registered */
 645                         slave_name = malloc(20);
 646                         snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
 647                         ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
 648                                         slave_name, offset_to_ofnode(slave),
 649                                         &sl_dev);
 650                         if (ret) {
 651                                 pr_err("ks2_net - not able to bind slave interfaces\n");
 652                                 return ret;
 653                         }
 654                 }
 655         }
 656
 657         sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
 658         fdt_for_each_subnode(slave, fdt, sec_slave) {
 659                 int slave_no;
 660
 661                 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
 662                 if (slave_no == -ENOENT)
 663                         continue;
 664
 665                 /* Slave devices to be registered */
 666                 slave_name = malloc(20);
 667                 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
 668                 ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
 669                                         offset_to_ofnode(slave), &sl_dev);
 670                 if (ret) {
 671                         pr_err("ks2_net - not able to bind slave interfaces\n");
 672                         return ret;
 673                 }
 674         }
 675
 676         return 0;
 677 }
 678
 679 static int ks2_eth_parse_slave_interface(int netcp, int slave,
 680                                          struct ks2_eth_priv *priv,
 681                                          struct eth_pdata *pdata)
 682 {
 683         const void *fdt = gd->fdt_blob;
 684         int mdio;
 685         int phy;
 686         int dma_count;
 687         u32 dma_channel[8];
 688         const char *phy_mode;
 689
 690         priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
 691         priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
 692
 693         /* U-Boot slave port number starts with 1 instead of 0 */
 694         priv->slave_port += 1;
 695
 696         dma_count = fdtdec_get_int_array_count(fdt, netcp,
 697                                                "ti,navigator-dmas",
 698                                                dma_channel, 8);
 699
 700         if (dma_count > (2 * priv->slave_port)) {
 701                 int dma_idx;
 702
 703                 dma_idx = priv->slave_port * 2 - 1;
 704                 priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
 705         }
 706
 707         priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
 708
 709         phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
 710
 711         if (phy >= 0) {
 712                 priv->phy_of_handle = phy;
 713                 priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
 714
 715                 mdio = fdt_parent_offset(fdt, phy);
 716                 if (mdio < 0) {
 717                         pr_err("mdio dt not found\n");
 718                         return -ENODEV;
 719                 }
 720                 priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
 721         }
 722
 723         if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
 724                 priv->phy_if = PHY_INTERFACE_MODE_SGMII;
 725                 pdata->phy_interface = priv->phy_if;
 726                 priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
 727                 priv->has_mdio = true;
 728         } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
 729                 phy_mode = fdt_getprop(fdt, slave, "phy-mode", NULL);
 730                 if (phy_mode) {
 731                         priv->phy_if = phy_get_interface_by_name(phy_mode);
 732                         if (priv->phy_if != PHY_INTERFACE_MODE_RGMII &&
 733                             priv->phy_if != PHY_INTERFACE_MODE_RGMII_ID &&
 734                             priv->phy_if != PHY_INTERFACE_MODE_RGMII_RXID &&
 735                             priv->phy_if != PHY_INTERFACE_MODE_RGMII_TXID) {
 736                                 pr_err("invalid phy-mode\n");
 737                                 return -EINVAL;
 738                         }
 739                 } else {
 740                         priv->phy_if = PHY_INTERFACE_MODE_RGMII;
 741                 }
 742                 pdata->phy_interface = priv->phy_if;
 743                 priv->has_mdio = true;
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
 750 {
 751         struct ks2_eth_priv *priv = dev_get_priv(dev);
 752         struct eth_pdata *pdata = dev_get_platdata(dev);
 753         const void *fdt = gd->fdt_blob;
 754         int slave = dev_of_offset(dev);
 755         int interfaces;
 756         int gbe;
 757         int netcp_devices;
 758         int netcp;
 759
 760         interfaces = fdt_parent_offset(fdt, slave);
 761         gbe = fdt_parent_offset(fdt, interfaces);
 762         netcp_devices = fdt_parent_offset(fdt, gbe);
 763         netcp = fdt_parent_offset(fdt, netcp_devices);
 764
 765         ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
 766
 767         pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
 768
 769         return 0;
 770 }
 771
 772 static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
 773 {
 774         struct ks2_eth_priv *priv = dev_get_priv(dev);
 775         struct eth_pdata *pdata = dev_get_platdata(dev);
 776         const void *fdt = gd->fdt_blob;
 777         int gbe_0 = -ENODEV;
 778         int netcp_devices;
 779         int gbe;
 780
 781         netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
 782                                            "netcp-devices");
 783         gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
 784
 785         ks2_eth_bind_slaves(dev, gbe, &gbe_0);
 786
 787         ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
 788
 789         pdata->iobase = devfdt_get_addr(dev);
 790
 791         return 0;
 792 }
 793
 794 static const struct udevice_id ks2_eth_ids[] = {
 795         { .compatible = "ti,netcp-1.0" },
 796         { }
 797 };
 798
 799 U_BOOT_DRIVER(eth_ks2_slave) = {
 800         .name   = "eth_ks2_sl",
 801         .id     = UCLASS_ETH,
 802         .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
 803         .probe  = ks2_eth_probe,
 804         .remove = ks2_eth_remove,
 805         .ops    = &ks2_eth_ops,
 806         .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
 807         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 808         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 809 };
 810
 811 U_BOOT_DRIVER(eth_ks2) = {
 812         .name   = "eth_ks2",
 813         .id     = UCLASS_ETH,
 814         .of_match = ks2_eth_ids,
 815         .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
 816         .probe  = ks2_eth_probe,
 817         .remove = ks2_eth_remove,
 818         .ops    = &ks2_eth_ops,
 819         .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
 820         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 821         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 822 };