drivers/net/ti/davinci_emac.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
   4  *
   5  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   6  *
   7  * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
   8  * follows:
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * dm644x_emac.c
  13  *
  14  * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
  15  *
  16  * Copyright (C) 2005 Texas Instruments.
  17  *
  18  * ----------------------------------------------------------------------------
  19  *
  20  * Modifications:
  21  * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
  22  * ver  1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
  23  */
  24 #include <common.h>
  25 #include <command.h>
  26 #include <cpu_func.h>
  27 #include <log.h>
  28 #include <net.h>
  29 #include <miiphy.h>
  30 #include <malloc.h>
  31 #include <asm/cache.h>
  32 #include <linux/compiler.h>
  33 #include <asm/arch/emac_defs.h>
  34 #include <asm/io.h>
  35 #include "davinci_emac.h"
  36
  37 unsigned int    emac_dbg = 0;
  38 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
  39
  40 #ifdef EMAC_HW_RAM_ADDR
  41 static inline unsigned long BD_TO_HW(unsigned long x)
  42 {
  43         if (x == 0)
  44                 return 0;
  45
  46         return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
  47 }
  48
  49 static inline unsigned long HW_TO_BD(unsigned long x)
  50 {
  51         if (x == 0)
  52                 return 0;
  53
  54         return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
  55 }
  56 #else
  57 #define BD_TO_HW(x)     (x)
  58 #define HW_TO_BD(x)     (x)
  59 #endif
  60
  61 #ifdef DAVINCI_EMAC_GIG_ENABLE
  62 #define emac_gigabit_enable(phy_addr)   davinci_eth_gigabit_enable(phy_addr)
  63 #else
  64 #define emac_gigabit_enable(phy_addr)   /* no gigabit to enable */
  65 #endif
  66
  67 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
  68 #define CONFIG_SYS_EMAC_TI_CLKDIV       ((EMAC_MDIO_BUS_FREQ / \
  69                 EMAC_MDIO_CLOCK_FREQ) - 1)
  70 #endif
  71
  72 static void davinci_eth_mdio_enable(void);
  73
  74 static int gen_init_phy(int phy_addr);
  75 static int gen_is_phy_connected(int phy_addr);
  76 static int gen_get_link_speed(int phy_addr);
  77 static int gen_auto_negotiate(int phy_addr);
  78
  79 void eth_mdio_enable(void)
  80 {
  81         davinci_eth_mdio_enable();
  82 }
  83
  84 /* EMAC Addresses */
  85 static volatile emac_regs       *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
  86 static volatile ewrap_regs      *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
  87 static volatile mdio_regs       *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
  88
  89 /* EMAC descriptors */
  90 static volatile emac_desc       *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
  91 static volatile emac_desc       *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
  92 static volatile emac_desc       *emac_rx_active_head = 0;
  93 static volatile emac_desc       *emac_rx_active_tail = 0;
  94 static int                      emac_rx_queue_active = 0;
  95
  96 /* Receive packet buffers */
  97 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
  98                                 __aligned(ARCH_DMA_MINALIGN);
  99
 100 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
 101 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT       3
 102 #endif
 103
 104 /* PHY address for a discovered PHY (0xff - not found) */
 105 static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
 106
 107 /* number of PHY found active */
 108 static u_int8_t num_phy;
 109
 110 phy_t                           phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
 111
 112 static int davinci_emac_write_hwaddr(struct udevice *dev)
 113 {
 114         struct eth_pdata *pdata = dev_get_platdata(dev);
 115         unsigned long           mac_hi;
 116         unsigned long           mac_lo;
 117
 118         /*
 119          * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
 120          * receive)
 121          *  Using channel 0 only - other channels are disabled
 122          *  */
 123         writel(0, &adap_emac->MACINDEX);
 124         mac_hi = (pdata->enetaddr[3] << 24) |
 125                  (pdata->enetaddr[2] << 16) |
 126                  (pdata->enetaddr[1] << 8)  |
 127                  (pdata->enetaddr[0]);
 128         mac_lo = (pdata->enetaddr[5] << 8) |
 129                  (pdata->enetaddr[4]);
 130
 131         writel(mac_hi, &adap_emac->MACADDRHI);
 132 #if defined(DAVINCI_EMAC_VERSION2)
 133         writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
 134                &adap_emac->MACADDRLO);
 135 #else
 136         writel(mac_lo, &adap_emac->MACADDRLO);
 137 #endif
 138
 139         writel(0, &adap_emac->MACHASH1);
 140         writel(0, &adap_emac->MACHASH2);
 141
 142         /* Set source MAC address - REQUIRED */
 143         writel(mac_hi, &adap_emac->MACSRCADDRHI);
 144         writel(mac_lo, &adap_emac->MACSRCADDRLO);
 145
 146
 147         return 0;
 148 }
 149
 150 static void davinci_eth_mdio_enable(void)
 151 {
 152         u_int32_t       clkdiv;
 153
 154         clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 155
 156         writel((clkdiv & 0xff) |
 157                MDIO_CONTROL_ENABLE |
 158                MDIO_CONTROL_FAULT |
 159                MDIO_CONTROL_FAULT_ENABLE,
 160                &adap_mdio->CONTROL);
 161
 162         while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
 163                 ;
 164 }
 165
 166 /*
 167  * Tries to find an active connected PHY. Returns 1 if address if found.
 168  * If no active PHY (or more than one PHY) found returns 0.
 169  * Sets active_phy_addr variable.
 170  */
 171 static int davinci_eth_phy_detect(void)
 172 {
 173         u_int32_t       phy_act_state;
 174         int             i;
 175         int             j;
 176         unsigned int    count = 0;
 177
 178         for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
 179                 active_phy_addr[i] = 0xff;
 180
 181         udelay(1000);
 182         phy_act_state = readl(&adap_mdio->ALIVE);
 183
 184         if (phy_act_state == 0)
 185                 return 0;               /* No active PHYs */
 186
 187         debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
 188
 189         for (i = 0, j = 0; i < 32; i++)
 190                 if (phy_act_state & (1 << i)) {
 191                         count++;
 192                         if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
 193                                 active_phy_addr[j++] = i;
 194                         } else {
 195                                 printf("%s: to many PHYs detected.\n",
 196                                         __func__);
 197                                 count = 0;
 198                                 break;
 199                         }
 200                 }
 201
 202         num_phy = count;
 203
 204         return count;
 205 }
 206
 207
 208 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
 209 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
 210 {
 211         int     tmp;
 212
 213         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 214                 ;
 215
 216         writel(MDIO_USERACCESS0_GO |
 217                MDIO_USERACCESS0_WRITE_READ |
 218                ((reg_num & 0x1f) << 21) |
 219                ((phy_addr & 0x1f) << 16),
 220                &adap_mdio->USERACCESS0);
 221
 222         /* Wait for command to complete */
 223         while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
 224                 ;
 225
 226         if (tmp & MDIO_USERACCESS0_ACK) {
 227                 *data = tmp & 0xffff;
 228                 return 1;
 229         }
 230
 231         return 0;
 232 }
 233
 234 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
 235 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
 236 {
 237
 238         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 239                 ;
 240
 241         writel(MDIO_USERACCESS0_GO |
 242                MDIO_USERACCESS0_WRITE_WRITE |
 243                ((reg_num & 0x1f) << 21) |
 244                ((phy_addr & 0x1f) << 16) |
 245                (data & 0xffff),
 246                &adap_mdio->USERACCESS0);
 247
 248         /* Wait for command to complete */
 249         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 250                 ;
 251
 252         return 1;
 253 }
 254
 255 /* PHY functions for a generic PHY */
 256 static int gen_init_phy(int phy_addr)
 257 {
 258         int     ret = 1;
 259
 260         if (gen_get_link_speed(phy_addr)) {
 261                 /* Try another time */
 262                 ret = gen_get_link_speed(phy_addr);
 263         }
 264
 265         return(ret);
 266 }
 267
 268 static int gen_is_phy_connected(int phy_addr)
 269 {
 270         u_int16_t       dummy;
 271
 272         return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
 273 }
 274
 275 static int get_active_phy(void)
 276 {
 277         int i;
 278
 279         for (i = 0; i < num_phy; i++)
 280                 if (phy[i].get_link_speed(active_phy_addr[i]))
 281                         return i;
 282
 283         return -1;      /* Return error if no link */
 284 }
 285
 286 static int gen_get_link_speed(int phy_addr)
 287 {
 288         u_int16_t       tmp;
 289
 290         if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
 291                         (tmp & 0x04)) {
 292 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 293                 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 294                 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
 295
 296                 /* Speed doesn't matter, there is no setting for it in EMAC. */
 297                 if (tmp & (LPA_100FULL | LPA_10FULL)) {
 298                         /* set EMAC for Full Duplex  */
 299                         writel(EMAC_MACCONTROL_MIIEN_ENABLE |
 300                                         EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
 301                                         &adap_emac->MACCONTROL);
 302                 } else {
 303                         /*set EMAC for Half Duplex  */
 304                         writel(EMAC_MACCONTROL_MIIEN_ENABLE,
 305                                         &adap_emac->MACCONTROL);
 306                 }
 307
 308                 if (tmp & (LPA_100FULL | LPA_100HALF))
 309                         writel(readl(&adap_emac->MACCONTROL) |
 310                                         EMAC_MACCONTROL_RMIISPEED_100,
 311                                          &adap_emac->MACCONTROL);
 312                 else
 313                         writel(readl(&adap_emac->MACCONTROL) &
 314                                         ~EMAC_MACCONTROL_RMIISPEED_100,
 315                                          &adap_emac->MACCONTROL);
 316 #endif
 317                 return(1);
 318         }
 319
 320         return(0);
 321 }
 322
 323 static int gen_auto_negotiate(int phy_addr)
 324 {
 325         u_int16_t       tmp;
 326         u_int16_t       val;
 327         unsigned long   cntr = 0;
 328
 329         if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
 330                 return 0;
 331
 332         val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
 333                                                 BMCR_SPEED100;
 334         davinci_eth_phy_write(phy_addr, MII_BMCR, val);
 335
 336         if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
 337                 return 0;
 338
 339         val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
 340                                                         ADVERTISE_10HALF);
 341         davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
 342
 343         if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
 344                 return(0);
 345
 346 #ifdef DAVINCI_EMAC_GIG_ENABLE
 347         davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
 348         val |= PHY_1000BTCR_1000FD;
 349         val &= ~PHY_1000BTCR_1000HD;
 350         davinci_eth_phy_write(phy_addr, MII_CTRL1000, val);
 351         davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
 352 #endif
 353
 354         /* Restart Auto_negotiation  */
 355         tmp |= BMCR_ANRESTART;
 356         davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
 357
 358         /*check AutoNegotiate complete */
 359         do {
 360                 udelay(40000);
 361                 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
 362                         return 0;
 363
 364                 if (tmp & BMSR_ANEGCOMPLETE)
 365                         break;
 366
 367                 cntr++;
 368         } while (cntr < 200);
 369
 370         if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
 371                 return(0);
 372
 373         if (!(tmp & BMSR_ANEGCOMPLETE))
 374                 return(0);
 375
 376         return(gen_get_link_speed(phy_addr));
 377 }
 378 /* End of generic PHY functions */
 379
 380
 381 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 382 static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
 383                                 int reg)
 384 {
 385         unsigned short value = 0;
 386         int retval = davinci_eth_phy_read(addr, reg, &value);
 387
 388         return retval ? value : -EIO;
 389 }
 390
 391 static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad,
 392                                  int reg, u16 value)
 393 {
 394         return davinci_eth_phy_write(addr, reg, value) ? 0 : 1;
 395 }
 396 #endif
 397
 398 static void  __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
 399 {
 400         u_int16_t data;
 401
 402         if (davinci_eth_phy_read(phy_addr, 0, &data)) {
 403                 if (data & (1 << 6)) { /* speed selection MSB */
 404                         /*
 405                          * Check if link detected is giga-bit
 406                          * If Gigabit mode detected, enable gigbit in MAC
 407                          */
 408                         writel(readl(&adap_emac->MACCONTROL) |
 409                                 EMAC_MACCONTROL_GIGFORCE |
 410                                 EMAC_MACCONTROL_GIGABIT_ENABLE,
 411                                 &adap_emac->MACCONTROL);
 412                 }
 413         }
 414 }
 415
 416 /* Eth device open */
 417 static int davinci_emac_start(struct udevice *dev)
 418 {
 419         dv_reg_p                addr;
 420         u_int32_t               clkdiv, cnt, mac_control;
 421         uint16_t                __maybe_unused lpa_val;
 422         volatile emac_desc      *rx_desc;
 423         int                     index;
 424
 425         debug_emac("+ emac_open\n");
 426
 427         /* Reset EMAC module and disable interrupts in wrapper */
 428         writel(1, &adap_emac->SOFTRESET);
 429         while (readl(&adap_emac->SOFTRESET) != 0)
 430                 ;
 431 #if defined(DAVINCI_EMAC_VERSION2)
 432         writel(1, &adap_ewrap->softrst);
 433         while (readl(&adap_ewrap->softrst) != 0)
 434                 ;
 435 #else
 436         writel(0, &adap_ewrap->EWCTL);
 437         for (cnt = 0; cnt < 5; cnt++) {
 438                 clkdiv = readl(&adap_ewrap->EWCTL);
 439         }
 440 #endif
 441
 442 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 443         defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 444         adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
 445         adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
 446         adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
 447 #endif
 448         rx_desc = emac_rx_desc;
 449
 450         writel(1, &adap_emac->TXCONTROL);
 451         writel(1, &adap_emac->RXCONTROL);
 452
 453         davinci_emac_write_hwaddr(dev);
 454
 455         /* Set DMA 8 TX / 8 RX Head pointers to 0 */
 456         addr = &adap_emac->TX0HDP;
 457         for (cnt = 0; cnt < 8; cnt++)
 458                 writel(0, addr++);
 459
 460         addr = &adap_emac->RX0HDP;
 461         for (cnt = 0; cnt < 8; cnt++)
 462                 writel(0, addr++);
 463
 464         /* Clear Statistics (do this before setting MacControl register) */
 465         addr = &adap_emac->RXGOODFRAMES;
 466         for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
 467                 writel(0, addr++);
 468
 469         /* No multicast addressing */
 470         writel(0, &adap_emac->MACHASH1);
 471         writel(0, &adap_emac->MACHASH2);
 472
 473         /* Create RX queue and set receive process in place */
 474         emac_rx_active_head = emac_rx_desc;
 475         for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
 476                 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
 477                 rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
 478                 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
 479                 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
 480                 rx_desc++;
 481         }
 482
 483         /* Finalize the rx desc list */
 484         rx_desc--;
 485         rx_desc->next = 0;
 486         emac_rx_active_tail = rx_desc;
 487         emac_rx_queue_active = 1;
 488
 489         /* Enable TX/RX */
 490         writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
 491         writel(0, &adap_emac->RXBUFFEROFFSET);
 492
 493         /*
 494          * No fancy configs - Use this for promiscous debug
 495          *   - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
 496          */
 497         writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
 498
 499         /* Enable ch 0 only */
 500         writel(1, &adap_emac->RXUNICASTSET);
 501
 502         /* Init MDIO & get link state */
 503         clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 504         writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
 505                &adap_mdio->CONTROL);
 506
 507         /* We need to wait for MDIO to start */
 508         udelay(1000);
 509
 510         index = get_active_phy();
 511         if (index == -1)
 512                 return(0);
 513
 514         /* Enable MII interface */
 515         mac_control = EMAC_MACCONTROL_MIIEN_ENABLE;
 516 #ifdef DAVINCI_EMAC_GIG_ENABLE
 517         davinci_eth_phy_read(active_phy_addr[index], MII_STAT1000, &lpa_val);
 518         if (lpa_val & PHY_1000BTSR_1000FD) {
 519                 debug_emac("eth_open : gigabit negotiated\n");
 520                 mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
 521                 mac_control |= EMAC_MACCONTROL_GIGABIT_ENABLE;
 522         }
 523 #endif
 524
 525         davinci_eth_phy_read(active_phy_addr[index], MII_LPA, &lpa_val);
 526         if (lpa_val & (LPA_100FULL | LPA_10FULL))
 527                 /* set EMAC for Full Duplex  */
 528                 mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
 529 #if defined(CONFIG_SOC_DA8XX) || \
 530         (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
 531         mac_control |= EMAC_MACCONTROL_RMIISPEED_100;
 532 #endif
 533         writel(mac_control, &adap_emac->MACCONTROL);
 534         /* Start receive process */
 535         writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
 536
 537         debug_emac("- emac_open\n");
 538
 539         return(1);
 540 }
 541
 542 /* EMAC Channel Teardown */
 543 static void davinci_eth_ch_teardown(int ch)
 544 {
 545         dv_reg          dly = 0xff;
 546         dv_reg          cnt;
 547
 548         debug_emac("+ emac_ch_teardown\n");
 549
 550         if (ch == EMAC_CH_TX) {
 551                 /* Init TX channel teardown */
 552                 writel(0, &adap_emac->TXTEARDOWN);
 553                 do {
 554                         /*
 555                          * Wait here for Tx teardown completion interrupt to
 556                          * occur. Note: A task delay can be called here to pend
 557                          * rather than occupying CPU cycles - anyway it has
 558                          * been found that teardown takes very few cpu cycles
 559                          * and does not affect functionality
 560                          */
 561                         dly--;
 562                         udelay(1);
 563                         if (dly == 0)
 564                                 break;
 565                         cnt = readl(&adap_emac->TX0CP);
 566                 } while (cnt != 0xfffffffc);
 567                 writel(cnt, &adap_emac->TX0CP);
 568                 writel(0, &adap_emac->TX0HDP);
 569         } else {
 570                 /* Init RX channel teardown */
 571                 writel(0, &adap_emac->RXTEARDOWN);
 572                 do {
 573                         /*
 574                          * Wait here for Rx teardown completion interrupt to
 575                          * occur. Note: A task delay can be called here to pend
 576                          * rather than occupying CPU cycles - anyway it has
 577                          * been found that teardown takes very few cpu cycles
 578                          * and does not affect functionality
 579                          */
 580                         dly--;
 581                         udelay(1);
 582                         if (dly == 0)
 583                                 break;
 584                         cnt = readl(&adap_emac->RX0CP);
 585                 } while (cnt != 0xfffffffc);
 586                 writel(cnt, &adap_emac->RX0CP);
 587                 writel(0, &adap_emac->RX0HDP);
 588         }
 589
 590         debug_emac("- emac_ch_teardown\n");
 591 }
 592
 593 /* Eth device close */
 594 static void davinci_emac_stop(struct udevice *dev)
 595 {
 596         debug_emac("+ emac_close\n");
 597
 598         davinci_eth_ch_teardown(EMAC_CH_TX);    /* TX Channel teardown */
 599         if (readl(&adap_emac->RXCONTROL) & 1)
 600                 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
 601
 602         /* Reset EMAC module and disable interrupts in wrapper */
 603         writel(1, &adap_emac->SOFTRESET);
 604 #if defined(DAVINCI_EMAC_VERSION2)
 605         writel(1, &adap_ewrap->softrst);
 606 #else
 607         writel(0, &adap_ewrap->EWCTL);
 608 #endif
 609
 610 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 611         defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 612         adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
 613         adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
 614         adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
 615 #endif
 616         debug_emac("- emac_close\n");
 617 }
 618
 619 static int tx_send_loop = 0;
 620
 621 /*
 622  * This function sends a single packet on the network and returns
 623  * positive number (number of bytes transmitted) or negative for error
 624  */
 625 static int davinci_emac_send(struct udevice *dev,
 626                              void *packet, int length)
 627 {
 628         int ret_status = -1;
 629         int index;
 630         tx_send_loop = 0;
 631
 632         index = get_active_phy();
 633         if (index == -1) {
 634                 printf(" WARN: emac_send_packet: No link\n");
 635                 return (ret_status);
 636         }
 637
 638         /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
 639         if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
 640                 length = EMAC_MIN_ETHERNET_PKT_SIZE;
 641         }
 642
 643         /* Populate the TX descriptor */
 644         emac_tx_desc->next = 0;
 645         emac_tx_desc->buffer = (u_int8_t *) packet;
 646         emac_tx_desc->buff_off_len = (length & 0xffff);
 647         emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
 648                                       EMAC_CPPI_SOP_BIT |
 649                                       EMAC_CPPI_OWNERSHIP_BIT |
 650                                       EMAC_CPPI_EOP_BIT);
 651
 652         flush_dcache_range((unsigned long)packet,
 653                            (unsigned long)packet + ALIGN(length, PKTALIGN));
 654
 655         /* Send the packet */
 656         writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
 657
 658         /* Wait for packet to complete or link down */
 659         while (1) {
 660                 if (!phy[index].get_link_speed(active_phy_addr[index])) {
 661                         davinci_eth_ch_teardown (EMAC_CH_TX);
 662                         return (ret_status);
 663                 }
 664
 665                 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
 666                         ret_status = length;
 667                         break;
 668                 }
 669                 tx_send_loop++;
 670         }
 671
 672         return (ret_status);
 673 }
 674
 675 /*
 676  * This function handles receipt of a packet from the network
 677  */
 678 static int davinci_emac_recv(struct udevice *dev, int flags, uchar **packetp)
 679 {
 680         volatile emac_desc *rx_curr_desc;
 681         volatile emac_desc *curr_desc;
 682         volatile emac_desc *tail_desc;
 683         int status, ret = -1;
 684
 685         rx_curr_desc = emac_rx_active_head;
 686         if (!rx_curr_desc)
 687                 return 0;
 688         *packetp = rx_curr_desc->buffer;
 689         status = rx_curr_desc->pkt_flag_len;
 690         if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) {
 691                 if (status & EMAC_CPPI_RX_ERROR_FRAME) {
 692                         /* Error in packet - discard it and requeue desc */
 693                         printf ("WARN: emac_rcv_pkt: Error in packet\n");
 694                 } else {
 695                         unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
 696                         unsigned short len =
 697                                 rx_curr_desc->buff_off_len & 0xffff;
 698
 699                         invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN));
 700                         ret = len;
 701                 }
 702
 703                 /* Ack received packet descriptor */
 704                 writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
 705                 curr_desc = rx_curr_desc;
 706                 emac_rx_active_head =
 707                         (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
 708
 709                 if (status & EMAC_CPPI_EOQ_BIT) {
 710                         if (emac_rx_active_head) {
 711                                 writel(BD_TO_HW((ulong)emac_rx_active_head),
 712                                        &adap_emac->RX0HDP);
 713                         } else {
 714                                 emac_rx_queue_active = 0;
 715                                 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
 716                         }
 717                 }
 718
 719                 /* Recycle RX descriptor */
 720                 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
 721                 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
 722                 rx_curr_desc->next = 0;
 723
 724                 if (emac_rx_active_head == 0) {
 725                         printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
 726                         emac_rx_active_head = curr_desc;
 727                         emac_rx_active_tail = curr_desc;
 728                         if (emac_rx_queue_active != 0) {
 729                                 writel(BD_TO_HW((ulong)emac_rx_active_head),
 730                                        &adap_emac->RX0HDP);
 731                                 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
 732                                 emac_rx_queue_active = 1;
 733                         }
 734                 } else {
 735                         tail_desc = emac_rx_active_tail;
 736                         emac_rx_active_tail = curr_desc;
 737                         tail_desc->next = BD_TO_HW((ulong) curr_desc);
 738                         status = tail_desc->pkt_flag_len;
 739                         if (status & EMAC_CPPI_EOQ_BIT) {
 740                                 writel(BD_TO_HW((ulong)curr_desc),
 741                                        &adap_emac->RX0HDP);
 742                                 status &= ~EMAC_CPPI_EOQ_BIT;
 743                                 tail_desc->pkt_flag_len = status;
 744                         }
 745                 }
 746                 return (ret);
 747         }
 748
 749         return (0);
 750 }
 751
 752 /*
 753  * This function initializes the emac hardware. It does NOT initialize
 754  * EMAC modules power or pin multiplexors, that is done by board_init()
 755  * much earlier in bootup process. Returns 1 on success, 0 otherwise.
 756  */
 757 static int davinci_emac_probe(struct udevice *dev)
 758 {
 759         u_int32_t       phy_id;
 760         u_int16_t       tmp;
 761         int             i;
 762         int             ret;
 763
 764         davinci_eth_mdio_enable();
 765
 766         /* let the EMAC detect the PHYs */
 767         udelay(5000);
 768
 769         for (i = 0; i < 256; i++) {
 770                 if (readl(&adap_mdio->ALIVE))
 771                         break;
 772                 udelay(1000);
 773         }
 774
 775         if (i >= 256) {
 776                 printf("No ETH PHY detected!!!\n");
 777                 return(0);
 778         }
 779
 780         /* Find if PHY(s) is/are connected */
 781         ret = davinci_eth_phy_detect();
 782         if (!ret)
 783                 return(0);
 784         else
 785                 debug_emac(" %d ETH PHY detected\n", ret);
 786
 787         /* Get PHY ID and initialize phy_ops for a detected PHY */
 788         for (i = 0; i < num_phy; i++) {
 789                 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
 790                                                         &tmp)) {
 791                         active_phy_addr[i] = 0xff;
 792                         continue;
 793                 }
 794
 795                 phy_id = (tmp << 16) & 0xffff0000;
 796
 797                 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
 798                                                         &tmp)) {
 799                         active_phy_addr[i] = 0xff;
 800                         continue;
 801                 }
 802
 803                 phy_id |= tmp & 0x0000ffff;
 804
 805                 sprintf(phy[i].name, "GENERIC @ 0x%02x",
 806                         active_phy_addr[i]);
 807                 phy[i].init = gen_init_phy;
 808                 phy[i].is_phy_connected = gen_is_phy_connected;
 809                 phy[i].get_link_speed = gen_get_link_speed;
 810                 phy[i].auto_negotiate = gen_auto_negotiate;
 811
 812                 debug("Ethernet PHY: %s\n", phy[i].name);
 813
 814                 int retval;
 815                 struct mii_dev *mdiodev = mdio_alloc();
 816                 if (!mdiodev)
 817                         return -ENOMEM;
 818                 strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
 819                 mdiodev->read = davinci_mii_phy_read;
 820                 mdiodev->write = davinci_mii_phy_write;
 821
 822                 retval = mdio_register(mdiodev);
 823                 if (retval < 0)
 824                         return retval;
 825 #ifdef DAVINCI_EMAC_GIG_ENABLE
 826 #define PHY_CONF_REG    22
 827                 /* Enable PHY to clock out TX_CLK */
 828                 davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
 829                 tmp |= PHY_CONF_TXCLKEN;
 830                 davinci_eth_phy_write(active_phy_addr[i], PHY_CONF_REG, tmp);
 831                 davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
 832 #endif
 833         }
 834
 835 #if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 836                 defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
 837                         !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE))
 838         for (i = 0; i < num_phy; i++) {
 839                 if (phy[i].is_phy_connected(i))
 840                         phy[i].auto_negotiate(i);
 841         }
 842 #endif
 843         return 0;
 844 }
 845
 846 static const struct eth_ops davinci_emac_ops = {
 847         .start          = davinci_emac_start,
 848         .send           = davinci_emac_send,
 849         .recv           = davinci_emac_recv,
 850         .stop           = davinci_emac_stop,
 851         .write_hwaddr   = davinci_emac_write_hwaddr,
 852 };
 853
 854 static const struct udevice_id davinci_emac_ids[] = {
 855         { .compatible = "ti,davinci-dm6467-emac" },
 856         { .compatible = "ti,am3517-emac", },
 857         { .compatible = "ti,dm816-emac", },
 858         { }
 859 };
 860
 861 U_BOOT_DRIVER(davinci_emac) = {
 862         .name           = "davinci_emac",
 863         .id             = UCLASS_ETH,
 864         .of_match       = davinci_emac_ids,
 865         .probe          = davinci_emac_probe,
 866         .ops            = &davinci_emac_ops,
 867         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 868 };