drivers/net/ti/cpsw.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * CPSW Ethernet Switch Driver
   4  *
   5  * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <cpu_func.h>
  11 #include <net.h>
  12 #include <miiphy.h>
  13 #include <malloc.h>
  14 #include <net.h>
  15 #include <netdev.h>
  16 #include <cpsw.h>
  17 #include <linux/errno.h>
  18 #include <asm/gpio.h>
  19 #include <asm/io.h>
  20 #include <phy.h>
  21 #include <asm/arch/cpu.h>
  22 #include <dm.h>
  23
  24 #include "cpsw_mdio.h"
  25
  26 #define BITMASK(bits)           (BIT(bits) - 1)
  27 #define NUM_DESCS               (PKTBUFSRX * 2)
  28 #define PKT_MIN                 60
  29 #define PKT_MAX                 (1500 + 14 + 4 + 4)
  30 #define CLEAR_BIT               1
  31 #define GIGABITEN               BIT(7)
  32 #define FULLDUPLEXEN            BIT(0)
  33 #define MIIEN                   BIT(15)
  34 #define CTL_EXT_EN              BIT(18)
  35 /* DMA Registers */
  36 #define CPDMA_TXCONTROL         0x004
  37 #define CPDMA_RXCONTROL         0x014
  38 #define CPDMA_SOFTRESET         0x01c
  39 #define CPDMA_RXFREE            0x0e0
  40 #define CPDMA_TXHDP_VER1        0x100
  41 #define CPDMA_TXHDP_VER2        0x200
  42 #define CPDMA_RXHDP_VER1        0x120
  43 #define CPDMA_RXHDP_VER2        0x220
  44 #define CPDMA_TXCP_VER1         0x140
  45 #define CPDMA_TXCP_VER2         0x240
  46 #define CPDMA_RXCP_VER1         0x160
  47 #define CPDMA_RXCP_VER2         0x260
  48
  49 /* Descriptor mode bits */
  50 #define CPDMA_DESC_SOP          BIT(31)
  51 #define CPDMA_DESC_EOP          BIT(30)
  52 #define CPDMA_DESC_OWNER        BIT(29)
  53 #define CPDMA_DESC_EOQ          BIT(28)
  54
  55 /*
  56  * This timeout definition is a worst-case ultra defensive measure against
  57  * unexpected controller lock ups.  Ideally, we should never ever hit this
  58  * scenario in practice.
  59  */
  60 #define CPDMA_TIMEOUT           100 /* msecs */
  61
  62 struct cpsw_regs {
  63         u32     id_ver;
  64         u32     control;
  65         u32     soft_reset;
  66         u32     stat_port_en;
  67         u32     ptype;
  68 };
  69
  70 struct cpsw_slave_regs {
  71         u32     max_blks;
  72         u32     blk_cnt;
  73         u32     flow_thresh;
  74         u32     port_vlan;
  75         u32     tx_pri_map;
  76 #ifdef CONFIG_AM33XX
  77         u32     gap_thresh;
  78 #elif defined(CONFIG_TI814X)
  79         u32     ts_ctl;
  80         u32     ts_seq_ltype;
  81         u32     ts_vlan;
  82 #endif
  83         u32     sa_lo;
  84         u32     sa_hi;
  85 };
  86
  87 struct cpsw_host_regs {
  88         u32     max_blks;
  89         u32     blk_cnt;
  90         u32     flow_thresh;
  91         u32     port_vlan;
  92         u32     tx_pri_map;
  93         u32     cpdma_tx_pri_map;
  94         u32     cpdma_rx_chan_map;
  95 };
  96
  97 struct cpsw_sliver_regs {
  98         u32     id_ver;
  99         u32     mac_control;
 100         u32     mac_status;
 101         u32     soft_reset;
 102         u32     rx_maxlen;
 103         u32     __reserved_0;
 104         u32     rx_pause;
 105         u32     tx_pause;
 106         u32     __reserved_1;
 107         u32     rx_pri_map;
 108 };
 109
 110 #define ALE_ENTRY_BITS          68
 111 #define ALE_ENTRY_WORDS         DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
 112
 113 /* ALE Registers */
 114 #define ALE_CONTROL             0x08
 115 #define ALE_UNKNOWNVLAN         0x18
 116 #define ALE_TABLE_CONTROL       0x20
 117 #define ALE_TABLE               0x34
 118 #define ALE_PORTCTL             0x40
 119
 120 #define ALE_TABLE_WRITE         BIT(31)
 121
 122 #define ALE_TYPE_FREE                   0
 123 #define ALE_TYPE_ADDR                   1
 124 #define ALE_TYPE_VLAN                   2
 125 #define ALE_TYPE_VLAN_ADDR              3
 126
 127 #define ALE_UCAST_PERSISTANT            0
 128 #define ALE_UCAST_UNTOUCHED             1
 129 #define ALE_UCAST_OUI                   2
 130 #define ALE_UCAST_TOUCHED               3
 131
 132 #define ALE_MCAST_FWD                   0
 133 #define ALE_MCAST_BLOCK_LEARN_FWD       1
 134 #define ALE_MCAST_FWD_LEARN             2
 135 #define ALE_MCAST_FWD_2                 3
 136
 137 enum cpsw_ale_port_state {
 138         ALE_PORT_STATE_DISABLE  = 0x00,
 139         ALE_PORT_STATE_BLOCK    = 0x01,
 140         ALE_PORT_STATE_LEARN    = 0x02,
 141         ALE_PORT_STATE_FORWARD  = 0x03,
 142 };
 143
 144 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
 145 #define ALE_SECURE      1
 146 #define ALE_BLOCKED     2
 147
 148 struct cpsw_slave {
 149         struct cpsw_slave_regs          *regs;
 150         struct cpsw_sliver_regs         *sliver;
 151         int                             slave_num;
 152         u32                             mac_control;
 153         struct cpsw_slave_data          *data;
 154 };
 155
 156 struct cpdma_desc {
 157         /* hardware fields */
 158         u32                     hw_next;
 159         u32                     hw_buffer;
 160         u32                     hw_len;
 161         u32                     hw_mode;
 162         /* software fields */
 163         u32                     sw_buffer;
 164         u32                     sw_len;
 165 };
 166
 167 struct cpdma_chan {
 168         struct cpdma_desc       *head, *tail;
 169         void                    *hdp, *cp, *rxfree;
 170 };
 171
 172 /* AM33xx SoC specific definitions for the CONTROL port */
 173 #define AM33XX_GMII_SEL_MODE_MII        0
 174 #define AM33XX_GMII_SEL_MODE_RMII       1
 175 #define AM33XX_GMII_SEL_MODE_RGMII      2
 176
 177 #define AM33XX_GMII_SEL_RGMII1_IDMODE   BIT(4)
 178 #define AM33XX_GMII_SEL_RGMII2_IDMODE   BIT(5)
 179 #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
 180 #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
 181
 182 #define GMII_SEL_MODE_MASK              0x3
 183
 184 #define desc_write(desc, fld, val)      __raw_writel((u32)(val), &(desc)->fld)
 185 #define desc_read(desc, fld)            __raw_readl(&(desc)->fld)
 186 #define desc_read_ptr(desc, fld)        ((void *)__raw_readl(&(desc)->fld))
 187
 188 #define chan_write(chan, fld, val)      __raw_writel((u32)(val), (chan)->fld)
 189 #define chan_read(chan, fld)            __raw_readl((chan)->fld)
 190 #define chan_read_ptr(chan, fld)        ((void *)__raw_readl((chan)->fld))
 191
 192 #define for_active_slave(slave, priv) \
 193         slave = (priv)->slaves + ((priv)->data)->active_slave; if (slave)
 194 #define for_each_slave(slave, priv) \
 195         for (slave = (priv)->slaves; slave != (priv)->slaves + \
 196                                 ((priv)->data)->slaves; slave++)
 197
 198 struct cpsw_priv {
 199 #ifdef CONFIG_DM_ETH
 200         struct udevice                  *dev;
 201 #else
 202         struct eth_device               *dev;
 203 #endif
 204         struct cpsw_platform_data       *data;
 205         int                             host_port;
 206
 207         struct cpsw_regs                *regs;
 208         void                            *dma_regs;
 209         struct cpsw_host_regs           *host_port_regs;
 210         void                            *ale_regs;
 211
 212         struct cpdma_desc               *descs;
 213         struct cpdma_desc               *desc_free;
 214         struct cpdma_chan               rx_chan, tx_chan;
 215
 216         struct cpsw_slave               *slaves;
 217         struct phy_device               *phydev;
 218         struct mii_dev                  *bus;
 219
 220         u32                             phy_mask;
 221 };
 222
 223 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
 224 {
 225         int idx;
 226
 227         idx    = start / 32;
 228         start -= idx * 32;
 229         idx    = 2 - idx; /* flip */
 230         return (ale_entry[idx] >> start) & BITMASK(bits);
 231 }
 232
 233 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
 234                                       u32 value)
 235 {
 236         int idx;
 237
 238         value &= BITMASK(bits);
 239         idx    = start / 32;
 240         start -= idx * 32;
 241         idx    = 2 - idx; /* flip */
 242         ale_entry[idx] &= ~(BITMASK(bits) << start);
 243         ale_entry[idx] |=  (value << start);
 244 }
 245
 246 #define DEFINE_ALE_FIELD(name, start, bits)                             \
 247 static inline int cpsw_ale_get_##name(u32 *ale_entry)                   \
 248 {                                                                       \
 249         return cpsw_ale_get_field(ale_entry, start, bits);              \
 250 }                                                                       \
 251 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)       \
 252 {                                                                       \
 253         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 254 }
 255
 256 DEFINE_ALE_FIELD(entry_type,            60,     2)
 257 DEFINE_ALE_FIELD(mcast_state,           62,     2)
 258 DEFINE_ALE_FIELD(port_mask,             66,     3)
 259 DEFINE_ALE_FIELD(ucast_type,            62,     2)
 260 DEFINE_ALE_FIELD(port_num,              66,     2)
 261 DEFINE_ALE_FIELD(blocked,               65,     1)
 262 DEFINE_ALE_FIELD(secure,                64,     1)
 263 DEFINE_ALE_FIELD(mcast,                 40,     1)
 264
 265 /* The MAC address field in the ALE entry cannot be macroized as above */
 266 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
 267 {
 268         int i;
 269
 270         for (i = 0; i < 6; i++)
 271                 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
 272 }
 273
 274 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
 275 {
 276         int i;
 277
 278         for (i = 0; i < 6; i++)
 279                 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
 280 }
 281
 282 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 283 {
 284         int i;
 285
 286         __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
 287
 288         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 289                 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
 290
 291         return idx;
 292 }
 293
 294 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 295 {
 296         int i;
 297
 298         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 299                 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
 300
 301         __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
 302
 303         return idx;
 304 }
 305
 306 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
 307 {
 308         u32 ale_entry[ALE_ENTRY_WORDS];
 309         int type, idx;
 310
 311         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 312                 u8 entry_addr[6];
 313
 314                 cpsw_ale_read(priv, idx, ale_entry);
 315                 type = cpsw_ale_get_entry_type(ale_entry);
 316                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 317                         continue;
 318                 cpsw_ale_get_addr(ale_entry, entry_addr);
 319                 if (memcmp(entry_addr, addr, 6) == 0)
 320                         return idx;
 321         }
 322         return -ENOENT;
 323 }
 324
 325 static int cpsw_ale_match_free(struct cpsw_priv *priv)
 326 {
 327         u32 ale_entry[ALE_ENTRY_WORDS];
 328         int type, idx;
 329
 330         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 331                 cpsw_ale_read(priv, idx, ale_entry);
 332                 type = cpsw_ale_get_entry_type(ale_entry);
 333                 if (type == ALE_TYPE_FREE)
 334                         return idx;
 335         }
 336         return -ENOENT;
 337 }
 338
 339 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
 340 {
 341         u32 ale_entry[ALE_ENTRY_WORDS];
 342         int type, idx;
 343
 344         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 345                 cpsw_ale_read(priv, idx, ale_entry);
 346                 type = cpsw_ale_get_entry_type(ale_entry);
 347                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 348                         continue;
 349                 if (cpsw_ale_get_mcast(ale_entry))
 350                         continue;
 351                 type = cpsw_ale_get_ucast_type(ale_entry);
 352                 if (type != ALE_UCAST_PERSISTANT &&
 353                     type != ALE_UCAST_OUI)
 354                         return idx;
 355         }
 356         return -ENOENT;
 357 }
 358
 359 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
 360                               int port, int flags)
 361 {
 362         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 363         int idx;
 364
 365         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 366         cpsw_ale_set_addr(ale_entry, addr);
 367         cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
 368         cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
 369         cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
 370         cpsw_ale_set_port_num(ale_entry, port);
 371
 372         idx = cpsw_ale_match_addr(priv, addr);
 373         if (idx < 0)
 374                 idx = cpsw_ale_match_free(priv);
 375         if (idx < 0)
 376                 idx = cpsw_ale_find_ageable(priv);
 377         if (idx < 0)
 378                 return -ENOMEM;
 379
 380         cpsw_ale_write(priv, idx, ale_entry);
 381         return 0;
 382 }
 383
 384 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
 385                               int port_mask)
 386 {
 387         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 388         int idx, mask;
 389
 390         idx = cpsw_ale_match_addr(priv, addr);
 391         if (idx >= 0)
 392                 cpsw_ale_read(priv, idx, ale_entry);
 393
 394         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 395         cpsw_ale_set_addr(ale_entry, addr);
 396         cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
 397
 398         mask = cpsw_ale_get_port_mask(ale_entry);
 399         port_mask |= mask;
 400         cpsw_ale_set_port_mask(ale_entry, port_mask);
 401
 402         if (idx < 0)
 403                 idx = cpsw_ale_match_free(priv);
 404         if (idx < 0)
 405                 idx = cpsw_ale_find_ageable(priv);
 406         if (idx < 0)
 407                 return -ENOMEM;
 408
 409         cpsw_ale_write(priv, idx, ale_entry);
 410         return 0;
 411 }
 412
 413 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
 414 {
 415         u32 tmp, mask = BIT(bit);
 416
 417         tmp  = __raw_readl(priv->ale_regs + ALE_CONTROL);
 418         tmp &= ~mask;
 419         tmp |= val ? mask : 0;
 420         __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
 421 }
 422
 423 #define cpsw_ale_enable(priv, val)      cpsw_ale_control(priv, 31, val)
 424 #define cpsw_ale_clear(priv, val)       cpsw_ale_control(priv, 30, val)
 425 #define cpsw_ale_vlan_aware(priv, val)  cpsw_ale_control(priv,  2, val)
 426
 427 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
 428                                        int val)
 429 {
 430         int offset = ALE_PORTCTL + 4 * port;
 431         u32 tmp, mask = 0x3;
 432
 433         tmp  = __raw_readl(priv->ale_regs + offset);
 434         tmp &= ~mask;
 435         tmp |= val & mask;
 436         __raw_writel(tmp, priv->ale_regs + offset);
 437 }
 438
 439 /* Set a self-clearing bit in a register, and wait for it to clear */
 440 static inline void setbit_and_wait_for_clear32(void *addr)
 441 {
 442         __raw_writel(CLEAR_BIT, addr);
 443         while (__raw_readl(addr) & CLEAR_BIT)
 444                 ;
 445 }
 446
 447 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 448                          ((mac)[2] << 16) | ((mac)[3] << 24))
 449 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 450
 451 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 452                                struct cpsw_priv *priv)
 453 {
 454 #ifdef CONFIG_DM_ETH
 455         struct eth_pdata *pdata = dev_get_platdata(priv->dev);
 456
 457         writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
 458         writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
 459 #else
 460         __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
 461         __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
 462 #endif
 463 }
 464
 465 static int cpsw_slave_update_link(struct cpsw_slave *slave,
 466                                    struct cpsw_priv *priv, int *link)
 467 {
 468         struct phy_device *phy;
 469         u32 mac_control = 0;
 470         int ret = -ENODEV;
 471
 472         phy = priv->phydev;
 473         if (!phy)
 474                 goto out;
 475
 476         ret = phy_startup(phy);
 477         if (ret)
 478                 goto out;
 479
 480         if (link)
 481                 *link = phy->link;
 482
 483         if (phy->link) { /* link up */
 484                 mac_control = priv->data->mac_control;
 485                 if (phy->speed == 1000)
 486                         mac_control |= GIGABITEN;
 487                 if (phy->duplex == DUPLEX_FULL)
 488                         mac_control |= FULLDUPLEXEN;
 489                 if (phy->speed == 100)
 490                         mac_control |= MIIEN;
 491                 if (phy->speed == 10 && phy_interface_is_rgmii(phy))
 492                         mac_control |= CTL_EXT_EN;
 493         }
 494
 495         if (mac_control == slave->mac_control)
 496                 goto out;
 497
 498         if (mac_control) {
 499                 printf("link up on port %d, speed %d, %s duplex\n",
 500                                 slave->slave_num, phy->speed,
 501                                 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
 502         } else {
 503                 printf("link down on port %d\n", slave->slave_num);
 504         }
 505
 506         __raw_writel(mac_control, &slave->sliver->mac_control);
 507         slave->mac_control = mac_control;
 508
 509 out:
 510         return ret;
 511 }
 512
 513 static int cpsw_update_link(struct cpsw_priv *priv)
 514 {
 515         int ret = -ENODEV;
 516         struct cpsw_slave *slave;
 517
 518         for_active_slave(slave, priv)
 519                 ret = cpsw_slave_update_link(slave, priv, NULL);
 520
 521         return ret;
 522 }
 523
 524 static inline u32  cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 525 {
 526         if (priv->host_port == 0)
 527                 return slave_num + 1;
 528         else
 529                 return slave_num;
 530 }
 531
 532 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 533 {
 534         u32     slave_port;
 535
 536         setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
 537
 538         /* setup priority mapping */
 539         __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
 540         __raw_writel(0x33221100, &slave->regs->tx_pri_map);
 541
 542         /* setup max packet size, and mac address */
 543         __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
 544         cpsw_set_slave_mac(slave, priv);
 545
 546         slave->mac_control = 0; /* no link yet */
 547
 548         /* enable forwarding */
 549         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 550         cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
 551
 552         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
 553
 554         priv->phy_mask |= 1 << slave->data->phy_addr;
 555 }
 556
 557 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
 558 {
 559         struct cpdma_desc *desc = priv->desc_free;
 560
 561         if (desc)
 562                 priv->desc_free = desc_read_ptr(desc, hw_next);
 563         return desc;
 564 }
 565
 566 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
 567 {
 568         if (desc) {
 569                 desc_write(desc, hw_next, priv->desc_free);
 570                 priv->desc_free = desc;
 571         }
 572 }
 573
 574 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
 575                         void *buffer, int len)
 576 {
 577         struct cpdma_desc *desc, *prev;
 578         u32 mode;
 579
 580         desc = cpdma_desc_alloc(priv);
 581         if (!desc)
 582                 return -ENOMEM;
 583
 584         if (len < PKT_MIN)
 585                 len = PKT_MIN;
 586
 587         mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
 588
 589         desc_write(desc, hw_next,   0);
 590         desc_write(desc, hw_buffer, buffer);
 591         desc_write(desc, hw_len,    len);
 592         desc_write(desc, hw_mode,   mode | len);
 593         desc_write(desc, sw_buffer, buffer);
 594         desc_write(desc, sw_len,    len);
 595
 596         if (!chan->head) {
 597                 /* simple case - first packet enqueued */
 598                 chan->head = desc;
 599                 chan->tail = desc;
 600                 chan_write(chan, hdp, desc);
 601                 goto done;
 602         }
 603
 604         /* not the first packet - enqueue at the tail */
 605         prev = chan->tail;
 606         desc_write(prev, hw_next, desc);
 607         chan->tail = desc;
 608
 609         /* next check if EOQ has been triggered already */
 610         if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
 611                 chan_write(chan, hdp, desc);
 612
 613 done:
 614         if (chan->rxfree)
 615                 chan_write(chan, rxfree, 1);
 616         return 0;
 617 }
 618
 619 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
 620                          void **buffer, int *len)
 621 {
 622         struct cpdma_desc *desc = chan->head;
 623         u32 status;
 624
 625         if (!desc)
 626                 return -ENOENT;
 627
 628         status = desc_read(desc, hw_mode);
 629
 630         if (len)
 631                 *len = status & 0x7ff;
 632
 633         if (buffer)
 634                 *buffer = desc_read_ptr(desc, sw_buffer);
 635
 636         if (status & CPDMA_DESC_OWNER) {
 637                 if (chan_read(chan, hdp) == 0) {
 638                         if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
 639                                 chan_write(chan, hdp, desc);
 640                 }
 641
 642                 return -EBUSY;
 643         }
 644
 645         chan->head = desc_read_ptr(desc, hw_next);
 646         chan_write(chan, cp, desc);
 647
 648         cpdma_desc_free(priv, desc);
 649         return 0;
 650 }
 651
 652 static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
 653 {
 654         struct cpsw_slave       *slave;
 655         int i, ret;
 656
 657         /* soft reset the controller and initialize priv */
 658         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 659
 660         /* initialize and reset the address lookup engine */
 661         cpsw_ale_enable(priv, 1);
 662         cpsw_ale_clear(priv, 1);
 663         cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
 664
 665         /* setup host port priority mapping */
 666         __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
 667         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 668
 669         /* disable priority elevation and enable statistics on all ports */
 670         __raw_writel(0, &priv->regs->ptype);
 671
 672         /* enable statistics collection only on the host port */
 673         __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
 674         __raw_writel(0x7, &priv->regs->stat_port_en);
 675
 676         cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
 677
 678         cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
 679         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
 680
 681         for_active_slave(slave, priv)
 682                 cpsw_slave_init(slave, priv);
 683
 684         ret = cpsw_update_link(priv);
 685         if (ret)
 686                 goto out;
 687
 688         /* init descriptor pool */
 689         for (i = 0; i < NUM_DESCS; i++) {
 690                 desc_write(&priv->descs[i], hw_next,
 691                            (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
 692         }
 693         priv->desc_free = &priv->descs[0];
 694
 695         /* initialize channels */
 696         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 697                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 698                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER2;
 699                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER2;
 700                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 701
 702                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 703                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER2;
 704                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER2;
 705         } else {
 706                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 707                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER1;
 708                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER1;
 709                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 710
 711                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 712                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER1;
 713                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER1;
 714         }
 715
 716         /* clear dma state */
 717         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 718
 719         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 720                 for (i = 0; i < priv->data->channels; i++) {
 721                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
 722                                         * i);
 723                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 724                                         * i);
 725                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
 726                                         * i);
 727                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
 728                                         * i);
 729                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
 730                                         * i);
 731                 }
 732         } else {
 733                 for (i = 0; i < priv->data->channels; i++) {
 734                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
 735                                         * i);
 736                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 737                                         * i);
 738                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
 739                                         * i);
 740                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
 741                                         * i);
 742                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
 743                                         * i);
 744
 745                 }
 746         }
 747
 748         __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
 749         __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
 750
 751         /* submit rx descs */
 752         for (i = 0; i < PKTBUFSRX; i++) {
 753                 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
 754                                    PKTSIZE);
 755                 if (ret < 0) {
 756                         printf("error %d submitting rx desc\n", ret);
 757                         break;
 758                 }
 759         }
 760
 761 out:
 762         return ret;
 763 }
 764
 765 static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
 766 {
 767         int timeout = CPDMA_TIMEOUT;
 768
 769         /* reap completed packets */
 770         while (timeout-- &&
 771                (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
 772                 ;
 773
 774         return timeout;
 775 }
 776
 777 static void _cpsw_halt(struct cpsw_priv *priv)
 778 {
 779         cpsw_reap_completed_packets(priv);
 780
 781         writel(0, priv->dma_regs + CPDMA_TXCONTROL);
 782         writel(0, priv->dma_regs + CPDMA_RXCONTROL);
 783
 784         /* soft reset the controller and initialize priv */
 785         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 786
 787         /* clear dma state */
 788         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 789
 790 }
 791
 792 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
 793 {
 794         int timeout;
 795
 796         flush_dcache_range((unsigned long)packet,
 797                            (unsigned long)packet + ALIGN(length, PKTALIGN));
 798
 799         timeout = cpsw_reap_completed_packets(priv);
 800         if (timeout == -1) {
 801                 printf("cpdma_process timeout\n");
 802                 return -ETIMEDOUT;
 803         }
 804
 805         return cpdma_submit(priv, &priv->tx_chan, packet, length);
 806 }
 807
 808 static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
 809 {
 810         void *buffer;
 811         int len;
 812         int ret;
 813
 814         ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
 815         if (ret < 0)
 816                 return ret;
 817
 818         invalidate_dcache_range((unsigned long)buffer,
 819                                 (unsigned long)buffer + PKTSIZE_ALIGN);
 820         *pkt = buffer;
 821
 822         return len;
 823 }
 824
 825 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
 826                             struct cpsw_priv *priv)
 827 {
 828         void                    *regs = priv->regs;
 829         struct cpsw_slave_data  *data = priv->data->slave_data + slave_num;
 830         slave->slave_num = slave_num;
 831         slave->data     = data;
 832         slave->regs     = regs + data->slave_reg_ofs;
 833         slave->sliver   = regs + data->sliver_reg_ofs;
 834 }
 835
 836 static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
 837 {
 838         struct phy_device *phydev;
 839         u32 supported = PHY_GBIT_FEATURES;
 840         int ret;
 841
 842         phydev = phy_connect(priv->bus,
 843                         slave->data->phy_addr,
 844                         priv->dev,
 845                         slave->data->phy_if);
 846
 847         if (!phydev)
 848                 return -1;
 849
 850         phydev->supported &= supported;
 851         if (slave->data->max_speed) {
 852                 ret = phy_set_supported(phydev, slave->data->max_speed);
 853                 if (ret)
 854                         return ret;
 855                 dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
 856                         slave->slave_num + 1, slave->data->max_speed);
 857         }
 858         phydev->advertising = phydev->supported;
 859
 860 #ifdef CONFIG_DM_ETH
 861         if (ofnode_valid(slave->data->phy_of_handle))
 862                 phydev->node = slave->data->phy_of_handle;
 863 #endif
 864
 865         priv->phydev = phydev;
 866         phy_config(phydev);
 867
 868         return 1;
 869 }
 870
 871 static void cpsw_phy_addr_update(struct cpsw_priv *priv)
 872 {
 873         struct cpsw_platform_data *data = priv->data;
 874         u16 alive = cpsw_mdio_get_alive(priv->bus);
 875         int active = data->active_slave;
 876         int new_addr = ffs(alive) - 1;
 877
 878         /*
 879          * If there is only one phy alive and its address does not match
 880          * that of active slave, then phy address can safely be updated.
 881          */
 882         if (hweight16(alive) == 1 &&
 883             data->slave_data[active].phy_addr != new_addr) {
 884                 printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
 885                        active, data->slave_data[active].phy_addr, new_addr);
 886                 data->slave_data[active].phy_addr = new_addr;
 887         }
 888 }
 889
 890 int _cpsw_register(struct cpsw_priv *priv)
 891 {
 892         struct cpsw_slave       *slave;
 893         struct cpsw_platform_data *data = priv->data;
 894         void                    *regs = (void *)data->cpsw_base;
 895
 896         priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
 897         if (!priv->slaves) {
 898                 return -ENOMEM;
 899         }
 900
 901         priv->host_port         = data->host_port_num;
 902         priv->regs              = regs;
 903         priv->host_port_regs    = regs + data->host_port_reg_ofs;
 904         priv->dma_regs          = regs + data->cpdma_reg_ofs;
 905         priv->ale_regs          = regs + data->ale_reg_ofs;
 906         priv->descs             = (void *)regs + data->bd_ram_ofs;
 907
 908         int idx = 0;
 909
 910         for_each_slave(slave, priv) {
 911                 cpsw_slave_setup(slave, idx, priv);
 912                 idx = idx + 1;
 913         }
 914
 915         priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
 916         if (!priv->bus)
 917                 return -EFAULT;
 918
 919         cpsw_phy_addr_update(priv);
 920
 921         for_active_slave(slave, priv)
 922                 cpsw_phy_init(priv, slave);
 923
 924         return 0;
 925 }
 926
 927 #ifndef CONFIG_DM_ETH
 928 static int cpsw_init(struct eth_device *dev, bd_t *bis)
 929 {
 930         struct cpsw_priv        *priv = dev->priv;
 931
 932         return _cpsw_init(priv, dev->enetaddr);
 933 }
 934
 935 static void cpsw_halt(struct eth_device *dev)
 936 {
 937         struct cpsw_priv *priv = dev->priv;
 938
 939         return _cpsw_halt(priv);
 940 }
 941
 942 static int cpsw_send(struct eth_device *dev, void *packet, int length)
 943 {
 944         struct cpsw_priv        *priv = dev->priv;
 945
 946         return _cpsw_send(priv, packet, length);
 947 }
 948
 949 static int cpsw_recv(struct eth_device *dev)
 950 {
 951         struct cpsw_priv *priv = dev->priv;
 952         uchar *pkt = NULL;
 953         int len;
 954
 955         len = _cpsw_recv(priv, &pkt);
 956
 957         if (len > 0) {
 958                 net_process_received_packet(pkt, len);
 959                 cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
 960         }
 961
 962         return len;
 963 }
 964
 965 int cpsw_register(struct cpsw_platform_data *data)
 966 {
 967         struct cpsw_priv        *priv;
 968         struct eth_device       *dev;
 969         int ret;
 970
 971         dev = calloc(sizeof(*dev), 1);
 972         if (!dev)
 973                 return -ENOMEM;
 974
 975         priv = calloc(sizeof(*priv), 1);
 976         if (!priv) {
 977                 free(dev);
 978                 return -ENOMEM;
 979         }
 980
 981         priv->dev = dev;
 982         priv->data = data;
 983
 984         strcpy(dev->name, "cpsw");
 985         dev->iobase     = 0;
 986         dev->init       = cpsw_init;
 987         dev->halt       = cpsw_halt;
 988         dev->send       = cpsw_send;
 989         dev->recv       = cpsw_recv;
 990         dev->priv       = priv;
 991
 992         eth_register(dev);
 993
 994         ret = _cpsw_register(priv);
 995         if (ret < 0) {
 996                 eth_unregister(dev);
 997                 free(dev);
 998                 free(priv);
 999                 return ret;
1000         }
1001
1002         return 1;
1003 }
1004 #else
1005 static int cpsw_eth_start(struct udevice *dev)
1006 {
1007         struct eth_pdata *pdata = dev_get_platdata(dev);
1008         struct cpsw_priv *priv = dev_get_priv(dev);
1009
1010         return _cpsw_init(priv, pdata->enetaddr);
1011 }
1012
1013 static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
1014 {
1015         struct cpsw_priv *priv = dev_get_priv(dev);
1016
1017         return _cpsw_send(priv, packet, length);
1018 }
1019
1020 static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1021 {
1022         struct cpsw_priv *priv = dev_get_priv(dev);
1023
1024         return _cpsw_recv(priv, packetp);
1025 }
1026
1027 static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
1028                                    int length)
1029 {
1030         struct cpsw_priv *priv = dev_get_priv(dev);
1031
1032         return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
1033 }
1034
1035 static void cpsw_eth_stop(struct udevice *dev)
1036 {
1037         struct cpsw_priv *priv = dev_get_priv(dev);
1038
1039         return _cpsw_halt(priv);
1040 }
1041
1042 static const struct eth_ops cpsw_eth_ops = {
1043         .start          = cpsw_eth_start,
1044         .send           = cpsw_eth_send,
1045         .recv           = cpsw_eth_recv,
1046         .free_pkt       = cpsw_eth_free_pkt,
1047         .stop           = cpsw_eth_stop,
1048 };
1049
1050 static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
1051                                  phy_interface_t phy_mode)
1052 {
1053         u32 reg;
1054         u32 mask;
1055         u32 mode = 0;
1056         bool rgmii_id = false;
1057         int slave = priv->data->active_slave;
1058
1059         reg = readl(priv->data->gmii_sel);
1060
1061         switch (phy_mode) {
1062         case PHY_INTERFACE_MODE_RMII:
1063                 mode = AM33XX_GMII_SEL_MODE_RMII;
1064                 break;
1065
1066         case PHY_INTERFACE_MODE_RGMII:
1067         case PHY_INTERFACE_MODE_RGMII_RXID:
1068                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1069                 break;
1070         case PHY_INTERFACE_MODE_RGMII_ID:
1071         case PHY_INTERFACE_MODE_RGMII_TXID:
1072                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1073                 rgmii_id = true;
1074                 break;
1075
1076         case PHY_INTERFACE_MODE_MII:
1077         default:
1078                 mode = AM33XX_GMII_SEL_MODE_MII;
1079                 break;
1080         };
1081
1082         mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
1083         mode <<= slave * 2;
1084
1085         if (priv->data->rmii_clock_external) {
1086                 if (slave == 0)
1087                         mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
1088                 else
1089                         mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
1090         }
1091
1092         if (rgmii_id) {
1093                 if (slave == 0)
1094                         mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
1095                 else
1096                         mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
1097         }
1098
1099         reg &= ~mask;
1100         reg |= mode;
1101
1102         writel(reg, priv->data->gmii_sel);
1103 }
1104
1105 static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
1106                                  phy_interface_t phy_mode)
1107 {
1108         u32 reg;
1109         u32 mask;
1110         u32 mode = 0;
1111         int slave = priv->data->active_slave;
1112
1113         reg = readl(priv->data->gmii_sel);
1114
1115         switch (phy_mode) {
1116         case PHY_INTERFACE_MODE_RMII:
1117                 mode = AM33XX_GMII_SEL_MODE_RMII;
1118                 break;
1119
1120         case PHY_INTERFACE_MODE_RGMII:
1121         case PHY_INTERFACE_MODE_RGMII_ID:
1122         case PHY_INTERFACE_MODE_RGMII_RXID:
1123         case PHY_INTERFACE_MODE_RGMII_TXID:
1124                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1125                 break;
1126
1127         case PHY_INTERFACE_MODE_MII:
1128         default:
1129                 mode = AM33XX_GMII_SEL_MODE_MII;
1130                 break;
1131         };
1132
1133         switch (slave) {
1134         case 0:
1135                 mask = GMII_SEL_MODE_MASK;
1136                 break;
1137         case 1:
1138                 mask = GMII_SEL_MODE_MASK << 4;
1139                 mode <<= 4;
1140                 break;
1141         default:
1142                 dev_err(priv->dev, "invalid slave number...\n");
1143                 return;
1144         }
1145
1146         if (priv->data->rmii_clock_external)
1147                 dev_err(priv->dev, "RMII External clock is not supported\n");
1148
1149         reg &= ~mask;
1150         reg |= mode;
1151
1152         writel(reg, priv->data->gmii_sel);
1153 }
1154
1155 static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
1156                          phy_interface_t phy_mode)
1157 {
1158         if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
1159                 cpsw_gmii_sel_am3352(priv, phy_mode);
1160         if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
1161                 cpsw_gmii_sel_am3352(priv, phy_mode);
1162         else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
1163                 cpsw_gmii_sel_dra7xx(priv, phy_mode);
1164 }
1165
1166 static int cpsw_eth_probe(struct udevice *dev)
1167 {
1168         struct cpsw_priv *priv = dev_get_priv(dev);
1169         struct eth_pdata *pdata = dev_get_platdata(dev);
1170
1171         priv->dev = dev;
1172         priv->data = pdata->priv_pdata;
1173         ti_cm_get_macid(dev, priv->data, pdata->enetaddr);
1174         /* Select phy interface in control module */
1175         cpsw_phy_sel(priv, priv->data->phy_sel_compat,
1176                      pdata->phy_interface);
1177
1178         return _cpsw_register(priv);
1179 }
1180
1181 #if CONFIG_IS_ENABLED(OF_CONTROL)
1182 static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data,
1183                                     int slave_index, ofnode subnode)
1184 {
1185         struct ofnode_phandle_args out_args;
1186         struct cpsw_slave_data *slave_data;
1187         const char *phy_mode;
1188         u32 phy_id[2];
1189         int ret;
1190
1191         slave_data = &data->slave_data[slave_index];
1192
1193         phy_mode = ofnode_read_string(subnode, "phy-mode");
1194         if (phy_mode)
1195                 slave_data->phy_if = phy_get_interface_by_name(phy_mode);
1196
1197         ret = ofnode_parse_phandle_with_args(subnode, "phy-handle",
1198                                              NULL, 0, 0, &out_args);
1199         if (!ret) {
1200                 slave_data->phy_of_handle = out_args.node;
1201
1202                 ret = ofnode_read_s32(slave_data->phy_of_handle, "reg",
1203                                       &slave_data->phy_addr);
1204                 if (ret)
1205                         printf("error: phy addr not found in dt\n");
1206         } else {
1207                 ret = ofnode_read_u32_array(subnode, "phy_id", phy_id, 2);
1208                 if (ret)
1209                         printf("error: phy_id read failed\n");
1210         }
1211
1212         slave_data->max_speed = ofnode_read_s32_default(subnode,
1213                                                         "max-speed", 0);
1214 }
1215
1216 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
1217 {
1218         struct eth_pdata *pdata = dev_get_platdata(dev);
1219         struct cpsw_platform_data *data;
1220         struct gpio_desc *mode_gpios;
1221         int slave_index = 0;
1222         int num_mode_gpios;
1223         ofnode subnode;
1224         int ret;
1225
1226         data = calloc(1, sizeof(struct cpsw_platform_data));
1227         pdata->priv_pdata = data;
1228         pdata->iobase = dev_read_addr(dev);
1229         data->version = CPSW_CTRL_VERSION_2;
1230         data->bd_ram_ofs = CPSW_BD_OFFSET;
1231         data->ale_reg_ofs = CPSW_ALE_OFFSET;
1232         data->cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
1233         data->mdio_div = CPSW_MDIO_DIV;
1234         data->host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
1235
1236         pdata->phy_interface = -1;
1237
1238         data->cpsw_base = pdata->iobase;
1239
1240         ret = dev_read_s32(dev, "cpdma_channels", &data->channels);
1241         if (ret) {
1242                 printf("error: cpdma_channels not found in dt\n");
1243                 return ret;
1244         }
1245
1246         ret = dev_read_s32(dev, "slaves", &data->slaves);
1247         if (ret) {
1248                 printf("error: slaves not found in dt\n");
1249                 return ret;
1250         }
1251         data->slave_data = malloc(sizeof(struct cpsw_slave_data) *
1252                                        data->slaves);
1253
1254         ret = dev_read_s32(dev, "ale_entries", &data->ale_entries);
1255         if (ret) {
1256                 printf("error: ale_entries not found in dt\n");
1257                 return ret;
1258         }
1259
1260         ret = dev_read_u32(dev, "bd_ram_size", &data->bd_ram_ofs);
1261         if (ret) {
1262                 printf("error: bd_ram_size not found in dt\n");
1263                 return ret;
1264         }
1265
1266         ret = dev_read_u32(dev, "mac_control", &data->mac_control);
1267         if (ret) {
1268                 printf("error: ale_entries not found in dt\n");
1269                 return ret;
1270         }
1271
1272         num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
1273         if (num_mode_gpios > 0) {
1274                 mode_gpios = malloc(sizeof(struct gpio_desc) *
1275                                     num_mode_gpios);
1276                 gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
1277                                           num_mode_gpios, GPIOD_IS_OUT);
1278                 free(mode_gpios);
1279         }
1280
1281         data->active_slave = dev_read_u32_default(dev, "active_slave", 0);
1282
1283         ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
1284                 const char *name;
1285
1286                 name = ofnode_get_name(subnode);
1287                 if (!strncmp(name, "mdio", 4)) {
1288                         data->mdio_base = ofnode_get_addr(subnode);
1289                         if (data->mdio_base == FDT_ADDR_T_NONE) {
1290                                 pr_err("Not able to get MDIO address space\n");
1291                                 return -ENOENT;
1292                         }
1293                 }
1294
1295                 if (!strncmp(name, "slave", 5)) {
1296                         if (slave_index >= data->slaves)
1297                                 continue;
1298
1299                         cpsw_eth_of_parse_slave(data, slave_index, subnode);
1300                         slave_index++;
1301                 }
1302
1303                 if (!strncmp(name, "cpsw-phy-sel", 12)) {
1304                         data->gmii_sel = ofnode_get_addr(subnode);
1305
1306                         if (data->gmii_sel == FDT_ADDR_T_NONE) {
1307                                 pr_err("Not able to get gmii_sel reg address\n");
1308                                 return -ENOENT;
1309                         }
1310
1311                         if (ofnode_read_bool(subnode, "rmii-clock-ext"))
1312                                 data->rmii_clock_external = true;
1313
1314                         data->phy_sel_compat = ofnode_read_string(subnode,
1315                                                                   "compatible");
1316                         if (!data->phy_sel_compat) {
1317                                 pr_err("Not able to get gmii_sel compatible\n");
1318                                 return -ENOENT;
1319                         }
1320                 }
1321         }
1322
1323         data->slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
1324         data->slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
1325
1326         if (data->slaves == 2) {
1327                 data->slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
1328                 data->slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
1329         }
1330
1331         ret = ti_cm_get_macid_addr(dev, data->active_slave, data);
1332         if (ret < 0) {
1333                 pr_err("cpsw read efuse mac failed\n");
1334                 return ret;
1335         }
1336
1337         pdata->phy_interface = data->slave_data[data->active_slave].phy_if;
1338         if (pdata->phy_interface == -1) {
1339                 debug("%s: Invalid PHY interface '%s'\n", __func__,
1340                       phy_string_for_interface(pdata->phy_interface));
1341                 return -EINVAL;
1342         }
1343
1344         return 0;
1345 }
1346
1347 static const struct udevice_id cpsw_eth_ids[] = {
1348         { .compatible = "ti,cpsw" },
1349         { .compatible = "ti,am335x-cpsw" },
1350         { }
1351 };
1352 #endif
1353
1354 int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
1355 {
1356         struct cpsw_priv *priv = dev_get_priv(dev);
1357         struct cpsw_platform_data *data = priv->data;
1358
1359         return data->slave_data[slave].phy_addr;
1360 }
1361
1362 U_BOOT_DRIVER(eth_cpsw) = {
1363         .name   = "eth_cpsw",
1364         .id     = UCLASS_ETH,
1365 #if CONFIG_IS_ENABLED(OF_CONTROL)
1366         .of_match = cpsw_eth_ids,
1367         .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
1368         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1369 #endif
1370         .probe  = cpsw_eth_probe,
1371         .ops    = &cpsw_eth_ops,
1372         .priv_auto_alloc_size = sizeof(struct cpsw_priv),
1373         .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
1374 };
1375 #endif /* CONFIG_DM_ETH */