drivers/net/sh_eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * sh_eth.c - Driver for Renesas ethernet controller.
   4  *
   5  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   6  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
   7  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   8  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   9  */
  10
  11 #include <config.h>
  12 #include <common.h>
  13 #include <cpu_func.h>
  14 #include <env.h>
  15 #include <log.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <netdev.h>
  19 #include <miiphy.h>
  20 #include <asm/cache.h>
  21 #include <linux/delay.h>
  22 #include <linux/errno.h>
  23 #include <asm/io.h>
  24
  25 #ifdef CONFIG_DM_ETH
  26 #include <clk.h>
  27 #include <dm.h>
  28 #include <linux/mii.h>
  29 #include <asm/gpio.h>
  30 #endif
  31
  32 #include "sh_eth.h"
  33
  34 #ifndef CONFIG_SH_ETHER_USE_PORT
  35 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  36 #endif
  37 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  38 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  39 #endif
  40
  41 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
  42         !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  43 #define flush_cache_wback(addr, len)    \
  44                 flush_dcache_range((unsigned long)addr, \
  45                 (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
  46 #else
  47 #define flush_cache_wback(...)
  48 #endif
  49
  50 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  51 #define invalidate_cache(addr, len)             \
  52         {       \
  53                 unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;  \
  54                 unsigned long start, end;       \
  55                 \
  56                 start = (unsigned long)addr;    \
  57                 end = start + len;              \
  58                 start &= ~(line_size - 1);      \
  59                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  60                 \
  61                 invalidate_dcache_range(start, end);    \
  62         }
  63 #else
  64 #define invalidate_cache(...)
  65 #endif
  66
  67 #define TIMEOUT_CNT 1000
  68
  69 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
  70 {
  71         int ret = 0, timeout;
  72         struct sh_eth_info *port_info = &eth->port_info[eth->port];
  73
  74         if (!packet || len > 0xffff) {
  75                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  76                 ret = -EINVAL;
  77                 goto err;
  78         }
  79
  80         /* packet must be a 4 byte boundary */
  81         if ((uintptr_t)packet & 3) {
  82                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  83                                 , __func__);
  84                 ret = -EFAULT;
  85                 goto err;
  86         }
  87
  88         /* Update tx descriptor */
  89         flush_cache_wback(packet, len);
  90         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  91         port_info->tx_desc_cur->td1 = len << 16;
  92         /* Must preserve the end of descriptor list indication */
  93         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  94                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  95         else
  96                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  97
  98         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  99
 100         /* Restart the transmitter if disabled */
 101         if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
 102                 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
 103
 104         /* Wait until packet is transmitted */
 105         timeout = TIMEOUT_CNT;
 106         do {
 107                 invalidate_cache(port_info->tx_desc_cur,
 108                                  sizeof(struct tx_desc_s));
 109                 udelay(100);
 110         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
 111
 112         if (timeout < 0) {
 113                 printf(SHETHER_NAME ": transmit timeout\n");
 114                 ret = -ETIMEDOUT;
 115                 goto err;
 116         }
 117
 118         port_info->tx_desc_cur++;
 119         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 120                 port_info->tx_desc_cur = port_info->tx_desc_base;
 121
 122 err:
 123         return ret;
 124 }
 125
 126 static int sh_eth_recv_start(struct sh_eth_dev *eth)
 127 {
 128         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 129
 130         /* Check if the rx descriptor is ready */
 131         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 132         if (port_info->rx_desc_cur->rd0 & RD_RACT)
 133                 return -EINVAL;
 134
 135         /* Check for errors */
 136         if (port_info->rx_desc_cur->rd0 & RD_RFE)
 137                 return -EINVAL;
 138
 139         return port_info->rx_desc_cur->rd1 & 0xffff;
 140 }
 141
 142 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
 143 {
 144         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 145
 146         /* Make current descriptor available again */
 147         if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 148                 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 149         else
 150                 port_info->rx_desc_cur->rd0 = RD_RACT;
 151
 152         flush_cache_wback(port_info->rx_desc_cur,
 153                           sizeof(struct rx_desc_s));
 154
 155         /* Point to the next descriptor */
 156         port_info->rx_desc_cur++;
 157         if (port_info->rx_desc_cur >=
 158             port_info->rx_desc_base + NUM_RX_DESC)
 159                 port_info->rx_desc_cur = port_info->rx_desc_base;
 160 }
 161
 162 static int sh_eth_reset(struct sh_eth_dev *eth)
 163 {
 164         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 165 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 166         int ret = 0, i;
 167
 168         /* Start e-dmac transmitter and receiver */
 169         sh_eth_write(port_info, EDSR_ENALL, EDSR);
 170
 171         /* Perform a software reset and wait for it to complete */
 172         sh_eth_write(port_info, EDMR_SRST, EDMR);
 173         for (i = 0; i < TIMEOUT_CNT; i++) {
 174                 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
 175                         break;
 176                 udelay(1000);
 177         }
 178
 179         if (i == TIMEOUT_CNT) {
 180                 printf(SHETHER_NAME  ": Software reset timeout\n");
 181                 ret = -EIO;
 182         }
 183
 184         return ret;
 185 #else
 186         sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
 187         mdelay(3);
 188         sh_eth_write(port_info,
 189                      sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
 190
 191         return 0;
 192 #endif
 193 }
 194
 195 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 196 {
 197         int i, ret = 0;
 198         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 199         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 200         struct tx_desc_s *cur_tx_desc;
 201
 202         /*
 203          * Allocate rx descriptors. They must be aligned to size of struct
 204          * tx_desc_s.
 205          */
 206         port_info->tx_desc_alloc =
 207                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
 208         if (!port_info->tx_desc_alloc) {
 209                 printf(SHETHER_NAME ": memalign failed\n");
 210                 ret = -ENOMEM;
 211                 goto err;
 212         }
 213
 214         flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
 215
 216         /* Make sure we use a P2 address (non-cacheable) */
 217         port_info->tx_desc_base =
 218                 (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
 219         port_info->tx_desc_cur = port_info->tx_desc_base;
 220
 221         /* Initialize all descriptors */
 222         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 223              cur_tx_desc++, i++) {
 224                 cur_tx_desc->td0 = 0x00;
 225                 cur_tx_desc->td1 = 0x00;
 226                 cur_tx_desc->td2 = 0x00;
 227         }
 228
 229         /* Mark the end of the descriptors */
 230         cur_tx_desc--;
 231         cur_tx_desc->td0 |= TD_TDLE;
 232
 233         /*
 234          * Point the controller to the tx descriptor list. Must use physical
 235          * addresses
 236          */
 237         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 238 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 239         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 240         sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 241         sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
 242 #endif
 243
 244 err:
 245         return ret;
 246 }
 247
 248 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 249 {
 250         int i, ret = 0;
 251         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 252         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 253         struct rx_desc_s *cur_rx_desc;
 254         u8 *rx_buf;
 255
 256         /*
 257          * Allocate rx descriptors. They must be aligned to size of struct
 258          * rx_desc_s.
 259          */
 260         port_info->rx_desc_alloc =
 261                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
 262         if (!port_info->rx_desc_alloc) {
 263                 printf(SHETHER_NAME ": memalign failed\n");
 264                 ret = -ENOMEM;
 265                 goto err;
 266         }
 267
 268         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
 269
 270         /* Make sure we use a P2 address (non-cacheable) */
 271         port_info->rx_desc_base =
 272                 (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
 273
 274         port_info->rx_desc_cur = port_info->rx_desc_base;
 275
 276         /*
 277          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
 278          * aligned and in P2 area.
 279          */
 280         port_info->rx_buf_alloc =
 281                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
 282         if (!port_info->rx_buf_alloc) {
 283                 printf(SHETHER_NAME ": alloc failed\n");
 284                 ret = -ENOMEM;
 285                 goto err_buf_alloc;
 286         }
 287
 288         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
 289
 290         /* Initialize all descriptors */
 291         for (cur_rx_desc = port_info->rx_desc_base,
 292              rx_buf = port_info->rx_buf_base, i = 0;
 293              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 294                 cur_rx_desc->rd0 = RD_RACT;
 295                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 296                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
 297         }
 298
 299         /* Mark the end of the descriptors */
 300         cur_rx_desc--;
 301         cur_rx_desc->rd0 |= RD_RDLE;
 302
 303         /* Point the controller to the rx descriptor list */
 304         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 305 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 306         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 307         sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 308         sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
 309 #endif
 310
 311         return ret;
 312
 313 err_buf_alloc:
 314         free(port_info->rx_desc_alloc);
 315         port_info->rx_desc_alloc = NULL;
 316
 317 err:
 318         return ret;
 319 }
 320
 321 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 322 {
 323         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 324
 325         if (port_info->tx_desc_alloc) {
 326                 free(port_info->tx_desc_alloc);
 327                 port_info->tx_desc_alloc = NULL;
 328         }
 329 }
 330
 331 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 332 {
 333         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 334
 335         if (port_info->rx_desc_alloc) {
 336                 free(port_info->rx_desc_alloc);
 337                 port_info->rx_desc_alloc = NULL;
 338         }
 339
 340         if (port_info->rx_buf_alloc) {
 341                 free(port_info->rx_buf_alloc);
 342                 port_info->rx_buf_alloc = NULL;
 343         }
 344 }
 345
 346 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 347 {
 348         int ret = 0;
 349
 350         ret = sh_eth_tx_desc_init(eth);
 351         if (ret)
 352                 goto err_tx_init;
 353
 354         ret = sh_eth_rx_desc_init(eth);
 355         if (ret)
 356                 goto err_rx_init;
 357
 358         return ret;
 359 err_rx_init:
 360         sh_eth_tx_desc_free(eth);
 361
 362 err_tx_init:
 363         return ret;
 364 }
 365
 366 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
 367                                 unsigned char *mac)
 368 {
 369         u32 val;
 370
 371         val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
 372         sh_eth_write(port_info, val, MAHR);
 373
 374         val = (mac[4] << 8) | mac[5];
 375         sh_eth_write(port_info, val, MALR);
 376 }
 377
 378 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
 379 {
 380         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 381         unsigned long edmr;
 382
 383         /* Configure e-dmac registers */
 384         edmr = sh_eth_read(port_info, EDMR);
 385         edmr &= ~EMDR_DESC_R;
 386         edmr |= EMDR_DESC | EDMR_EL;
 387 #if defined(CONFIG_R8A77980)
 388         edmr |= EDMR_NBST;
 389 #endif
 390         sh_eth_write(port_info, edmr, EDMR);
 391
 392         sh_eth_write(port_info, 0, EESIPR);
 393         sh_eth_write(port_info, 0, TRSCER);
 394         sh_eth_write(port_info, 0, TFTR);
 395         sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 396         sh_eth_write(port_info, RMCR_RST, RMCR);
 397 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 398         sh_eth_write(port_info, 0, RPADIR);
 399 #endif
 400         sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 401
 402         /* Configure e-mac registers */
 403         sh_eth_write(port_info, 0, ECSIPR);
 404
 405         /* Set Mac address */
 406         sh_eth_write_hwaddr(port_info, mac);
 407
 408         sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
 409 #if defined(SH_ETH_TYPE_GETHER)
 410         sh_eth_write(port_info, 0, PIPR);
 411 #endif
 412 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 413         sh_eth_write(port_info, APR_AP, APR);
 414         sh_eth_write(port_info, MPR_MP, MPR);
 415         sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
 416 #endif
 417
 418 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 419         sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 420 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 421         sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 422 #endif
 423 }
 424
 425 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
 426 {
 427         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 428         struct phy_device *phy = port_info->phydev;
 429         int ret = 0;
 430         u32 val = 0;
 431
 432         /* Set the transfer speed */
 433         if (phy->speed == 100) {
 434                 printf(SHETHER_NAME ": 100Base/");
 435 #if defined(SH_ETH_TYPE_GETHER)
 436                 sh_eth_write(port_info, GECMR_100B, GECMR);
 437 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 438                 sh_eth_write(port_info, 1, RTRATE);
 439 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 440                 val = ECMR_RTM;
 441 #endif
 442         } else if (phy->speed == 10) {
 443                 printf(SHETHER_NAME ": 10Base/");
 444 #if defined(SH_ETH_TYPE_GETHER)
 445                 sh_eth_write(port_info, GECMR_10B, GECMR);
 446 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 447                 sh_eth_write(port_info, 0, RTRATE);
 448 #endif
 449         }
 450 #if defined(SH_ETH_TYPE_GETHER)
 451         else if (phy->speed == 1000) {
 452                 printf(SHETHER_NAME ": 1000Base/");
 453                 sh_eth_write(port_info, GECMR_1000B, GECMR);
 454         }
 455 #endif
 456
 457         /* Check if full duplex mode is supported by the phy */
 458         if (phy->duplex) {
 459                 printf("Full\n");
 460                 sh_eth_write(port_info,
 461                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
 462                              ECMR);
 463         } else {
 464                 printf("Half\n");
 465                 sh_eth_write(port_info,
 466                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
 467                              ECMR);
 468         }
 469
 470         return ret;
 471 }
 472
 473 static void sh_eth_start(struct sh_eth_dev *eth)
 474 {
 475         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 476
 477         /*
 478          * Enable the e-dmac receiver only. The transmitter will be enabled when
 479          * we have something to transmit
 480          */
 481         sh_eth_write(port_info, EDRRR_R, EDRRR);
 482 }
 483
 484 static void sh_eth_stop(struct sh_eth_dev *eth)
 485 {
 486         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 487
 488         sh_eth_write(port_info, ~EDRRR_R, EDRRR);
 489 }
 490
 491 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
 492 {
 493         int ret = 0;
 494
 495         ret = sh_eth_reset(eth);
 496         if (ret)
 497                 return ret;
 498
 499         ret = sh_eth_desc_init(eth);
 500         if (ret)
 501                 return ret;
 502
 503         sh_eth_mac_regs_config(eth, mac);
 504
 505         return 0;
 506 }
 507
 508 static int sh_eth_start_common(struct sh_eth_dev *eth)
 509 {
 510         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 511         int ret;
 512
 513         ret = phy_startup(port_info->phydev);
 514         if (ret) {
 515                 printf(SHETHER_NAME ": phy startup failure\n");
 516                 return ret;
 517         }
 518
 519         ret = sh_eth_phy_regs_config(eth);
 520         if (ret)
 521                 return ret;
 522
 523         sh_eth_start(eth);
 524
 525         return 0;
 526 }
 527
 528 #ifndef CONFIG_DM_ETH
 529 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
 530 {
 531         int ret = 0;
 532         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 533         struct eth_device *dev = port_info->dev;
 534         struct phy_device *phydev;
 535
 536         phydev = phy_connect(
 537                         miiphy_get_dev_by_name(dev->name),
 538                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 539         port_info->phydev = phydev;
 540         phy_config(phydev);
 541
 542         return ret;
 543 }
 544
 545 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
 546 {
 547         struct sh_eth_dev *eth = dev->priv;
 548
 549         return sh_eth_send_common(eth, packet, len);
 550 }
 551
 552 static int sh_eth_recv_common(struct sh_eth_dev *eth)
 553 {
 554         int len = 0;
 555         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 556         uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 557
 558         len = sh_eth_recv_start(eth);
 559         if (len > 0) {
 560                 invalidate_cache(packet, len);
 561                 net_process_received_packet(packet, len);
 562                 sh_eth_recv_finish(eth);
 563         } else
 564                 len = 0;
 565
 566         /* Restart the receiver if disabled */
 567         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 568                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 569
 570         return len;
 571 }
 572
 573 static int sh_eth_recv_legacy(struct eth_device *dev)
 574 {
 575         struct sh_eth_dev *eth = dev->priv;
 576
 577         return sh_eth_recv_common(eth);
 578 }
 579
 580 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
 581 {
 582         struct sh_eth_dev *eth = dev->priv;
 583         int ret;
 584
 585         ret = sh_eth_init_common(eth, dev->enetaddr);
 586         if (ret)
 587                 return ret;
 588
 589         ret = sh_eth_phy_config_legacy(eth);
 590         if (ret) {
 591                 printf(SHETHER_NAME ": phy config timeout\n");
 592                 goto err_start;
 593         }
 594
 595         ret = sh_eth_start_common(eth);
 596         if (ret)
 597                 goto err_start;
 598
 599         return 0;
 600
 601 err_start:
 602         sh_eth_tx_desc_free(eth);
 603         sh_eth_rx_desc_free(eth);
 604         return ret;
 605 }
 606
 607 void sh_eth_halt_legacy(struct eth_device *dev)
 608 {
 609         struct sh_eth_dev *eth = dev->priv;
 610
 611         sh_eth_stop(eth);
 612 }
 613
 614 int sh_eth_initialize(bd_t *bd)
 615 {
 616         int ret = 0;
 617         struct sh_eth_dev *eth = NULL;
 618         struct eth_device *dev = NULL;
 619         struct mii_dev *mdiodev;
 620
 621         eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 622         if (!eth) {
 623                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 624                 ret = -ENOMEM;
 625                 goto err;
 626         }
 627
 628         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 629         if (!dev) {
 630                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 631                 ret = -ENOMEM;
 632                 goto err;
 633         }
 634         memset(dev, 0, sizeof(struct eth_device));
 635         memset(eth, 0, sizeof(struct sh_eth_dev));
 636
 637         eth->port = CONFIG_SH_ETHER_USE_PORT;
 638         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 639         eth->port_info[eth->port].iobase =
 640                 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
 641
 642         dev->priv = (void *)eth;
 643         dev->iobase = 0;
 644         dev->init = sh_eth_init_legacy;
 645         dev->halt = sh_eth_halt_legacy;
 646         dev->send = sh_eth_send_legacy;
 647         dev->recv = sh_eth_recv_legacy;
 648         eth->port_info[eth->port].dev = dev;
 649
 650         strcpy(dev->name, SHETHER_NAME);
 651
 652         /* Register Device to EtherNet subsystem  */
 653         eth_register(dev);
 654
 655         bb_miiphy_buses[0].priv = eth;
 656         mdiodev = mdio_alloc();
 657         if (!mdiodev)
 658                 return -ENOMEM;
 659         strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 660         mdiodev->read = bb_miiphy_read;
 661         mdiodev->write = bb_miiphy_write;
 662
 663         ret = mdio_register(mdiodev);
 664         if (ret < 0)
 665                 return ret;
 666
 667         if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
 668                 puts("Please set MAC address\n");
 669
 670         return ret;
 671
 672 err:
 673         if (dev)
 674                 free(dev);
 675
 676         if (eth)
 677                 free(eth);
 678
 679         printf(SHETHER_NAME ": Failed\n");
 680         return ret;
 681 }
 682
 683 #else /* CONFIG_DM_ETH */
 684
 685 struct sh_ether_priv {
 686         struct sh_eth_dev       shdev;
 687
 688         struct mii_dev          *bus;
 689         phys_addr_t             iobase;
 690         struct clk              clk;
 691         struct gpio_desc        reset_gpio;
 692 };
 693
 694 static int sh_ether_send(struct udevice *dev, void *packet, int len)
 695 {
 696         struct sh_ether_priv *priv = dev_get_priv(dev);
 697         struct sh_eth_dev *eth = &priv->shdev;
 698
 699         return sh_eth_send_common(eth, packet, len);
 700 }
 701
 702 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
 703 {
 704         struct sh_ether_priv *priv = dev_get_priv(dev);
 705         struct sh_eth_dev *eth = &priv->shdev;
 706         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 707         uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
 708         int len;
 709
 710         len = sh_eth_recv_start(eth);
 711         if (len > 0) {
 712                 invalidate_cache(packet, len);
 713                 *packetp = packet;
 714
 715                 return len;
 716         } else {
 717                 len = 0;
 718
 719                 /* Restart the receiver if disabled */
 720                 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 721                         sh_eth_write(port_info, EDRRR_R, EDRRR);
 722
 723                 return -EAGAIN;
 724         }
 725 }
 726
 727 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
 728 {
 729         struct sh_ether_priv *priv = dev_get_priv(dev);
 730         struct sh_eth_dev *eth = &priv->shdev;
 731         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 732
 733         sh_eth_recv_finish(eth);
 734
 735         /* Restart the receiver if disabled */
 736         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 737                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 738
 739         return 0;
 740 }
 741
 742 static int sh_ether_write_hwaddr(struct udevice *dev)
 743 {
 744         struct sh_ether_priv *priv = dev_get_priv(dev);
 745         struct sh_eth_dev *eth = &priv->shdev;
 746         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 747         struct eth_pdata *pdata = dev_get_platdata(dev);
 748
 749         sh_eth_write_hwaddr(port_info, pdata->enetaddr);
 750
 751         return 0;
 752 }
 753
 754 static int sh_eth_phy_config(struct udevice *dev)
 755 {
 756         struct sh_ether_priv *priv = dev_get_priv(dev);
 757         struct eth_pdata *pdata = dev_get_platdata(dev);
 758         struct sh_eth_dev *eth = &priv->shdev;
 759         int ret = 0;
 760         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 761         struct phy_device *phydev;
 762         int mask = 0xffffffff;
 763
 764         phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
 765         if (!phydev)
 766                 return -ENODEV;
 767
 768         phy_connect_dev(phydev, dev);
 769
 770         port_info->phydev = phydev;
 771         phy_config(phydev);
 772
 773         return ret;
 774 }
 775
 776 static int sh_ether_start(struct udevice *dev)
 777 {
 778         struct sh_ether_priv *priv = dev_get_priv(dev);
 779         struct eth_pdata *pdata = dev_get_platdata(dev);
 780         struct sh_eth_dev *eth = &priv->shdev;
 781         int ret;
 782
 783         ret = sh_eth_init_common(eth, pdata->enetaddr);
 784         if (ret)
 785                 return ret;
 786
 787         ret = sh_eth_start_common(eth);
 788         if (ret)
 789                 goto err_start;
 790
 791         return 0;
 792
 793 err_start:
 794         sh_eth_tx_desc_free(eth);
 795         sh_eth_rx_desc_free(eth);
 796         return ret;
 797 }
 798
 799 static void sh_ether_stop(struct udevice *dev)
 800 {
 801         struct sh_ether_priv *priv = dev_get_priv(dev);
 802         struct sh_eth_dev *eth = &priv->shdev;
 803         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 804
 805         phy_shutdown(port_info->phydev);
 806         sh_eth_stop(&priv->shdev);
 807 }
 808
 809 static int sh_ether_probe(struct udevice *udev)
 810 {
 811         struct eth_pdata *pdata = dev_get_platdata(udev);
 812         struct sh_ether_priv *priv = dev_get_priv(udev);
 813         struct sh_eth_dev *eth = &priv->shdev;
 814         struct ofnode_phandle_args phandle_args;
 815         struct mii_dev *mdiodev;
 816         int ret;
 817
 818         priv->iobase = pdata->iobase;
 819
 820 #if CONFIG_IS_ENABLED(CLK)
 821         ret = clk_get_by_index(udev, 0, &priv->clk);
 822         if (ret < 0)
 823                 return ret;
 824 #endif
 825
 826         ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
 827         if (!ret) {
 828                 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
 829                                            &priv->reset_gpio, GPIOD_IS_OUT);
 830         }
 831
 832         if (!dm_gpio_is_valid(&priv->reset_gpio)) {
 833                 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
 834                                      GPIOD_IS_OUT);
 835         }
 836
 837         mdiodev = mdio_alloc();
 838         if (!mdiodev) {
 839                 ret = -ENOMEM;
 840                 return ret;
 841         }
 842
 843         mdiodev->read = bb_miiphy_read;
 844         mdiodev->write = bb_miiphy_write;
 845         bb_miiphy_buses[0].priv = eth;
 846         snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
 847
 848         ret = mdio_register(mdiodev);
 849         if (ret < 0)
 850                 goto err_mdio_register;
 851
 852         priv->bus = miiphy_get_dev_by_name(udev->name);
 853
 854         eth->port = CONFIG_SH_ETHER_USE_PORT;
 855         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 856         eth->port_info[eth->port].iobase =
 857                 (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
 858
 859 #if CONFIG_IS_ENABLED(CLK)
 860         ret = clk_enable(&priv->clk);
 861         if (ret)
 862                 goto err_mdio_register;
 863 #endif
 864
 865         ret = sh_eth_init_common(eth, pdata->enetaddr);
 866         if (ret)
 867                 goto err_phy_config;
 868
 869         ret = sh_eth_phy_config(udev);
 870         if (ret) {
 871                 printf(SHETHER_NAME ": phy config timeout\n");
 872                 goto err_phy_config;
 873         }
 874
 875         return 0;
 876
 877 err_phy_config:
 878 #if CONFIG_IS_ENABLED(CLK)
 879         clk_disable(&priv->clk);
 880 #endif
 881 err_mdio_register:
 882         mdio_free(mdiodev);
 883         return ret;
 884 }
 885
 886 static int sh_ether_remove(struct udevice *udev)
 887 {
 888         struct sh_ether_priv *priv = dev_get_priv(udev);
 889         struct sh_eth_dev *eth = &priv->shdev;
 890         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 891
 892 #if CONFIG_IS_ENABLED(CLK)
 893         clk_disable(&priv->clk);
 894 #endif
 895         free(port_info->phydev);
 896         mdio_unregister(priv->bus);
 897         mdio_free(priv->bus);
 898
 899         if (dm_gpio_is_valid(&priv->reset_gpio))
 900                 dm_gpio_free(udev, &priv->reset_gpio);
 901
 902         return 0;
 903 }
 904
 905 static const struct eth_ops sh_ether_ops = {
 906         .start                  = sh_ether_start,
 907         .send                   = sh_ether_send,
 908         .recv                   = sh_ether_recv,
 909         .free_pkt               = sh_ether_free_pkt,
 910         .stop                   = sh_ether_stop,
 911         .write_hwaddr           = sh_ether_write_hwaddr,
 912 };
 913
 914 int sh_ether_ofdata_to_platdata(struct udevice *dev)
 915 {
 916         struct eth_pdata *pdata = dev_get_platdata(dev);
 917         const char *phy_mode;
 918         const fdt32_t *cell;
 919         int ret = 0;
 920
 921         pdata->iobase = devfdt_get_addr(dev);
 922         pdata->phy_interface = -1;
 923         phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
 924                                NULL);
 925         if (phy_mode)
 926                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 927         if (pdata->phy_interface == -1) {
 928                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 929                 return -EINVAL;
 930         }
 931
 932         pdata->max_speed = 1000;
 933         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
 934         if (cell)
 935                 pdata->max_speed = fdt32_to_cpu(*cell);
 936
 937         sprintf(bb_miiphy_buses[0].name, dev->name);
 938
 939         return ret;
 940 }
 941
 942 static const struct udevice_id sh_ether_ids[] = {
 943         { .compatible = "renesas,ether-r7s72100" },
 944         { .compatible = "renesas,ether-r8a7790" },
 945         { .compatible = "renesas,ether-r8a7791" },
 946         { .compatible = "renesas,ether-r8a7793" },
 947         { .compatible = "renesas,ether-r8a7794" },
 948         { .compatible = "renesas,gether-r8a77980" },
 949         { }
 950 };
 951
 952 U_BOOT_DRIVER(eth_sh_ether) = {
 953         .name           = "sh_ether",
 954         .id             = UCLASS_ETH,
 955         .of_match       = sh_ether_ids,
 956         .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
 957         .probe          = sh_ether_probe,
 958         .remove         = sh_ether_remove,
 959         .ops            = &sh_ether_ops,
 960         .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
 961         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 962         .flags          = DM_FLAG_ALLOC_PRIV_DMA,
 963 };
 964 #endif
 965
 966 /******* for bb_miiphy *******/
 967 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 968 {
 969         return 0;
 970 }
 971
 972 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 973 {
 974         struct sh_eth_dev *eth = bus->priv;
 975         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 976
 977         sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
 978
 979         return 0;
 980 }
 981
 982 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 983 {
 984         struct sh_eth_dev *eth = bus->priv;
 985         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 986
 987         sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
 988
 989         return 0;
 990 }
 991
 992 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 993 {
 994         struct sh_eth_dev *eth = bus->priv;
 995         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 996
 997         if (v)
 998                 sh_eth_write(port_info,
 999                              sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
1000         else
1001                 sh_eth_write(port_info,
1002                              sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
1003
1004         return 0;
1005 }
1006
1007 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
1008 {
1009         struct sh_eth_dev *eth = bus->priv;
1010         struct sh_eth_info *port_info = &eth->port_info[eth->port];
1011
1012         *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
1013
1014         return 0;
1015 }
1016
1017 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
1018 {
1019         struct sh_eth_dev *eth = bus->priv;
1020         struct sh_eth_info *port_info = &eth->port_info[eth->port];
1021
1022         if (v)
1023                 sh_eth_write(port_info,
1024                              sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
1025         else
1026                 sh_eth_write(port_info,
1027                              sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
1028
1029         return 0;
1030 }
1031
1032 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
1033 {
1034         udelay(10);
1035
1036         return 0;
1037 }
1038
1039 struct bb_miiphy_bus bb_miiphy_buses[] = {
1040         {
1041                 .name           = "sh_eth",
1042                 .init           = sh_eth_bb_init,
1043                 .mdio_active    = sh_eth_bb_mdio_active,
1044                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
1045                 .set_mdio       = sh_eth_bb_set_mdio,
1046                 .get_mdio       = sh_eth_bb_get_mdio,
1047                 .set_mdc        = sh_eth_bb_set_mdc,
1048                 .delay          = sh_eth_bb_delay,
1049         }
1050 };
1051
1052 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);